CECC EIA Exxelia Temex Code Operating temperature range Storage temperature range Maximun C/ C over Temperature range without voltage applied Ageing

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Taping SCT Series : dimensions High Temperature Stacked Capacitors FEATURES Multilayer stacked ceramic capacitors Dielectric type II Capacitance range: 47 nf to 390 µf Voltage range: 50 V DC to 500 V

1 Taping SCT Series : dimensions High Temperature Stacked Capacitors FEATURES Multilayer stacked ceramic capacitors Dielectric type II Capacitance range: 47 nf to 390 µf Voltage range: 50 V DC to 500 V DC TERMINATIONS Ag 0% termination developed for high temperature up to 15 C. Less sensitive to thermal shocks and compatible with high melting point solder containing lead. DIL type J, L or N are available. MARKING Size Marking codes Example All sizes PACKAGING «TA» logo Cap code + Tolerance code Rated voltage value TA 5M 0 V ELECTRICAL SPECIFICATIONS CECC EIA Exxelia Temex Code Description Operating temperature range Storage temperature range Maximun C/ C over Temperature range without voltage applied Ageing «X» Series (type II) R1 X7R X 55 C to +15 C 55 C to +15 C ± 15%.5% per decade hour Dissipation Factor (DF).5% Voltage proof Insulation Resistance (IR) at 5 C under Ur Insulation Resistance (IR) at 15 C under Ur Measurement Conditions for C and DF at 0 C U R 00 V:.5 x U R U R > 00 V:.0 x U R 0GΩ or 00Ω.F whichever is the less GΩ or 0Ω.F whichever is the less 0pF: 1MHz / 1Vrms (no bias) > 0pF: 1KHz / 1Vrms (no bias) Capacitance versus applied Voltage and Temperature See page 99 «Blister» boxes: For all products, special «blister» boxes are used to optimize the protection of the parts during the carriage and the storage. Depending upon the termination (with or without connection) and the size, the number of the parts in each box is defined. Please, consult us for more details. HOW TO ORDER 01 SCT 01 X 5 K R - -RoHS Rated voltage Series Exxelia size code Dielectric code Capacitance Tolerance Termination Coating RoHS Compliant 500: 50 V 1: 0 V 01: 00 V 501: 500 V SCT X = X7R 1 st two digits represent significant figures; last digit specifies the number of zeros to follow. Examples: 4: 0.1µF 335: 3.3µF 156: 15µF 7: µf K = ±% M = ±0% DN DIL N type DJ DL DIL J type DIL L type RoHS = HMP tinned phosphor bronze, non magnetic. - = uncoated and no marking U = uncoated and marked Non-RoHS not available

2 High Temperature Stacked Capacitors General characteristics SCT Series DIMENSIONS in inches (mm) SC SERIES Dual In Line DIL termination DN Type DJ Type DL Type L L L 0.1 (.54) Ls TA 5M 0V 0.01 (0.5) W 0.0 (0.5) H ( 3.75) 0.1 (.54) Note: the marking shown here is just given as an example D Ls TA 5M 0V 0.01 (0.5) W 0.0 (0.5) H E D 0.1 (.54) Ls TA 5M 0V 0.01 (0.5) W 0.0 (0.5) H E Size L max. W max. SCT00 SCT01 SCT0 SCT04 SCT05 SCT06 SCT07 SCT SCT1 LS ± 0.0* (±0.5)* E ± 0.01 (±0.5)** D ± 0.0 (±0.5) (7.6) (7) (6.35) (1.8) () (.) (9.6) (7.6) (1.5) (.5) (11.9) (11.4) (.16) (1.5) (.5) (16.5) (14) (13.7) (1.5) (.5) (18.5) (17) (17.78) (1.5) (.5) (17.8) (1.6) (15.4) (1.5) (.5) (.7) (16.6) (0.3) (1.5) (.5) (13.) (7.5) (11.5) (.1) (.6) (40.6) (0.3) (.5) (.5) * Except for the SCT07, tolerance = ± 0.03 in (±0.8mm). ** For the SCT1, tolerance = ± 0.01 in (±0.3mm). Number of leads per side H max. Please, consult the tables of standard ratings Wires bending: max max DERATING RULES The given voltages in the below capacitance range are the nominal voltages at 15 C. For higher operating temperatures, the derating rules to be applied on the voltage versus temperature are defined as per the following table : HIGH TEMPERATURE 15 C 00 C 15 C 500V 00V 0V 00V 0V 50V 0V 50V 5V 50V 5V 16V 3 info@exxelia.com Page revised 09/17

3 Taping SCT Series : dimensions High Temperature Stacked Capacitors STANDARD RATINGS Exxelia size code SCT00 SCT01 SCT0 SCT04 U R 50 V 0 V 00 V 500 V 50 V 0 V 00 V 500 V 50 V 0 V 00 V 500 V 50 V 0 V 00 V 500 V 47 nf µf (3) (.1) (3) (.1) (3) (.1) (3) (.1) (1.8) (3) (.1) (.5) (3) (1.8) (3) (.1) (.5) (3) () (6.4) (.1) (.5) (3) (1.8) (1.8) () (6.4) (.1) (.1) (.1) (3.) (.1) (3) (1.8) (1.8) (.5) (6.4) (.1) (.1) (.1) (3.) (.1) (3) (1.8) (1.8) (.5) (9.6) (.1) (.1) (.1) (3.5) (.1) (3) (.5) (1.8) (1.8) (3) (9.6) (.1) (.1) (.1) (6.1) (.1) (.1) (.1) (3.3) (.5) (1.8) (1.8) (3) (1.8) (.1) (.1) (.1) (6.1) (.1) (.1) (.1) (3.5) (.5) (1.8) (1.8) (5.4) (1.8) (.1) (.1) (.1) (6.9) (.1) (.1) (.1) (3) () () (5.9) (14) (.1) (.1) (.5) (.5) (.1) (.1) (.1) (4.3) (3) () () (6.4) (16) (.1) (.1) (3) (.5) (.1) (.1) (.5) (7) (3) () () (8.1) (18) (.1) (.1) (3,5) (13.9) (.1) (.1) (.5) (9.9) (3) (3.5) (.) (.) (9.6) (.5) (.5) (4.4) (14.8) (.1) (.1) (3) (.3) (3) (4.) (.5) (.5) (1.8) (.5) (.5) (5.4) (17.6) (.1) (.1) (3.5) (14) (3) (6.4) (3) (3) (14) (.8) (.8) (6.6) (.1) (.1) (16) (3) (9.6) (4.4) (4.4) (16.4) (.8) (.8) (8.8) (.5) (.5) (5.9) (18) (.5) (.5) (3) (9.6) (5.1) (5.1) (16.4) (.8) (.8) (.8) (.5) (.5) (6.4) (18) (.5) (.5) (3) (9.6) (5.9) (5.9) (3.3) (3.3) (14) (.8) (.8) (6.4) (.5) (.5) (3.5) (1.8) (7.5) (7.5) (3.8) (3.8) (15) (.8) (.8) (9.6) (.5) (.5) (14.8) (8.6) (8.6) (6) (6.) (3.3) (3.3) (9.6) (.5) (.5) (6.4) (16.8) (9.6) (9.6) (6) (6.4) (3.5) (3.5) (1.8) (3) (3) (9.6) (1.3) (1.3) (7) (7.) (3.6) (3.6) (16) (3) (3) (9.6) (1.8) (1.8) (8.) (4.7) (4.7) (18) (3) (3) (11) (16) (16) (11) (11.) (7.) (9) (3.5) (3.5) (11.1) (1) (1.) (7.4) (9) (3.8) (3.8) (1.6) (14) (14.4) (.5) (1) (6.4) (6.4) (16) (11.1) (1.5) (7.) (8.1) (14.8) (15) (7.7) (.8) (15.) (15.) (1.8) (11.7) (1.8) (1) (14.8) (16) (16.8) Cap. code * Consult us - The height Hmax in inches (in mm) for the SCT Series is indicated in the cells. 4

4 High Temperature Stacked Capacitors General characteristics SCT Series STANDARD RATINGS Exxelia size code / SCT05 SCT06 / SCT07 SCT SCT11 U R 50 V 0 V 00 V 500 V 50 V 0 V 00 V 500 V 50 V 0 V 00 V 500 V 50 V 0 V 00 V 500 V 70 nf µf (.5) (.5) (.5) (.5) (3) (.5) (.5) (3) (.5) (.5) (3) (3.5) (.5) (3) (3) (3) (3.5) (.5) (.5) (.5) (3) (3) (3) (3) (3) (3.8) (.5) (.5) (.5) (3.5) (3.5) (3) (3) (3) (3.8) (.5) (.5) (.5) (3) (3) (3) (3) (6.4) (.5) (.5) (.5) (4.5) (3) (4.5) (3) (3) (3) (6.4) (.5) (.5) (.5) (6.9) (3) (6.9) (3) (3) (3.5) (6.4) (.5) (.5) (3) (7.9) (3) (9.6) (3) (3) (3.8) (7.4) (.5) (.5) (3) (8.4) (3) (.1) (3) (3) (9.6) (.5) (.5) (3.5) (11.1) (3) (3) (3.5) (1.8) (3) (3) (5.4) (1.8) (.5) (.5) (1.6) (3) (3) (14.8) (3) (3) (5.9) (14.8) (.5) (.5) (5.9) (16.8) (3) (3) (6.4) (14.8) (3) (3) (6.4) (14.8) (.5) (.5) (6.4) (0.8) (3) (3) (6.4) (16.8) (3) (3) (8.1) (16.8) (3) (3) (9.1) (3) (3) (9.6) (18,8) (3) (3) (9.6) (3) (3) (9.6) (3.5) (3.5) (9.6) (3.5) (3.5) (9.6) (3.5) (3.5) (1.8) (3.5) (3.5) (1,8) (3.5) (3.5) (1.8) (14.8) (3.5) (3.5) (1,8) (6.4) (6.4) (1.8) (6.4) (6.4) (3.7) (3.7) (16) (6.4) (6.4) (16.8) (6.4) (6.4) (6.4) (7.4) (18,8) (9.6) (9.6) (7.9) (9.6) (6.4) (8.) (18,8) (9.6) (9.6) (8.4) (9.6) (7.1) (.5) (1.8) (1.8) (11.6) (1.8) (9.6) (11.) (1.8) (1.8) (1.6) (1.8) (9.6) (11.8) (15) (15) (16.8) (17) (11.6) (1) (15) (15) (14.8) (15) Cap. code * 75 * 335 * 395 * 475 * 565 * 685 * * 85 * * 6 * * * 16 * * 156 * * 186 * * 6 * * * 76 * * * 336 * * 396 * * 476 * * 566 * * 686 HIGH TEMPERATURE * 86 * 7 * 17 * Consult us - The height Hmax in inches (in mm) for the SCT Series is indicated in the cells. 5 info@exxelia.com Page revised 09/17

5 Taping SCT Series : dimensions High Temperature Stacked Capacitors STANDARD RATINGS Exxelia size code SCT1 U R 50 V 0 V 00 V 500 V 50 V 0 V 00 V 500 V SCT18 Cap. code 680 nf µf * 85 * (1) * (1) * * (16) * 186 * * * * 6 7 * 0.47 (1) * * * (1) * * * (16) * * * * * * * * * * * * * * * * (1) * * * (1) 0.47 (1) * * (1) (16) * * (16) * * * * 7 70 * * * 397 * Consult us - The height Hmax in inches (in mm) for the SCT Series is indicated in the cells. 6

6 Taping General : dimensions Information High temperature capacitors are made of class 1 or class ceramic dielectrics featuring special compositions based upon high purity oxides to reduce ionic conduction inherent to the presence of atoms such as sodium. In addition, all quality controls carried out at intermediate and final production stages (lot acceptance test under U RC and insulation resistance measurement at operating temperature) are the assurance of enhanced reliability. High temperature capacitors include : chip class 1 (CEC 03 to CEC 33) and class (CNC 03 to 33), encapsulated radial leads class 1 and (TCE / TCN 01 to 04), encapsulated axial leads class 1 and (TCE / TCN 5 to 54), selfprotected radial leads class 1 and (TCE / TCN 1 to 16) and radial leads class 1 and (TCE / TCN 63). Mechanical stress is eliminated with replacement of epoxy by selfprotected ceramic. This also allows the increase of the capacitance ranges and improves the reliability. high voltage varnished capacitors (TCH 79 to 85) high capacitance value SCT Series. They are highly recommended for operation at temperatures of up to 00 C. Capacitors specifically designed for higher operating temperatures (e.g. TCE / TCN 1 to 16 and TCE / TCN 63 to 66) are also available. High temperature capacitors are made of class 1 or class ceramic dielectrics featuring special compositions based upon high purity oxides to reduce ionic conduction inherent to the presence of atoms such as sodium. In addition, all quality controls carried out at intermediate and final production stages (lot acceptance test under 0.5 U RC and insulation resistance measurement at 00 C) are the assurance of enhanced reliability. TYPICAL CURVES: CE / CN Series, TCE / TCN Series, TCH Series NPO: TYPICAL CAPACITANCE VARIATION VERSUS TEMPERATURE NPO: TYPICAL INSULATION RESISTANCE VERSUS TEMPERATURE 0.8 C/C (%) Insulation resistance (MΩ.µF) Typical Limit X7R: TYPICAL CAPACITANCE VARIATION VERSUS TEMPERATURE X7R: TYPICAL INSULATION RESISTANCE VERSUS TEMPERATURE 5 C/C (%) 000 Insulation resistance (MΩ.µF) Temperature coefficient without voltage Temperature coefficient at full rated voltage

7 General General characteristics Information TYPICAL CURVES: SCT Series C/C VERSUS APPLIED VOLTAGE AND RATED VOLTAGE (U R ) CAPACITANCE VERSUS TEMPERATURE C/C (%) C/C (%) U R = 0V U R = 00V U R = 500V Voltage (V) DIELECTRIC LOSSES VERSUS TEMPERATURE INSULATION RESISTANCE VERSUS TEMPERATURE 3,5 DF (%) 0000 RI (Ω.F) HIGH TEMPERATURE 99 info@exxelia.com Page revised 09/17

Taping Ceramic : dimensions Capacitors Technology MLCC STRUCTURE Tin Tin / Lead Gold (Solderable layer) Terminations EQUIVALENT CIRCUIT Ceramic Electrodes Margins Silver or Silver / Palladium

8 Taping Ceramic : dimensions Capacitors Technology MLCC STRUCTURE Tin Tin / Lead Gold (Solderable layer) Terminations EQUIVALENT CIRCUIT Ceramic Electrodes Margins Silver or Silver / Palladium (electrodes contact layer) Polymer (crack protection layer) Nickel or Copper barrier (leaching protection layer) Capacitor is a complex component combining resistive, inductive and capacitive phenomena. A simplified schematic for the equivalent circuit is: IR Ls Rs C DIELECTRIC CHARACTERISTICS Insulation Resistance (IR) is the resistance measured under DC voltage across the terminals of the capacitor and consists principally of the parallel resistance shown in the equivalent circuit. As capacitance values and hence the area of dielectric increases, the IR decreases and hence the product (C x IR) is often specified in Ω.F or MΩ.µF. The Equivalent Series Resistance (ESR) is the sum of the resistive terms which generate heating when capacitor is used under AC voltage at a given frequency (f). Dissipation factor (DF) is the ration of the apparent power input will turn to heat in the capacitor: DF = π f C ESR When a capacitor works under AC voltage, heat power loss (P), expressed in Watt, is equal to: P = π f C Vrms DF The series inductance (Ls) is due to the currents running through the electrodes. It can distort the operation of the capacitor at high frequency where the impedance (Z) is given as: Z = Rs + j (Ls.q - 1 (C.q)) with q = πf When frequency rises, the capacitive component of capacitors is gradually canceled up to the resonance frequency, where : Z = Rs and LsC.q = 1 Above this frequency the capacitor behaves like an inductor. Dielectric material P0 NPO N00 (C4xx) BX C1 X7R Porcelain Magnesium titanate or Neodynium baryum titanate Barium zirconate titanate Baryum titanate (BaTiO 3 ) Dielectric constant ,000 5,000 Electrode technology PME (Precious Metal Electrodes): Ag/Pd Capacitance variation between 55 C and +15/ C without DC voltage Capacitance variation between 55 C and +15/ C with DC rated voltage (0±30)ppm/ C (0±30)ppm/ C (,00±500) ppm/ C ±15% ±0% ±15% 0-15% 15% 5% 0% 30% Piezo-electric effect None None Yes Dielectric absorption None Few % Few % Thermal shock sensitive Not applicable 8

MANUFACTURING STEPS CERAMIC CAPACITORS Ceramic General Capacitors characteristics Technology GENERAL INFORMATION SLIP CASTING ELECTRODE SCREEN PRINTING STACKING A slurry, a mix of ceramic powder,

The electrode ink, made from a metal powder mixed with solvents, is printed onto the ceramic sheets using a screen printing process.

9 MANUFACTURING STEPS CERAMIC CAPACITORS Ceramic General Capacitors characteristics Technology GENERAL INFORMATION SLIP CASTING ELECTRODE SCREEN PRINTING STACKING A slurry, a mix of ceramic powder, binder and solvents, is poured onto conveyor belt inside a drying oven, resulting in a dry ceramic sheet. The electrode ink, made from a metal powder mixed with solvents, is printed onto the ceramic sheets using a screen printing process. The sheets with electrode printed are stacked to create a multilayer structure. TERMINATIONS SINTERING PRESSING Each terminal of the capacitor is dipped in the termination ink, mix of metal powder, solvents and glass frit and the parts are fired in an oven. The parts are sintered in an oven with a precise temperature profile which is very important to the characteristics of the capacitors. Pressure is applied to the stack to fuse all the separate layers, this created a monolithic structure. TERMINATIONS PLATING FINAL TESTING PACKAGING Stacking + leads soldering + encapsulation (see pages -11) 9 info@exxelia.com Page revised 09/17

10 Taping User Guide : dimensions SMD TERMINATIONS NON RoHS COMPLIANT Code RoHS COMPLIANT Code Magnetic Epoxy bonding Iron soldering Recommended mounting process Wave soldering Vapor phase soldering Infrared soldering Wire bonding Ag Q Ag QW / P No 18 Ag/Pd/Pt - Ag/Pd/Pt W / A No 4 Ag + Ni + dipped Sn/Pb 60/40 Ag/Pd/Pt + dipped Sn/Pb 60/40 Ag + Ni + electrolytic Sn/Pb 95/5 Ag + Ni + electrolytic Sn/Pb 60/40 T** - - No 4 H C - - Ag + Ni + dipped Sn/Pb 60/40 Ag/Pd/Pt + dipped Sn Ag + Ni + electrolytic Sn Storage (months)* HW No 4 CW / S Yes 18 D - - Yes 18 E Ag + Cu + electrolytic Sn Ag + Ni + electrolytic Sn C*** No 18 EW Yes 4 Ag + Ni + Au G Ag + Ni + Au GW Yes 36 Ag + Polymer + Ni + Sn/Pb 95/5 Ag + Polymer + Ni + Sn/Pb 60/40 Ag + Polymer + Ni + Au YC Ag + Polymer + Ni + Sn YCW Yes 18 YD - - Yes 18 YG Ag + Polymer + Ni + Au YGW Yes 36 Nickel (Ni) or Copper (Cu) barriers amplify thermal shock and are not recommended for chip sizes larger than * Storage must be in a dry environment at a temperature of 0 C with a relative humidity below 50%, or preferably in a package enclosing a desiccant. ** Maintenance only. *** Non magnetic chips series only. SMD ENVIRONMENTAL TESTS Ceramic chip capacitors for SMD are designed to meet test requirements of CECC 30 and NF C standards as specified below in compliance with NF C 0700 and IEC 68 standards: Solderability: NF C 0758, 60 C, bath 6/36/. Adherence: 5N force. Vibration fatigue test: NF C 0706, 0 g, Hz to,000 Hz, 1 cycles of 0 minutes each. Rapid temperature change: NF C 0714, 55 C to + 15 C, 5 cycles. Combined climatic test: IEC Damp heat: NF C 0703, 93 %, H.R., 40 C. Endurance test: 1,000 hours, 1.5 U RC, 15 C. STORAGE OF CHIP CAPACITORS TINNED OR NON TINNED CHIP CAPACITORS Storage must be in a dry environment at a temperature of 0 C with a relative humidity below 50 %, or preferably in a packaging enclosing a desiccant. STORAGE IN INDUSTRIAL ENVIRONMENT: years for tin dipped chip capacitors, 18 months for tin electroplated chip capacitors, years for non tinned chip capacitors, 3 years for gold plated chip capacitors. STORAGE IN CONTROLLED NEUTRAL NITROGEN ENVIRONMENT: 4 years for tin dipped or electroplated chip capacitors, 4 years for non tinned chip capacitors, 5 years for gold plated chip capacitors. Storage duration should be considered from delivery date and not from batch manufacture date. The tests carried out at final acceptance stage (solderability, susceptibility to solder heat) enable to assess the compatibility to surface mounting of the chips.

11 LEAD STYLES CERAMIC CAPACITORS General characteristics User Guide GENERAL INFORMATION SURFACE MOUNTING TROUGH-HOLE MOUNTING DIL LEADS AXIAL AND RADIAL P style PL style Radial leads (Type 6) Radial leads (4 leads) L style J style Axial leads (Type 7) DIL leads: N style RIBBON LEADS Micro-strip (type 1) Short Micro-strip (type 1S) Axial (Type ) ENCAPSULATION STYLES Radial (Type 3) R style Ceramic encapsulation (selfprotected) Varnish RX style RJ style Conformal coating Molding Please contact Exxelia sales for any lead configuration not shown info@exxelia.com Page revised 09/17

12 Taping User Guide : dimensions SOLDERING ADVICES FOR REFLOW SOLDERING l 3 l l1 Large chips above size 5 are not recommended to be mounted on epoxy board due to thermal expansion coefficient mismatch between ceramic capacitor and epoxy. Where larger sizes are required, it is recommended to use components with ribbon or other adapted leads so as to absorb thermo-mechanical strains. Dimensions in inches (in mm) Reflow soldering Wave soldering I 1 I I 3 I 1 I I (1.1) (0.9) 0.01 (0.3) (1.1) (1.) 0.01 (0.3) (1.4) (0.9) 0.01 (0.3) (1.4) (1.) 0.01 (0.3) (1.6) (1.3) (0.4) (1.6) (1.6) (0.4) (1.4) (1.5) 0.0 (0.5) (1.4) (1.8) 0.0 (0.5) (1.85) (1.65) 0.04 (0.6) (1.85) (1.95) 0.04 (0.6) (.4) (1.65) (0.9) (.4) (1.95) (0.9) (1.85) (1.7) (1) (1.85) () (1) (.1) (1.7) (1.5) (.1) () (1.5) (3) (1.75) (1.5) (3) (.05) (1.5) (1.85) (1.8) (.) (1.85) (.1) (.) (.) (1.85) 0. (.6) (.) (.15) 0. (.6) (3.85) (1.85) 0. (.6) 0.15 (3.85) (.15) 0. (.6) (7.15) (1.85) 0. (.6) 0.81 (7.15) (.15) 0. (.6) 0.13 (3.3) () (3.7) 0.13 (3.3) (.3) (3.7) (5.8) () (3.7) 0.8 (5.8) (.3) (3.7) (7.15) () (3.7) 0.81 (7.15) (.3) (3.7) RECOMMENDED FOOTPRINT FOR SMD CAPACITORS Ceramic is by nature a material which is sensitive both thermally and mechanically. Stresses caused by the physical and thermal properties of the capacitors, substrates and solders are attenuated by the leads. Wave soldering is unsuitable for sizes larger than 0 and for the higher ends of capacitance ranges due to possible thermal shock (capacitance values given upon request). Infrared and vapor phase reflow, are preferred for high reliability applications as inherent thermo-mechanical strains are lower than those inherent to wave soldering. Whatever the soldering process is, it is highly recommended to apply a thermal cycle, see hereafter our recommended soldering profile: RECOMMENDED VAPOR PHASE REFLOW PROFILE RECOMMENDED IR REFLOW PROFIL RECOMMENDED WAVE SOLDERING PROFILE >50 C/s 0 C 0 15 C 50 C Preheat zone Natural cool down RoHS No RoHS Time (min) C 0 15 C-5 C 45 C-55 C Natural cool down RoHS No RoHS Time (min) C 50 C 80 C Natural cool down RoHS No RoHS Time (min) 1

13 SOLDERING ADVICES FOR IRON SOLDERING Attachment with a soldering iron is discouraged due to ceramic brittleness and the process control limitations. In the event that a soldering iron must be used, the following precautions should be observed: Use a substrate with chip footprints big enough to allow putting side by side one end of the capacitor and the iron tip without any contact between this tip and the component, place the capacitor on this footprint, heat the substrate until the capacitor s temperature reaches 150 C minimum (preheating step, maximum 1 C per second), place the hot iron tip (a flat tip is preferred) on the footprint without touching the capacitor. Use a regulated iron with a 30 watts maximum power. The recommended temperature of the iron is 70 ± C. The temperature gap between the capacitor and the iron tip must not exceed 10 C, CERAMIC CAPACITORS General characteristics User Guide leave the tip on the footprint for a few seconds in order to increase locally the footprint s temperature, use a cored wire solder and put it down on the iron tip. In a preferred way use Sn/Pb/Ag 6/36/ alloy, wait until the solder fillet is formed on the capacitor s termination, take away iron and wire solder, wait a few minutes so that the substrate and capacitor come back down to the preheating temperature, solder the second termination using the same procedure as the first, let the soldered component cool down slowly to avoid any thermal shock. GENERAL INFORMATION PACKAGING TAPE AND REEL The films used on the reels correspond to standard IEC Films are delivered on reels in compliance with document IEC 86-3 dated Minimum quantity is 50 chips. Maximum quantities per reel are as follows: Super 8 reel - Ø 180:,500 chips. Super 8 reel - Ø 330:,000 chips. Super 1 reel - Ø 180: 1,000 chips. Reel marking complies with CECC 30 standard: Model. Rated capacitance. Capacitance tolerance. Rated voltage. Batch number. TRAY PACKAGES E A D Chips tray depth: C D B E DIMENSIONAL CHARACTERISTICS OF CHIPS TRAY PACKAGES Sizes Nr. of chips/ package Oriented chips No No Yes Yes Yes No 1 0 Yes No 5 Yes 0 Yes 5 Yes Dimensions in inches (in mm) A B C D E Ø 0.11 (Ø 3.0) (1.65) (4.4) Ø 0.11 (Ø 3.0) (1.65) (4.4) (1.5) (1.14) (0.89) (4.4) 0.1 (.54) 0.06 (1.5) (1.14) (4.4) 0.1 (.54) 0.06 (1.5) (1.14) (4.4) 0.14 (3.56) 0.14 (3.56) 0.06 (1.5) (4.4) 0.14 (3.56) 0.14 (3.56) 0.06 (1.5) (4.4) 0.5 (6.35) 0.5 (6.35) 0.13 (3.3) (8.76) 4 (1.6) 0.4 (6.1) 0.65 (6.73) 0.07 (1.78) (8.76) 0.5 (6.35) 0.5 (6.35) 0.13 (3.3) (8.76) 4 (1.6) 0.4 (6.1) 0.65 (6.73) 0.07 (1.78) (8.76) 13 info@exxelia.com Page revised 09/17

14 Taping User Guide : dimensions EIA STANDARD CAPACITANCE VALUES Following EIA standard, the values and multiples that are indicated in the chart below can be ordered. E48, E96 series and intermediary values are available upon request. PART MARKING VOLTAGE CODES Use the following voltage code chart for part markings: E6 (± 0%) E1 (± %) E4 (± 5%) Voltage (V) Code Letter code 5 50 A B C D 0 1 E G H K L 1,000 M,000 0 P 3, R 4, S 5, T 7, U,000 3 W EIA CAPACITANCE CODE The capacitance is expressed in three digit codes and in units of pico Farads (pf). The first and second digits are significant figures of the capacitance value and the third digit identifies the multiplier. For capacitance value < pf, R designates a decimal point. See examples below: EIA code Capacitance value in pf in nf in µf R R , , , , , , ,300,000 3, ,00,000 8, ,000,000 15, ,000,000 68, ,000,000 0, ,000,000 0,000 0 PART MARKING TOLERANCE CODES Use the following tolerance code chart for part markings: Tolerance Letter code ±0.5pF CU ±0.5pF DU ±1pF FU ±1% F ±% G ±5% J ±% K ±0% M 14

15 RELIABILITY LEVELS Exxelia proposes different reliability levels for the ceramic capacitors for both NPO and X7R ceramics. CERAMIC CAPACITORS General characteristics User Guide GENERAL INFORMATION CECC EXXELIA TECHNOLOGIES chips capacitors are qualified according to CECC ESA ESCC EXXELIA TECHNOLOGIES chips capacitors are qualified (QPL) according to ESCC n 3009 (chips) and ESCC n 3001 (leaded) Æ Æ Æ Standard CoC Standard Æ Æ Æ F Æ Æ Æ Æ Æ T5 0% electrical and visual control Voltage proof Insulation Resistance Capacitance value Dissipation factor Æ Æ Æ Æ Æ Æ Æ T6 Only for rated voltage <500V Rapid Change of Temperature cycles 55 C +15 C CoC F Burn-in (0% control) 168 h, 15 C, 1.5 Un CoC T5 Solderability Test On parts Rapid Change of Temperature 5 cycles 55 C +15 C Damp Heat 85 C 85 % RH 40 h 1.5 V On 40 parts CoC T6 Æ Æ Æ Æ Level FM IN PROCESS control According ESCC n 3009/3001 Chart F According ESCC n 3009/3001 Chart F3 According ESCC n 3009/3001 Æ Documentation: according ESCC n 3009/ info@exxelia.com Page revised 09/17

Operating temperature Maximum C/C over temperature range without DC voltage applied

Operating temperature Maximum C/C over temperature range without DC voltage applied Planar Arrays General characteristics BPM Series FEATURES Planar capacitor arrays X7R dielectrics (NPO available on request) Capacitance range: 330pF - 68nF Voltage range: 5V DC to 00V DC Specific configurations