Quantum Memory Hierarchies

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1 Quantum Memory Hierarchies Efficient Designs that Match Available Parallelism in Quantum Processors Darshan D. Thaker Tzvetan S. Metodi UC Davis Andrew W. Cross Issac L. Chuang MIT Frederic T. Chong UC Santa Barbara

2 Motivation Study tradeoffs between area - reliability - performance. Goals of this research: Reduce overall area of the design. Leverage conventional architectural techniques to improve performance. Provide abstractions for further research.

3 Outline Background and prior work. Overview of quantum error correction codes. Specialization into memory and compute regions. Improving performance. Results and discussion.

4 Ion-Traps Ion trapping region T-junction Use ions trapped in electromagnetic fields. Lasers acting on ions induce quantum gates. Courtesy: C.Monroe at U.Michigan Newer traps are micromachined.

5 Quantum Logic Array Single logical qubit Compute-anywhere design. Sea of lower level qubits R Q Q Q R R Teleportation based longdistance communication. Q R Q Q Q R R Exponential speedup when factoring large numbers. Repeaters Unresolved Issue: Size

6 Quantum Logic Array Sea of qubits design. Teleportation based longdistance communication. Exponential speedup when factoring large numbers. QLA: 90cm x 90cm Unresolved Issue: Size

7 Design Pyramid QLA Area Reliability Speed

8 Outline Background and prior work. Overview of quantum error correction codes. Specialization into memory and compute regions. Improving performance. Results and discussion.

9 Comparison with Classical Codes Classical three bit code Equivalent quantum code Single bit encoded as three bits. Majority Voting. Nine qubit Shor code Protects against bit-flips and phase-flips.

10 Comparison with Classical Codes Classical three bit code Equivalent quantum code Single bit encoded as three bits. Majority Voting. Nine qubit Shor code Protects against bit-flips and phase-flips.

11 Greater Reliability Need greater reliability than provided by encoding a single time. The No cloning theorem and restrictions on measurement require greater reliability. Cannot use methods like checkpointing or make duplicates. Solution: Use concatenated codes.

12 Concatenated Codes 1 logical qubit Level 1: 7 physical qubits Reliability increases doubly exponentially. Exponentially slower. Exponentially greater resources. Level 2: 49 physical qubits Concatenated Steane Code

13 Outline Background and prior work. Overview of quantum error correction codes. Specialization into memory and compute regions. Improving performance. Results and discussion.

14 Quantum Logic Array Sea of lower level qubits Q Q Q Sea of lower level qubits Q Q Q R R R R R R R Q Q Q Q Q Q Q Q R R R R R R R Conventional wisdom: Max. parallelism necessary to minimize computation time and reduce prob. of failure.

15 Modular Exponentiation Shor s quantum algorithm to find factors of very large numbers yields exponential speedup over classical algorithms. Modular exponentiation is the most compute intensive part of Shor s factoring algorithm. Primary component: Draper carry-lookahead adder (quantum version of the classical adder).

16 App. Constrained Parallelism Create slower but denser memory region and faster but sparse compute region.

17 Specialization Compute Region Memory Region Ancilla : Data 2 : 1 Ancilla : Data 1 : 8 Logical data qubits Logical ancilla qubits An ion when idle has a lifetime of ~10 sec

18 CQLA: Compressed QLA Memory Block Compute Block

19 Area Reduction 10.0 Area Reduced Perf. Change 9.1 Factor of bit 256-bit 512-bit 1024-bit Shor s Alg. Input Size -20%

20 CQLA: Reduced Size CQLA: 28cm x 28cm QLA: 90cm x 90cm

21 Design Pyramid: CQLA CQLA QLA Area Reliability Speed

22 Outline Background and prior work. Overview of quantum error correction codes. Specialization into memory and compute regions. Improving performance. Results and discussion.

23 Concatenated Codes 1 logical qubit Level 1: 7 physical qubits Reliability increases doubly exponentially. Exponentially slower. Exponentially greater resources. Level 2: 49 physical qubits Concatenated Steane Code

24 Level 1 Level 2 Encoding Memory: Very reliable and slow. (Periodic error-correction) Compute: Very reliable and fast. (49bit quantum operations and error-correction) Transfer between encoding levels Level 1 Encoding Cache: Less reliable. (Infrequent Error-correction) Compute: Less reliable, exponentially faster. (7bit quantum operations and error-correction)

25 Faster CQLA Level 1 Level 1 Memory Block Compute Block

26 Overall Results Area Reduced L1 SpeedUp Total SpeedUp Factor of bit 512-bit 1024-bit Shor s Alg. Input Size

27 Design Pyramid: QLA QLA Area Reliability Speed

28 Design Pyramid: CQLA CQLA QLA Area Reliability Speed

29 Design Pyramid: CQLA v2 CQLA v2 QLA Area Reliability Speed

30 Discussion Parallelism in quantum computing constrained by applications. Different scheduling mechanisms of quantum operations. Introduced a memory hierarchy for quantum computers. Area reduced factor of 9 and speedup of factor of 4.

31 Discussion - 2 Even better results using the Bacon-Shor quantum errorcorrection code.! Area reduced by a factor of 13.! Speedup of factor of 8. Details of transfer networks to enable change in encodings.

32 Future Work Limited control signals: Incorporate studies of laser resources and laser power. Incorporating fault tolerance into compiler optimization: Compiler techniques to reduce error-correction costs.

33 Questions? Project webpage: Your questions...

34 Overall Results

35 Concatenated Codes 1 logical qubit Level 1: 9 physical qubits Reliability increases doubly exponentially. Exponentially slower. Exponentially greater resources. Level 2: 81 physical qubits

36 Improve Performance Let memory remain at Level 2 encoding. Compute at Level 1 encoding. Drawbacks: Reliability degrades. Transfer between Level 1 and Level 2 is very expensive. Use a cache to alleviate transfer costs.

37 Size Reduction Input Size Compute Blocks Area Reduced (Factor of) Speed Up 64-bit 256-bit 512-bit 1024-bit

38 Overall Results Parallel Transfers Input Size L1 Speed Up L2 Speed Up Total Speed Up Area Reduced (Factor of)

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