WHY DO SIMPLE WAFER FAB MODELS FAIL IN CERTAIN SCENARIOS? Oliver Rose. Institute of Computer Science University of Würzburg Würzburg, GERMANY

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1 Proceedngs of the 2 Wnter Smulaton Conference J. A. Jones, R. R. Barton, K. Kang, and P. A. Fshwck, eds. WHY DO SIMPLE WAFER FAB MODELS FAIL IN CERTAIN SCENARIOS? Olver Rose Insttute of Computer Scence Unversty of Würzburg 9774 Würzburg, GERMANY ABSTRACT Prevous work has proved that smple smulaton models are suffcent for analyzng the behavor of complex wafer fabs n certan scenaros. In ths paper, we gve an example where the smple model fals to accurately predct cycle tmes and WIP levels of the complex model. To determne the reason for ths behavor, we analyze the correlaton propertes of a full fab model and the correspondng smple one. It turns out that the smple model s not capable of capturng the correlatons n an adequate way because there s lot overtakng (passng) n the smple model whle almost no overtakng can be found n the complex counterpart. 1 INTRODUCTION In some recent papers, smple smulaton models are successfully used to explan the behavor of wafer fabs (Rose 1998) or to predct ther performance measures such as product cycle tmes (Rose 1999a). The smple model reproduces only the behavor of the bottleneck workcenter n detal whle all other machnes are aggregated nto delays wth adequate dstrbutons. Each lot vsts the bottleneck as often as t would do n a real fab. By desgn, ths knd of model mmcs the dependence of the fab capacty on the bottleneck propertes and the cyclc fashon of producton, two of the major constrants of wafer fabrcaton. We found, however, that as soon as lot release regulaton, e.g., CONWIP (CONstant Work In Progress) (Wen 1988, Hopp and Spearman 1991), s mplemented the smple model fals n predctng WIP and cycle tme of the complex model. Ths happens despte the fact that the delay dstrbutons of the smple and complex model are almost dentcal. We conjecture that correlaton between the delays must also have an mportant mpact on the performance of the models. Therefore, we analyze n detal the correlaton propertes of the (Measurement and Improvement of Manufacturng Capacty) full fab model (Fowler and Robnson 1995) and the smple model and reason on the cause of the dfferences found. The paper s organzed as follows. Secton 2 ntroduces the and the smple smulaton model. We show the man results from the CONWIP smulaton study where the smple model fals. In Secton 3, we provde the measures that we use for our correlaton analyss. Then, dfferent types of dependences between lots are ntroduced and examned. Secton 4 deals wth overtakng of lots as the man reason for the presence of correlaton n wafer fab models. 2 SIMULATION MODELS 2.1 Models Ths secton presents the wafer fab smulaton models we used to derve our smplfed models. As we had no possblty to analyze real world data from a semconductor wafer fabrcaton faclty we produced such data by usng one of the model sets and the Factory Explorer smulaton tool (Wrght Wllams & Kelly 1997). These factory-level data sets are freely avalable at the SEMATECH (SEmconductor MAnufacturng TECHnology) FTP-Server ftp://ftp.sematech.org/pub/datasets. We chose model 6 as reference for our smulaton studes. It conssts of 228 workstatons that perform 14 dfferent processng steps. A total of 9 dfferent products are bult n ths fab. The nput rate was set to 95% of the approxmate maxmum that was estmated by Factory Explorer s capacty analyss whch s run before the smulaton. We dd not use lower nput rates, because they would decrease the mpact and the dfferences between constant and CONWIP lot release rules. Each tool group n the model uses the FIFO dspatch rule (Frst In Frst Out). Because of modelng restrctons n our smple models we had to make changes to the model. Frst of all we do not model operator avalablty. Operators are normally used n the producton process to load and unload the workstatons wth lots, to set up the machnes and to supervse the producton. We assume n our models that there s always an nfnte number of operators avalable. 1481

2 The second change we mplemented focuses on the scrap a machne produces. Wth a probablty of.4% each machne makes the lot t currently processes unusable. Ths happens very rarely and has no consderable mpact on the overall fab performance. Therefore, the fab was smplfed n such a way that t produces no scrap at all. As the smple model ntroduced n the next secton only has product sequences, whch enter and leave the man bottleneck workstaton, we have to remove all products from the model, that do not have the bottleneck n ther processng sequence. These are the products wth numbers 2, 7 and 8. Therefore we have models wth sx dfferent product types (1, 3, 4, 5, 6, 9). The removal of these 3 products does not change the locaton of bottleneck. If we want to study nter-cycle correlaton alone we remove all producton processes except for product 1. Ths enables us to swtch off nter-product correlaton. Of course t s possble to observe nter-cycle correlaton n the orgnal fab, but n ths case the correlaton curve s always a mxture of both types of correlatons. 2.2 Smple Models In ths secton, we brefly descrbe a smple model for a wafer fabrcaton faclty, whch was ntroduced n (Rose 1998). Ths model ntends to reduce the requred toolgroups n a fab to a mnmum. Nevertheless, ths model stll tres to capture the behavor of the complex fabrcaton faclty Basc Smple Model Fgure 1 depcts the bottleneck workstaton whch s the most mportant part n ths model and n the real fab because t lmts the throughput. It s the workstaton named 254_CAN_.43_MII n the fab 6. Ths toolgroup processes each lot separately. Hence, there s no need to model batches n our smple model and we can use lots as the smallest entty n our models. Delay Cycle experence as t passes through the tool-groups ncludng the processng and the watng tme n queues defned by the subsequences n the producton process. The Delay In group covers the delay a lot needs from enterng the fab untl t reaches the bottleneck for the frst tme. The Delay Cycle group models the delay a lot needs after leavng the bottleneck and before enterng t the next tme. It s very lkely that the sequence s dfferent for two bottleneck entres. So we need to know how often the bottleneck has been vsted by a lot. When a lot completes ts fnal bottleneck processng step t enters the thrd delay group that s left as soon as the producton of ths lot s fnshed. Next, we take a closer look at the desgn of the delay groups. As prevously mentoned, each group represents a subset of the producton process. For each product and group we receve a set of delay tmes whch occurred durng the Factory Explorer smulaton. Now, t s possble to buld hstograms from these data sets and use them as a dscrete dstrbuton to sample delay values n the smple model. Another way s to estmate the parameters of a gven dstrbuton type based on the hstogram data. We use Gamma varates because those dstrbuton types cover a wde range of shapes and are a good ft for most of the smulaton data. In the smple fab models we apply the three parameter Gamma dstrbuton Gamma(α, β, γ ) wth shape, scale, and locaton parameters α, β, and γ, respectvely. It has the densty β ) f(x; α, β, γ ) = (x γ)α 1 exp( x γ β α Ɣ(α). (1) The three parameters are determned by a fttng process such as the nonlnear least-squares (NLLS) Marquardt- Levenberg algorthm. A detaled explanaton and mplementaton of ths method can be found n Press et al. (1992). Fgure 2 shows the dstrbuton of the delay n group for the frst product and the resultng Gamma densty functon after the fttng process. The dstrbuton s plotted as a hstogram where the vertcal lne shows the dstrbuton s mean. All smple models were mplemented wth the ARENA smulaton tool (Kelton et al. 1997) Smple Model wth CONWIP Rule fnshed? The smple model has to be modfed n order to run the factory wth a CONWIP rule (Fgure 3). In ths new model Delay In Queue Delay Out the lots are released n constant tme ntervals, but f the Bottleneck upper lot lmt for a product s reached all lots of ths product Fgure 1: Smple Wafer Fab Model have to wat n the queue n front of the fab untl a lot of ths product fnshes processng and leaves the system. There are three addtonal groups. These are the Delay If the lot lmts are set too hgh ths model behaves In group, the Delay Cycle group and the Delay as the basc smple model wthout WIP control. If the Out group. Each group represents the delay a lot has to lmts are set close to or below the average number of lots 1482

3 Frequency Delay dstrbuton Ftted functon Delay (hours) Fgure 2: Delay Dstrbuton of Product 1 n the Frst Delay Group and Gamma Densty Functon Estmate Delay In Delay Cycle Queue Bottleneck Fxed WIP fnshed? Delay Out Fgure 3: Smple Wafer Fab Model Wth WIP Control n the system there s a fxed number of lots n the system. An nventory level can be specfed n the Factory Explorer smulatons n the same way. Therefore we can compare ths release rule for both the complex factory and the smple model. 2.3 Smulaton Parameters For each model the smulated perod s 1 years. The frst year s consdered as the warmup phase and ts results are dscarded. We requred such a long smulaton perod to obtan enough data for the estmaton of all delay dstrbutons of the smple model. For the smulatons wth CONWIP lot release we defned sx models wth dfferent WIP levels that are suffcent to analyze the rule s effects on the fab performance. The upper bounds for the nventory are gven n Table 1. The model wth CONWIP level 25 s smlar to a model wthout CONWIP because the nventory boundares n models wth WIP level 25 represent the maxmum value reached n a smulaton run wthout a WIP bound. If the nventory bounds for all sx products n the model wth CONWIP level 25 are decreased by one, we receve the next lower boundares of the model wth CONWIP level 24. Table 1: CONWIP Levels CONWIP Levels for product type level The boundary values for all other models can be computed n the same way. 2.4 Drawbacks of the Smple Model In ths secton, we dscuss some lmtatons and dsadvantages of the smple model. Fg. 4 and 5 show the cycle tmes and nventores of product 1 n the and smple models. The sold hstograms were bult from the model data. The dotted ones represent smple model data. The mean values are shown as vertcal lnes wthn the hstograms. The dstrbutons and means of both models dffer. Even though the sngle delay groups have nearly the same means and dstrbutons due to the fttng of gamma dstrbutons to the smulaton data, the model has on the average hgher cycle tmes and work n progress. Takng nto account the smplcty of the reduced model, however, the accuracy of the above results can be acceptable n certan research contexts. A drawback arses, however, when usng the CONWIP lot release strategy. Fg. 6 and 7 llustrate the dfferences n the cycle tme and nventory of both models for CONWIP level 24. The results for a model wth CONWIP level 25 are not depcted because they are almost dentcal to those of a model wth no WIP regulaton. In the model the cycle tme ncreases for an nventory level of 24. The nventory s always at the hghest Number of lots smple Cycle tme (hours) Fgure 4: Product 1 Cycle Tme Wthout CONWIP 1483

4 Frequency smple Rose As t s not possble to model a CONWIP lot release strategy wth the smple model, t s unlkely that the model s able to cope wth other lot schedulng strateges as descrbed n Wen (1988) and Rose (1999b). Consequently, there s a need to further analyze the behavor of a semconductor faclty and to model t n a more detaled way. In partcular, the dependences between the products or between the lots of a partcular product have a great mpact on the factory characterstcs and have been neglected by the models so far. Number of lots Number of lots Fgure 5: Product 1 WIP Wthout CONWIP smple Cycle tme (hours) Fgure 6: Product 1 Cycle Tme Wth CONWIP Level 24 3 CORRELATION IN WAFER FABS Before we start dscussng dependences between delays n the and the smple model, we frst present the bascs for measurng correlaton. Frst, formulae are ntroduced that we need to calculate correlaton between measured data. Then, types of correlaton we measured n the wafer fab are presented. 3.1 Correlaton Equatons In ths secton, we defne the terms correlaton and autocorrelaton of stochastc processes or data vectors. These defntons can also be found n most computer smulaton or statstcs book (Law and Kelton 1991). Let A be a dstrbuton and E[A] ts expectaton. The coeffcent of correlaton of two dstrbuton functons A 1 and A 2 s expressed as COR[A 1, A 2 ]= E[A 1 A 2 ] E[A 1 ]E[A 2 ] E[(A1 m 1 ) 2 ] E[(A 2 m 2 ) 2 ] (2) Frequency smple Number of lots Fgure 7: Product 1 WIP Wth CONWIP Level 24 possble level. The smple model on the other hand shows no change n cycle tme dstrbuton and the number of lots s always below the allowed level and t s spread over several WIP levels as n the model wth no nventory bound where m = E[A ], {1, 2} The analyss of our smulaton models requres to use data vectors nstead of dstrbuton functons A n Equaton 2. Both data vectors A 1 = [a1 1,,a1 n ] and A 2 =[a1 2,,a2 n ] must have the same sze A 1 = A 2. We use notaton A() to access element a of vector A wth 1 A and A(, j) to receve or to modfy elements a up to a j, where 1 <j A. Autocorrelaton s a specal case of the standard correlaton. Instead of usng two dfferent data vectors only one s used and the correlaton between values wthn ths sequence s expressed by autocorrelaton. Autocorrelaton s computed for dfferent lags. The lag s the dstance between two values for whch the correlaton value should be gathered.

5 Let A be a data vector. The autocorrelaton of ts values s defned by ACOR[A, l] =COR[A(1, A l), A(l, A )] (3) lot x delay wth l A mean delay x 3.2 Sldng Wndows For some cases of nterest we cannot use the correlaton Equaton (2) and (3) drectly. For example, t s not applcable f we ntend to measure the dependences between the delays of product 1 and product 2 whle beng n cycle 2. It s not possble to use the above coeffcent of correlaton for these two sequences of delay measurements because the measurement do not happen at the same ponts n tme. In addton, t s unlkely that the number of measurements of each sequence wll be the same for a gven observaton perod. Thus, we have to transform these contnuous tmedependent data sets nto sequences wth the same number of values and a dscrete ndex. Ths problem seems to be uncommon to the statstcs communty. Therefore, we developed our own approach to transform the raw data sets nto a graph that can be used for comparng the correlaton propertes of the consdered models. In Fgure 8, two dfferent tme dependent data sequences X and Y are shown. The elements e of each sequence are pars (e t,e v ) of a tme pont e t when the delay s started and the delay value e v. In order to calculate a correlaton value for the sequences we put a wndow over both of them. Ths wndow starts at a dscrete pont n tme w t and has a predefned fxed sze w s. The wndow sldes from the begnnng of each sequence to ts end usng W t and w s to set a new poston. Gven a sequence E, let and e mn t = mn{e t (e t,e v ) E} e max t Then we buld W t as W t =[w 1 t,w2 t,..., wn t ], = max{e t (e t,e v ) E}. wth w1 t = mn{xt mn and wt n max{xt max The w t must be subsequent and may not overlap w +1 t = w t + w s.,yt mn },y max t }. Note that for both sequences we have to use the same start tme otherwse we would perform a mxture between autocorrelaton and correlaton computaton for two dfferent sequences. Each tme the wndow covers a new range 1485 lot y mean delay y wndow sze tme Fgure 8: Correlaton Computaton Wth Sldng Wndow [w t,w t + w s) all values, whch le theren, are collected from the data sequence. X w ={x x = (x t,x v ) X w t x t w t + w s} As t can be seen from Fgure 8 the mean of these values s computed and stored n a new data set X w. X w = X w X w X w =[X 1 w, X2 w,..., Xn w ] The same procedure s appled to data sequence Y.By defnton both new data sets are of equal sze: X w = Y w. The generated data sets are now used to compute a representaton of the correlaton that exsts between the orgnal data sets by Equaton (2) c = COR[X w, Y w ]. Yet, t s not clear whch wndow sze w s should be used to dvde the data n equal szed peces. If the wndow sze s too small there mght be wndows wthout any data n t. On the other hand f the wndow sze s too large the averages are computed over too many values and we lose certan tme dependent characterstcs of the data. In the sequel, we therefore use a graph wth a range of wndow szes and the resultng correlaton values, nstead of a sngle correlaton value wth a fxed wndow sze. There s no obvous nterpretaton avalable for ths graph but now we

6 are able to compare correlaton propertes of the fab wth the ones of our smple model. So far we have only consdered the computaton of correlaton between data vectors. Next, we explan n whch cases correlaton occurs n wafer fabs and whch effects cause ths correlaton. In most cases we measure the correlaton of lot delays between two passes through the bottleneck. 3.3 Correlaton n a Sngle Cycle Autocorrelaton smple model In a wafer fab, there s obvously correlaton between the delays of consecutve lots of the same type. Fgure 9 llustrates ths case for a delay cycle and a sngle wafer type. Wafers wth a hgher lot number are dependent on those whch entered the cycle earler. The arrows ndcate dependences between the lots. If a lot of wafers has to wat a long tme n a queue before processng s started, t s very lkely that some of ts successors have to wat for a longer tme, too. As a delay group represents a sequence of tool-groups t s clear that such dependences occur more than once and we only measure and model the aggregaton of ths lot behavor. Ths knd of dependence s expressed by autocorrelaton, see Equaton (3) Lag Fgure 1: Autocorrelaton of Product 1 n the Frst Delay Cycle Cycle sequence x Cycle sequence y fnshed? Bottleneck fnshed? Fgure 9: Correlaton n a Sngle Cycle Now, we compare the autocorrelaton propertes of both the and the smple model. Fgure 1 presents only the frst delay cycle of product 1 because all other cycles and products behave n a smlar way. From the two curves we conclude that there are no dependences between lots n the same cycle n our smple model. On the contrary, the model shows sgnfcant autocorrelaton values for the frst two non-zero lags. 3.4 Correlaton Between Cycles In Fgure 11 wafer lots n two dfferent cycles are llustrated. Both sequences share a common tool-group n ths sketch. In a real fab ths could be several workstatons. Table 2 llustrates the common tool-groups n the cycles 2 and 3 of product 1. The thrd column ndcates f two toolgroups match (m), f a space has to be nserted () or f there s a msmatch. The sequence of all matchng toolgroups s the longest common subsequence (LCSS) of both orgnal sequences. The LCSS algorthm s a specal case of 1486 Bottleneck Fgure 11: Inter-Cycle, Inter-Product Correlaton the global algnment problem and s descrbed n Gusfeld (1997). The number of matches s 13, of msmatches 4, and of gaps 1. Obvously, the match percentage s 48 percent for both sequences. We see, that the dependences are caused by the dfferent types of lots as they are ntermxed n the queues and n the workstatons. We call these dependences between lots of the same product type, but n dfferent cycles nter-cycle correlaton. A good way to llustrate nter-cycle correlaton s to use a fab model wth only a sngle product (Fgure 12). Once agan, the smple model cannot reproduce the correlaton values for longer wndow szes n the model. The correlaton values below 3 should not be consdered as too mportant because the mean nterarrval tme for cycle 2 s 33.7 and for the thrd cycle s The standard devaton s n both cases Therefore we conclude, that only a few lot delay events occur n wndows smaller than 3. In summary, the smple model shows no nter-cycle correlaton whle the model exhbts strong dependences among lots of dfferent cycles.

7 Table 2: Longest Common Subsequence of the Frst Product Proc. seq. cycle 2 Proc. seq. cycle 3 254_CAN_.43_MII 254_CAN_.43_MII m 1121_DNS-PUD 1121_DNS-PUD m 15122_LTS_ _LTS_1 m 15627_HIT_S _LAM_49B_ _LTS_ _IMP-MC_ _IMP-MC_1+2 m 12553_POSI_GP 12553_POSI_GP m 12531_SH 12531_SH m 15131_LZZZZ 15131_LZZZZ m 15627_HIT_S6 1221_AUTO-CL_undot 1221_AUTO-CL_undot m 1129_ASM_C1_D1 1127_ASM_B3_B4_D4 m 12226_NF _NF-2 m 1221_AUTO-CL_undot 1224_NIT-ETCH 1126_ASM_B _LZZZZ m 11125_ASM_E1_E2_H4 1222_AUTO-CL_dot 11127_ASM_E3_G2_H _SURF_2 1123_DNS _DNS-3 m 1123_DNS _DNS-3 m Table 3: Longest Common Subsequence of the Frst Product n the Second Cycle and the Thrd Product n the Second Cycle Proc. seq. of product 3 Proc. seq. of product 1 254_CAN_.43_MII 254_CAN_.43_MII m 1121_DNS-PUD 1121_DNS-PUD m 15122_LTS_ _LTS_1 m 15627_HIT_S _LAM_49B_ _LTS_ _IMP-MC_ _IMP-MC_1+2 m 12553_POSI_GP 12553_POSI_GP m 12531_SH 12531_SH m 15131_LZZZZ 15131_LZZZZ m 15627_HIT_S6 1221_AUTO-CL_undot 1221_AUTO-CL_undot m 1129_ASM_C1_D1 1127_ASM_B3_B4_D4 m 12226_NF _NF-2 m 1221_AUTO-CL_undot 1224_NIT-ETCH 1125_ASM_B1_H _LZZZZ m 11125_ASM_E1_E2_H4 1222_AUTO-CL_dot 11127_ASM_E3_G2_H3 1123_DNS _DNS-3 m 1123_DNS _DNS-3 m.2.1 smple model there are 13 matches, 4 msmatches, and 9 gaps, whch gves us a match percentage of 5 percent. To further emphasze ths pont, Fgure 13 shows the correlaton curves between lots of product type 1 and 3, both n the second delay cycle. Obvously, the smple model does not show any nter-product dependences. Correlaton smple model Wndow sze (hours) Fgure 12: Correlaton Between Cycle 2 and 3 n Sngle Product Models 3.5 Correlaton Between Products The term nter-cycle correlaton can be generalzed to several products. Both types of wafers n Fgure 11 can be consdered as dfferent products as well. As several product processes have to share the same sets of tool-groups, correlaton between products can be expected. Bascally, ths nter-product correlaton s a generalzaton of nter-cycle correlaton. Table 3 gves an example whch dependences can exst between two dfferent wafer products. In ths case Correlaton Wndow sze (hours) Fgure 13: Correlaton Between Lots of Product 1 and Product 3 Both n the Second Cycle Unfortunately, we cannot separate nter-product correlaton from nter-cycle correlaton. In order to model only nter-product correlaton a factory wth sequences whch have only a sngle cycle would be requred. 1487

8 4 OVERTAKING In the prevous secton, we dscovered that the measurements from the fab show consderably more dependences of varous knds than the smple model although all delay dstrbutons were approxmately the same n both cases. Therefore, there must be at least one feature that s fundamentally dfferent n both models. We came to the concluson that most of the correlaton effects must have been caused by the non-overtakng property of the lots of the fab. In contrast, there was no overtakng regulaton n the smple model. Successve lots of a certan type receve random delay cycle values from a gven Gamma dstrbuton. Therefore, t s unlkely that a lot always fnshes the delay before the lots wth a hgher lot number. But n the real fab all lots have to proceed through the same tool-groups and overtakng n a queue s not possble due to the FIFO dspatchng rule. 4.1 Defntons In ths secton, we ntroduce the terms, fnshed delay, rest delay, relatve fnshed delay, and overtakng, that are used to descrbe overtakng behavor. Let x be a delay gven as a tuple (x t,x v ), where x t s the pont n tme the delay starts and x v s the duraton of the delay. The fnshed delay of x at pont n tme t s defned as x f (t) = mn{t x t,x v }, t x t. The rest delay of x s gven by or x r (t) = x v x f (t). x r (t) = max{x v (t x t ), }. The relatve fnshed delay x rf s defned as: x rf (t) = x f (t) x v The relatve fnshed delay s a measure of the percentage of a delay, that has already been worked off. Let x and y be delays. Delay x s taken over by delay y f the rest delay of x at the event tme y t s greater than the total delay of y, whch s x r (y t )>y v. Fgure 14 llustrates the term fnshed delay and rest delay graphcally at the pont n tme y t. Lot x s overtaken by lot z but not by lot y. lot x lot y lot z x f x f x v z v x t z t y t tme Fgure 14: An Overtakng and a Non-Overtakng Case x r y v (y t ) (y t) (z t ) (z t) We see that there are two factors whch nfluence overtakng. The frst factor s the length of a delay. The longer a delay s, the easer t s for other lots to overtake, because t s more lkely for ther delays to ft nto the long delay. The second factor s the percentage amount of the fnshed delay. If the percentage s hgh, there s only a short rest delay. Therefore t s unlkely that other lots overtake ths one. On the other hand, f the percentage s low, the delay just started and the lot needs a longer tme to fnsh. Then future lots have a hgher chance to be delayed less than the rest delay of the lot currently watng and take t over. The relatve fnshed delay allows us to combne both factors n a sngle measure. The fnshed delay and the rest delay cannot be used for ths purpose as these measures do not take nto account the length of the delay. The overtakng percentage of two lot types x, y s defned as x r D y OV OV (x, y) = D y OV + Dy NOV, where D y OV s the number of overtakng lots and Dy NOV the number of non-overtakng ones. If p = OV (x, y), p percent of the lots of type y overtake the lots of type x. The overtakng percentage facltates the comparson of the overtakng behavor of lot types n dfferent smulaton models. The overtakng percentage s dependent on shared processng tool-groups and on the delay dstrbutons of both lot types. For nstance, f the dstrbuton of lot type x has on the average smaller delay values compared to the values of lot type y, OV (x, y) has a value below 5 percent because most of the tme lots of y have a greater delay value than the rest delay of the current x delay. On the other hand, OV (y, x) s above 5 percent as x delays occur more frequently and wth shorter delays. 1488

9 4.2 Overtakng Behavor n the Smulaton Models Now we compare the smple models and the model wth reference to lot overtakng. The followng plots llustrate the entry tmes of several lots nto the bottleneck (Fg. 15 and 16). Each row shows all entry events for a sngle lot. Agan, all models make use of all sx products, but only the frst one s shown. Each vertcal lne represents an entry event of a lot. They have been plotted alternately wth dfferent lne types to facltate a comparson of neghborng lots. The dstance between entry events of the same lot number are the sum of the bottleneck processng tme and the delay n a sngle cycle. Lot number Tme (hours) x 1 4 Fgure 15: Lots Enterng the Bottleneck n the Model nearly no overtakng for lots of the same product type and n the same cycle n the model (Fgure 15). If we compare ths observaton wth results from models based on the smple model we observe consderable overtakng n those models. For nstance, f we consder lot number 217 and 218 on the second entry nto the bottleneck (Fgure 16). In ths case lot 218 s overtakng lot 217, because t enters the bottleneck earler than prevous lot. Ths holds for all followng bottleneck entres n ths case, too. As these plots show only a small snapshot, we have counted the number of overtakngs and dvded t by the sum of overtakngs and non-overtakngs. The method to generate these overtakng percentages OV (x, y) from the data sets s gven below. The followng steps have to be performed for all possble pars of lot types x, y. 1. Reset the counters c OV = and c NOV =. 2. Let D be a vector of delay values and T the correspondng tme events of lot type {x,y}. 3. For all elements t x T x (a) Generate the set of ndces (b) Create the set J ={j t x t y j <tx +1 }. D y J ={dy j j J } (c) Create the sets of overtakng and nonovertakng lots and D y OV ={d j d j D y J dx r (ty j )>d j } Lot number D y NOV ={d j d j D y J dx r (ty j ) d j }, where the rest delay s computed by d x r = t y j tx. (d) Update the counters c OV and c NOV : Tme (hours) x 1 4 Fgure 16: Lots Enterng the Bottleneck n the Smple Model If we look at all vertcal lnes at the -th poston n the rows, we can compare the overtakng behavor of lots of the same type. Obvously, lots wth a hgher lot number enter the bottleneck after a gven cycle always after all lots wth lower lot numbers have entered the bottleneck workstaton n that cycle. We conclude, that there s c OV = c OV + D y OV c NOV = c NOV + D y NOV 4. Calculate the overtakng percentage by c OV OV (x, y) = c OV + c NOV Applyng ths procedure we receve the percentage of overtakng lots that occur durng a smulaton run for models wth all sx products. Table 4 shows the overtakng 1489

10 percentages of lots frst product. Each column represents a dfferent cycle. The other products behave n a smlar way. Table 4: Overtakng Percentages of Lots of Same Type Cycle Model smple Cycle Model smple Snce all lots of a certan type have to advance through the same tool-groups and wat n the same queues, t s obvous that they usually cannot overtake each other. Ths s due to the fact that a FIFO dspatchng rule s used n the smulatons. In the rare case when a lot s overtaken by another one, t s lkely that both lots entered a tool-group at the same tme consstng of more than a sngle workstaton. After the processng s fnshed, they are unloaded from the workstatons n the reverse order and an overtakng happens. The same effect occurs f a workstaton operates on batches of lots. Both cases are very unlkely and therefore we conclude that there s almost no overtakng n the model. In contrast, the smple model shows a consderable amount of overtakng n almost all cycles. 5 CONCLUSIONS In ths paper, we showed that smple smulaton models for wafer fabs may lead to questonable performance predctons n certan scenaros. Ths s caused by the absence of lot dependences that can be found n full fab smulaton models lke the data sets. The man reason for ths msbehavor s the fact that overtakngs of lots happen due to replacng sequences of work centers by delays. In contrast, overtakng happens only sporadcally n a real fab. We conclude, that n spte of the problems dscussed n ths paper smple models are stll useful but they have to be mproved for certan problem scenaros. The problem s to avod lot overtakng n the smple model wthout ncreasng the model complexty too much. Ths could be done by replacng the delays ether by a seres of pseudo work statons or by desgnng a way of samplng the delays such that overtakng of lots s avoded. ACKNOWLEDGMENTS The author would lke to thank Chrstan Schloter for frutful dscussons and hs valuable programmng efforts. REFERENCES Fowler, J. and J. Robnson Measurement and mprovement of manufacturng capactes (): Fnal report. Techncal Report A-TR, SE- MATECH, Austn, TX. Gusfeld, D Algorthms on Strngs, Trees, and Sequences: computer scence and computatonal bology. Cambrdge Unversty Press, Cambrdge, Massachusetts, frst edton. Hopp, W. J. and M. L. Spearman Throughput of a constant work n process manufacturng lne subject to falures. Internatonal Journal of Producton Research, 29(3): Kelton, W. D., R. P. Sadowsk, and D. A. Sadowsk Smulaton wth Arena. McGraw Hll, New York. Law, A. M. and W. D.Kelton Smulaton Modelng & Analyss. McGraw Hll, New York, 2nd edton. Press, W. H., S. A. Teukolsky, W. T. Vetterlng, and B. P. Flannery Numercal Recpes n C: the art of scentfc computng. Cambrdge Unversty Press, Cambrdge, Massachusetts, second edton. Rose, O WIP evoluton of a semconductor factory after a bottleneck workcenter breakdown. In Proceedngs of the Wnter Smulaton Conference 98. Rose, O. 1999a. Estmaton of the cycle tme dstrbuton of a wafer fab by a smple smulaton model. In Proceedngs of the SMOMS 99 (1999 WMC). Rose, O. 1999b. CONLOAD - A new lot release rule for semconductor wafer fabs. In Proceedngs of the Wnter Smulaton Conference 99. Wen, L. M Schedulng semconductor wafer fabrcaton. IEEE Transactons on Semconductor Manufacturng, 1(3): Wrght Wllams & Kelly Factory Explorer 2.3 User Manual. AUTHOR BIOGRAPHY OLIVER ROSE s an assstant professor n the Department of Computer Scence at the Unversty of Würzburg, Germany. He receved an M.S. degree n appled mathematcs and a Ph.D. degree n computer scence from the same unversty. He has a strong background n the modelng and performance evaluaton of hgh-speed communcaton networks. Currently, hs research focuses on the analyss of semconductor and car manufacturng facltes. He s a member of IEEE, ASIM, and SCS. Hs emal and web addresses are, respectvely, <rose@nformatk.un-wuerzburg.de> and <www-nfo3.nformatk.un-wuerzburg. de/ rose>. 149