Implementation of 64-Point FFT Processor Based on Radix-2 Using Verilog

Transcription

1 Inernaional Journal of Engineering Reearch & Technology (IJERT) Implemenaion of 64-oin roceor Baed on Radix-2 Uing Verilog T.TIRUALA KOTESWARA RAO 1, S. SARATH CHANDRA 2 Suden of. Tech Deparmen of Elecronic and Communicaion Engineering 1, QIS Iniue Of Technology, Ongole. Aociae rofeor 2, Deparmen of Elecronic and Communicaion Engineering, QIS Iniue Of Technology, Ongole. Abrac A Fa Fourier ranform i an efficien algorihm o compue he dicree Fourier Tranform (DFT). The operaion ha a high compuaional requiremen of large number of operaion (N 2 complex muliplicaion and N (N-1) addiion). Thi make compuaional and implemenaion very difficu Shor lengh rucure are can be obain higher lengh. To obain VLSI rucure by uing 4-poin o conruc N-poin raher han 8-poin. In hi paper he propoed archiecure i higher order and i i pli ino hree and each i radix-2 baed 4-poin o reduce he number of operaion. In hi archiecure each require 8 complex addiion/ubracion o reduce he no of complex muliplicaion afer each 4-poin and o keep pipe line way of compuaion of deign. ropoed archiecure i implemened uing verilog HDL XILINX ISE The performance of he propoed archiecure i implemened in erm of relaive error. The propoed archiecure give be compromie in erm of peed. Key word: FGA, 8-poin, 4-poin, paial diribuion, emporal diribuion. 1. Inroducion The Dicree Fourier Tranform (DFT) i one of he mo imporan ool ued in digial ignal proceing applicaion. I ha been widely implemened digial communicaion uch a Radar, Ulra wide band receiver (UWB) and many oher applicaion. Compuing hi operaion ha high compuaional requiremen and large number of operaion (N 2 complex muliplicaion and N (N-1) addiion).thi make compuing and implemenaion very difficul o realize. To reduce he number of operaion a fa algorihm ha been inroduced by Cooley-Tukey [2] called Fa Fourier Tranform (). Laer reduce he compuaional complexiy from O (N2) o O (NlogN). To reduce he complexiy of algorihm oher reearcher propoe numerou echnique like radix-4 [2], pli radix []. By uing hee wo echnique we can able o avoid he radix-2 rucure. Thee archiecure are baed on eiher Decimaion in Time Domain (DIT) or Decimaion in Frequency (DIF). uch oher archiecure wa propoed on he bai of hee archiecure. In anoher way here i growing inere in he Field of Field rogrammable Gae Array (FGA). FGA have poenially ubanially acceleraed compuaional algorihm like. The Higher Order are implemened by uing High-Co FGA. I i no poible o inaniae 512-poin wih he XILINX I core o implemen in Sparan- family. To reach hi challenge, we preen a VLSI rucure o allow higher order o be implemened ino low co FGA. The remainder hi paper i organized a follow. The ecion I regarding he back ground work for he DFT. Algorihm, in ecion II i devoed o he propoed low archiecure and ecion III i decribed abou he wo kind of diribuion (Temporal and Spaial Diribuion). In ecion II we deail he principle and rucure for generalized o higher order. Afer ha echnique o ave area are illuraed. Secion IV i preen experimenal reul and comparion wih I core and former work quoed in he lieraure. In Secion V finally we conclude he paper. I Background For a given equence x of n ample, he Dicree Fourier ranform (DFT) frequency componen X (k) may be defined. 2811

2 Inernaional Journal of Engineering Reearch & Technology (IJERT) N 1. k X ( k) n) W n N (1) n0 where, W N e 2 j N he widdle facor, n and k are repecively he ime and frequency domain indexe. 0 n N And N i he DFT 0 k N 1, 1 lengh. Le u conider ha he N =. T, k = + T. and n = l +. m, where, T are ineger, l {0, 1.-1} and, m{0,1.t-1}. Applying hee conideraion in (1), we obain (2) 1 T 1 l. m T. X ( T. ) l. W. T (2) l0 m0 I can be found ha (2) i equivalen o 1 T 1 l. m T. X ( T. ) l. W. T () l0 m0 Y And finally, () can be rewrien 1 l0 T 1 m. W. T l. WT m0 X ( T. ) W (4) Equaion (4) mean ha i i poible o realize N-poin o fir Decompoing ino one -poin and one N-poin where N =.T and hen combining hem. For example ake 64-poin a a cae udy afer ha i i generalized for higher order. To perform he 64- poin ake N==8. Then equaion (4) i given a follow: 7 l0 7 m. W xl 8 mw 8 64 X ( 8. ) W (5) 8. m0 Equaion (5) illurae ha he 64-poin i expreed by uing wo-dimenional rucure of 8- poin. According o he Equaion (5) he proceing higher order elemen i 8-poin. II. LOW AREA ARCHITECTURE The N-poin pli in o hree according o nex equaion. X ( q Kp) L1 1 K 1 l0 m0 k 0 l, m, k) ( Klmk)( Kpq) W N (6) The 64-poin may be conruced by eiher of 8-poin, 4-poin, 2-poin. The rucured i no highly and inhomogeneou. Anoher oluion for conrucing he 64-poin i o pli 64-poin ino hree of 4-poin. For L==K=4, hen he Equaion for 64-poin i given by X ( 4q 16 p) Opimizaion l0 m0 k0 l, m, k) W (16l4mk )(16p4q) 64 (7) The 64-poin according o he ignal flow graph of fig Radix-4 i he proceing elemen. The 64-poin compoed of a conrol uni and block of 4-poin uni, wo block of muliplier wih wo phae generaor uni, wih a complex 64-poin memory uni. The conrol uni managing -4 block and muliplier and memory uni. The conrol uni alo generae addree of inpu and ou pu of each block. 1) Radix-4 modificaion: Oupu of uch algorihm are preened by he following equaion A C X( 0) 0) 2) 1) ) B X( 1) 0) 2) j( 1) )) X( 2) 0) 2) 1) ) X( ) 0) 2) j1) j) D (8) The ignal flow graph of radix-4 rucure i given in he fig2. The radix-4 algorihm i compoed of 8 complex addiion/ubracion. To reduce he number of complex muliplier afer each 4-poin and o perform he pipeline way of compuaional deign we have o modify he 4-poin archiecure. The Radix-4 i compued a muli inpu and muli oupu. Thi rucure require 4 muliplier in one clock cycle. Thi rucure preen a high peed deign bu i require a S2 block o erialize daa. For hi reaon we have o re deign he propoed archiecure. The reuling deign produce one oupu for one clock cycle. Iner mediae ignal are ued o know he parallel proceing of he daa. 2812

3 0) Inernaional Journal of Engineering Reearch & Technology (IJERT) 2) emory uni: hae generaor generae he widdle facor for each oupu of 4-poin. The muliplier perform he complex muliplicaion and ore i in he 64-poin complex memory. Thi memory i alo known a hared memory. By uing haring memory, he memory i reued and hared beween all he block. 4S 1 ulip lier hae genera Conrol uni 4S 2 ulip lier hae genera 4S or or Fig1 Signal Flow Graph of he ropoed Low area archiecure The compuaion of 64-poin baed on 4- poin need complex memorie. Bu in he archiecure we are uing only one memory and ha i divided in o he four mall par conaining 16-poin complex memorie in order o improve he laency. By uing hared memory we have a problem ha i ha only one wrie por. A par of daa i aved already and i i no ued. If we ue he dual por memory and ha will be ynheized a BRA. Thee are available in he low co FGA. III. Technique for ropoed Low Area A. Spaial Diribuion The poible realizaion of 64-poin i preened in he ignal flow graph of fig1. In hi diribuion he compuaion of 64-poin i compoed on five leve The Fir level have wo erial o parallel converer ued o ore real and imaginary daa. The econd level compoed of 8 block of 8-poin pli radix DIT. The non rivial muliplicaion i given by he hird block and i ha 49 complex muliplier. The econd level i a ame a ha of econd leve Final level i compoed of wo 2S block o give he daa in a erial way. All he inpu daa are ready o proceed a 64 h clock cycle. 2) 1) ) Fig2 Radix-4 buer fly diagram The 8-poin oupu are available and muliplicaion can be ared afer 5 clock cycle. The complex muliplicaion done by Block muliplier need wo clock cycle o perform 49 complex muliplicaion. 5 clock cycle afer he la of 8- poin block he oupu of 64-poin are available. The main advan of hi archiecure i high peed and low laency. The implemenaion of hi archiecure on FGA need high memory and high number of complex muliplicaion and addiion. For hi reaon he archiecure i no uiable for Low co FGA uch a Sparan family. B. Temporal diribuion The 64-poin may alo be realized by emporal diribuion. The Temporal diribuion ha alo having 5 leve In he econd and fourh level i ha he only one block of 8-poin when compared wih paial diribuion. The Fir level i compoed of one S2 block o erialize he inpu daa. The inpu daa may be parallied in order o perform he compuaion. The S2 block are implemened by delay regier. The conrol uni man he inpu daa addree and he fir 8-poin inpu daa ha he addre in he form of 8j, j E (0, 1.. 7). A he 56 h clock cycle he inpu may proceed o he fir of 8-poin. The 8-poin oupu are available and muliplicaion can be ared afer he 5 clock cycle. A he 57 h clock cycle he indexed daa 8j+1 may be ranformed by he fir 8-poin and he muliplier oupu are available afer 7 clock cycle.the la reul of muliplier available a he 71 clock cycle. The reul are ored in he complex 64-poin memory. Similarly, he econd 8-poin may be proceed and ored in he 64- poin complex memory. 281

4 relaive error Inernaional Journal of Engineering Reearch & Technology (IJERT) S2 S2 uliplier 2S 2S Fig Signal flow graph of he paial diribuion C. Compromie analyi In boh paial and emporal diribuion he 64-poin i fir decompoed ino 8-poin. In erm of hroughpu boh are ame and laency in boh cae i alo ame. The laency in boh he archiecure are given by he formula L (N) = N+7log (N-2). The conumed area i he major difference beween he wo diribuion. The emporal diribuion conume 7 ime le area when compared wih paial diribuion becaue i uing only one block of 8-poin inead of 8 in he paial diribuion. The number of muliplicaion and number of 8-poin block i reduced o 7 and 2 repecively. The complex daa memory may be removed by uing he muliplier o ore he reu Real par Imagin ary par S2 S2 Fig4 Signal flow graph of he emporal diribuion To low co FGA. The oher limiaion i ha he number of inpu by 8-poin we have inpu N=8 n. To overcome hi problem he 8-poin may be pli ino 4-poin uing radix-4 algorihm. By uing hi algorihm we can able o reduce 2% of occupied lice in parane XCS500. IV. Reul A. Simulaion Reul FF T8 Conrol uni uli hae 64- poin com plex relaive error of real value FF T8 2 S 2S relaive error Real par Imagina ry par The uliplier oupu are ored in he S2 regier by uing he addree 8j, 8j+1.. roceeded one can ue he addree. The major drawback of decompoiion of higher order ino 8-poin i relaed o he hardware conumed reource. The percen of occupied lice in parane XCS500 while we are uing pli radix DIT decripion wih 8-poin i 0%. The reource are over flowed o deign higher order, for hi reaon we are opimizing our deign real value of inpu equence Fig5 Relaive error of real value of inpu equence The relaive error may be calculaed by comparing he ATLAB imulaion reul wih he verilog coding implemened for low co FGA. The phae relaive error i a follow. The Relaive phae error of phae value give u he phae angle and he relaive error of real value. 2814

5 relaive error Inernaional Journal of Engineering Reearch & Technology (IJERT) Rev Fig6-0.5 Relaive error of phae value o he inpu equence phae value of inpu equence B. Synhei reul relaive error of phae angle Fig7 TO LEVEL C. Implemenaion reul relaive error Fig6 Relaive error of phae value o he inpu equence V. Concluion The echnique o implemen higher order ino Low Co FGA are propoed and implemened. An opimized archiecure propoed for higher order afer a deailed udy and i i implemened. Our Fuure work i devoed o he FGA implemenaion by he opimizaion of block muliplier and algorihm propoed in [6] o replace embedded muliplier. REFERENCES [1] Youri Ouerhani, aher Jridi and A. Alfalou Implemenaion echnique of higher order in o low co FGA. [2] W. Cooley and 1. Tukey, An algorihm for he machine calculaion of Complex Fourier erie, ah. Compu., vo 19, pp , April [] A. Y. Oppenheim, R. W. Schafer, and J. R. Buck,Dicree-Time Signal roceing, 2nd ed. Englewood Cliff, NJ: renice-hall, [4] H. Sorenen,. Heindeman, and C. Burru, On compuing he pli radix, IEEE Tran. Acouic, Speech, Signal roce, vo1.4, pp , [5] K. aharana, E. Gra, and Ulrich Jagldhold, A 64-oin Fourier Tranform Chip for High- Speed Wirele LAN Applicaion Uing OFD, IEEE 1. Solid-Sae Circui, vo 9, pp , arch [6] Xilinx roduc Specificaion, High perfomance 64-poin Complex IIF Y.7.0 June 2009 [online]. Available on: hp:// [7]. Jridi and A. Alfalou, A Low-ower. High- Speed DCT archiecure for im compreion: principle and implemenaion, in roc. VLSI Sy. in Chip Conf (VLSI-SoC), pp , Sep [8]. Jridi and A. Alfalou, Direc Digial Frequency Synheizer wih CORDIC Algorihm and Taylor Serie Approximaion for Digial Re ceiver, Euro Journal of Scienific Reearch, vo 0, No. 4, pp Fig 8 Implemenaion Reul of higer order 2815