Extraction of Parasitic Capacitance for Multilayer Chip Ceramic Inductor

Transcription

1 第卷第期电子元件与材料 Vol. No. 年 8 月 ELETRONI OMPONENTS - - AND MATERIALS Aug. Extractio of Parasitic apacitace for Multilayer hip eramic Iductor. Itroductio hip ca be classified as wire woud type ad multilayer type o the basis of the electrode coil formatio type. The former is the extedig product of traditioal wire woud ad is hard to dowsize. However, multilayer chip is made by castig ceramic slurry, pritig silver paste, ad co-firig to form closed magetic loop. The advaced thick-film scree pritig techology ad multilayer proceedig techology achieve miiaturizatio ad SMT. Therefore, multilayer chip is the paramout focus i idustry. Due to the high frequecy desig tedecy of the electroics products, the ifluece effect of parasitic parameters o circuit becomes more ad more serious. ompared with traditioal wire woud type, multilayer chip has larger parasitic which is the key factor of low self-resoace frequecy (S.R.F.) ad thus is limited for high frequecy applicatio. Whe workig at low frequecy, multilayer chip is equivalet to the series circuit of a ad a low resistace resistor. As the work frequecy icreasig, the effect amog the electrode layers becomes obvious ad the equals to a i series with a resistor, ad the i parallel with a capacitor. The behaves high resistace at SRF due to the couterbalace of iductive reactace ad capacitive reactace. While at higher frequecy tha SRF, the behaves capacitive effect. We ca see the performace of multilayer chip at high frequecy completely depeds o its parasitic, which is comprised of stray amog iteral electrode layers ad stray betwee iteral electrodes ad termial electrodes. Therefore,it is sigificat for desig ad simulatio of to extract the parasitic by a easy ad effective method. ommoly, there are three methods, which are aalytical method, test method ad umerical method. Aalytical method is a approximate method to obtai based o dividig the etire space ito lots of uits. Every uit is small eough to be treated as uiform electric field, ad the the of each uit ca be calculated by the formula of parallel plate capacitor. Actually, it is a complicated method. Test method is a deductio method by measurig the iductace ad the SRF. However, due to ski effect, the iductace at SRF is very differet from that at low frequecy ad it is ecessary to figure out a accurate iductace. This method is heavily depeded o the precisio of measuremet ad calculatio, ad ca be oly used as validatio for calculatio value. As a umerical method, Fiite Elemet Method (FEM) is a effective method to solve egieerig problem. Specifically, first we eed to get the physical ad geometric parameters of the ceramic ad electrode of multilayer chip ; ad the we establish a 3D fiite elemet module of the usig Asoft Q3D software; fially, the parasitic ca be calculated by operatig capacitor matrix amog electrodes. This method ca obtai accurate result ad is applied i desig.. Priciple of parasitic extractio. Stray amog electrodes urretly, the commo size of multilayer chip ceramic is.mm.5mm (5) ad the wavelegth of GHz electromagetic wave is 3mm. That meas each electrode i ca be treated as i equipotetial at GHz. So the

2 stray ca be figured out at the coditio of electrostatic field. etwork of the etire ca be summarized. The itegrated betwee port ad is the parasitic of the.,,4 Fig. Stray of electrodes of multilayer chip ceramic Is,3,,3 3 3,4 4,, 3, 4,,. 3D fiite elemet module I cosideratio of the edge effect i electrostatic field, the result from 3D module is obviously more precise tha that from D module. Firstly, we build a 3D fiite elemet electrostatic module for multilayer ceramic chip i Q3D. Secodly, the importat material ad structure parameters eed to be filled out, such as termiatio width A, electrode width Wc, gap betwee electrode ad electrical parameters of ceramic ad electrode. Thirdly, delete the coectios betwee electrodes ad combie termial electrodes with top ad bottom iteral electrodes separately showed as fig. 3. There are 6 electrodes ad the amog them ca be calculated usig Q3D software. Fig. 3D FEM model of multilayer chip ceramic 3 Fig.3 Order umbers of the electrodes of multilayer chip ceramic.3 apacitor etwork ad lumped Accordig to the coectio status of electrodes i multilayer chip ceramic, A Wc 5 4 Fig.4 apacitace etwork of multilayer chip ceramic Whe applyig uit curret Is betwee port ad, based o Kirchhoff curret law(kl): the algebraic sum of currets i a etwork of coductors meetig at a poit is zero, the voltage equatio of ode ca be formulated as belows: ( U U U ) Is jω (),,,,,, Ad, U, U, U, U U, So,,U,,U,U Equatio ca be trasformed to: ( U U U U U ) Is jω (),,,,, Ad equatio ca be trasformed to: [( ) U U U ] Is jω (3),,,, I like maer, voltage equatio of ode ca be formulated as [ U ( ) U U ] jω (4),,,, For voltage equatio of ode, [ U U ( ) U ] jω (5),,,, I a word, the matrix of ode voltage equatio ca be summarized as: T [ Is & ] [ ] T jω YcU & (6) I equatio 6, jω Yc is a admittace matrix, ad U & is a ode voltage colum matrix. I additio, we kow that:

3 i Yc Μ, i,, i, Μ, i,,, Μ, i i (7) Lac is A iductace ad p is parasitic, which is also the iput equivalet got from equatio. Rac Lac U & &] (8) [ T U p I equatio 7, i j j, i,, we set i, i i, for Fig.5 Equivalet circuit model for coveiece of calculatio. So we get equatio 9 by matrix iverse operatio: [ ] T ω & & & & (9) U T j U jω[ U U ] Yc The iput admittace of port ad is: Is Y j & Σ ω Σ () Ad the correspodig iput equivalet or parasitic is: Σ () jω Besides, matrix iverse operatio ca be operated through Miverse fuctio of Excel. I coclusio, the operatig steps for parasitic extractio of multilayer chip ceramic are listed as below:. Establish a 3D module of i Q3D, ad calculate the betwee each electrode;. Build a equivalet capacitor etwork, ad formulate voltage equatios of ode; 3. Solve the liear equatios through matrix coverse operatio, ad the reciprocal of the first matrix factor result is the parasitic of..4 Idirect measuremet of parasitic The equivalet module of is show as fig. 5. Rac is the high frequecy resistace of electrode, which is iflueced by ski effect ad i direct proportio to the square root of frequecy. The ifluece of Rac to S.R.F ca be igored because the value of Rac is always small. Therefore S.R.F. ca be expressed as below: SRF () π Lac p I the equatio, Lac is A iductace at S.R.F. which ca be calculated by Q3D ad S.R.F. ca be measured by RF impedace aalyzer. So, parasitic ca be calculated based o the kow A iductace ad S.R.F. 3 Parasitic aalysis for multilayer chip ceramic 3. ompariso of the result by measuremet ad umerical calculatio Take a commo multilayer chip ceramic for example, which is.mm.5mm size ad H at MHz with the ormal horizotal type electrode structure. Tab. Model parameters ad parasitic results for horizotal type of 5-N Relative permittivity of ceramic material 4.5 Number of electrode layers 6 S.R.F. by measuremet/ghz 4.6 Lac by simulatio/h 9.58 Parasitic by calculatio/pf.45 Parasitic by measuremet ad derivatio/pf.53 Absolute error/pf -.8 Relative error/% -5% I this table, S.R.F. is measured by vector etwork aalyzer 879ES. We ca see the results by umerical calculatio ad measuremet are

4 almost the same. Thus it is proved that the method metioed i.3 is efficacious for extractig parasitic ad ca be used for parasitic ifluece factors researchig of multilayer chip ceramic. 3. Effect of permittivity of ceramic material o parasitic /pf y.3x ε r Fig.6 Effects of ceramic permittivity o parasitic of It is show as fig. 6 that the parasitic is liear with ceramic permittivity for with complicated structure. Thus we ca reduce the parasitic by choosig ceramic material with smaller permittivity. urretly, the relative permittivity of ceramic powder i idustry is about 4~8 ad is expected to reduce further due to material techology improvig. 3.4 Effect of film thickess o parasitic /pf Film thickess /mm Fig.8 Effects of thi-film s thickess o parasitic of The maufacturig techology of multilayer chip ceramic is based o thick film pritig process. First, ceramic gree sheet with uiform thickess is formed o PET film by tape castig, ad the is puched at the pre-desiged dot positio by laser pucher. After that, iteral electrodes are prited o the puched ceramic films by pritig machie based o the pre-desiged electrode patter. The ceramic films with electrode are lamiated i order ad the pressed. So the chip body has bee doe. The gap betwee electrodes depeds o the ceramic film thickess ad is also oe of the key factors of parasitic. 3.3 Effect of iteral electrode width o parasitic /pf Parasitic. Parasitic resistace 内部电极线宽 /μm Fig.7 Effects of iside electrodes width o parasitic ad parasitic resistace It is show as fig.7 that the parasitic is approximately liear with iteral electrode width. We ca also reduce the width of iteral electrode to get small parasitic but the bad ews is that the resistace will icrease at the same time. So at egieerig desig stage all electrical parameters should be cosidered ad balaced to get suitable ad optimized performace R /Ω The effect of ceramic film thickess o parasitic is show as fig. 8. The parasitic reduces at first ad the icreases as film thickess icreases. The reaso is whe film thickess is thi, the gap betwee electrodes is also thi, ad thus the becomes large; whe film thickess icreases to some value, though the betwee electrodes is small, the top ad bottom substrate is also thi which results i large betwee ier electrode ad termial electrode. So the mezzo film thickess should be cosidered at egieerig desig stage.

5 3.5 Effect of termial width o parasitic..5 /pf Termial width /mm Fig.9 Effects of termial s width o parasitic of hip compoets are mouted to PB usig surface mout techology (SMT) so the termial electrodes are ecessary located at the bottom or the side surface to make sure good coectio. As a two-port compoet, multilayer chip ceramic has a certai parasitic betwee termial electrode ad iteral electrodes which will icrease as the termial width icreasig. The effect of termial width o parasitic is show as fig. 9. It is a effective way to decrease parasitic by reducig termial width. But the tred is cotaied at the poit of.mm width. I additio, it is importat to realize that termials with arrow width would cause weak bod to ceramic body ad eve quality problem of termial splittig away ad weak solderability. The ormal termial width for 5 size chip compoet is.3mm, while the parasitic ca be % off if the width is reduced to.mm. Besides, the strog reliability is also kept. 3.6 Parasitic of vertical structure There is aother vertical structure multilayer chip ceramic show as fig. except horizotal structure. The S.R.F. would be improved obviously as the vertical structure has small parasitic. Fig. 3D FEM model of vertical electrodes Take multilayer chip ceramic with vertical structure for example,.mm.5mm, H at MHz. Tab. Model parameters ad parasitic results for vertical type of 5-N Relative permittivity of ceramic material 4.5 Number of electrode layers 8 S.R.F. by measuremet/ghz 6.78 Lac by simulatio/h 9.74 Parasitic by calculatio/pf.55 Parasitic by measuremet ad derivatio/pf.57 Absolute error/pf -. Relative error/% -3.5% From tab. we ca see the vertical structure achieve 38% of horizotal structure oe because of the followig features: ) Small betwee iteral electrodes due to small area ecircled by ier electrode ) Small due to coectio i series mixed parallel betwee lays 3) Small betwee termial electrodes ad iteral electrodes due to log distace betwee them. 4 oclusio I a word, usig 3D electrostatic field fiite elemet method to calculate stray of multilayer chip ceramic is effective ad feasible, which ca be used i egieerig desig