LNN Reversible Circuit Realization Using Fast Harmony Search Based Heuristic 1

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1 LNN Reversible Circuit Realization Using Fast Harmony Search Based Heuristic 1 Mohammad AlFailakawi a*, Imtiaz Ahmad a, & Suha Hamdan a a Computer Engineering Department, College of Computing Sciences & Engineering, Kuwait University *Corresponding Author: alfailakawi.m@ku.edu.kw ABSTRACT Realization of circuits using Linear Nearest Neighbor (LNN) architecture in technologies such as liquid state Nuclear Magnetic Resonance (NMR) and simple trapped-ions is consider a must. Such restriction increases circuit cost due to introduction of swap gates to bring distant qubit lines in a quantum gate to adjacent ones. In this work, we extend the Harmony Search based heuristic proposed in [1] to find input line ordering to reduce the number of swaps needed by efficient including a local insertion engine that results in near optimal cost for LNN architecture. Experimental results show the efficiency of the proposed approach in term of execution time and quality of the solutions generated. Keyword: Reversible Circuit, Algorithm, Harmony Search, Linear Nearest Neighbor 1. Introduction The interest in quantum computing is growing in exponential rate in recent years. It was demonstrated that quantum computers outperform classical one on a set of problems such as number factoring, database search, and triangle counting in graph algorithms [2] [4]. Moreover, shrinking transistor sizes and high power dissipation are some of the most important bottlenecks in the development of smaller and more powerful circuits for today s computer chips. A key feature of the quantum computation model is reversibility [5]. Reversible circuits are circuits that have one-to-one mapping between their input and output and thus do not lose information during computation. Unlike traditional computation that operates on bits, quantum computation operates on quantum bits, or qubits. Qubits is the unit used to represent quantum information but unlike traditional bits which allow only 0 and 1 state, qubits can be in any superposition of such states. Synthesis for reversible circuits is the first step towards the synthesis of quantum circuits and many have been introduced recently [6] [13]. Optimal algorithms were proposed [8] [10], however, due the intractability of the problem, heuristic methods are preferred for large circuits [7], [12], [13]. Physical realizations of quantum gates require interacting qubit(s) to be physically adjacent [14], [15], which is called Linear Nearest Neighbor configuration. It is common to use a pair of SWAP gates to bring distant interacting qubits of any quantum gate to adjacent lines and maintain correct circuit functionality. Recently, efficient LNN implementations have been reported for a wide range of applications [16] [19]. It has been shown that if a quantum circuit can be 1 This project was supported by Kuwait University Grant No. QE 02/14

2 realized efficiently using an LNN architecture, it can be implemented in other architectures as well [15], [20]. Therefore, LNN architecture is often considered a good approximation of scalable quantum architecture. Several heuristic methods for converting a quantum circuit to its equivalent LNN architecture have been proposed in literature [11], [20] [26]. In this paper, we introduce a Harmony Search (HS) based algorithm to find input line ordering to reduce number of swap gates needed for LNN realization. In addition to global line ordering, the proposed algorithm includes a local heuristic function to properly insert swap gate to limit the number of swaps in the final implementation. The proposed technique is scalable and provides an efficient solution in terms of run time as well as cost when compared to more elaborate approaches for large circuits. The remainder of the paper is organized as follows. In Section II, we present a brief overview of reversible circuits and quantum cost. The problem formulation is discussed in Section III. The proposed algorithm is discussed in Section IV. Experimental results on benchmark circuits are presented in Section V and conclusions are highlighted in Section VI. 2. Reversible Circuits & Quantum Cost A reversible circuit is a circuit that has same number of inputs as outputs with no feedback loops or fan-out. Reversible circuits consist of a cascade of reversible gates. It is common to use quantum gates in such circuits due to their inherit reversibility. Some of the most commonly used quantum gates are given in Figure 1. (a) NOT (b) Controlled-NOT (c) Controlled V+ (d) Controlled V Figure 1: Elementary Quantum Gates It is unlikely to find circuits that realize classical functions implemented using elementary quantum gates; rather, more complex multi-qubit gates are used. One of the most commonly used multi-qubit gate that can implement any reversible function, thus a universal gate, is the multi-control toffoli gate (MCT). Quantum cost refers to the number of elementary gates needed to implement a design. In this work, gates in the NCV gate library constitute the universe of elementary gates used to calculate the cost, nonetheless, for different technology other elementary gates can be used as well [7]. When a reversible function is implemented using complex quantum gates, every gate in such implementation must be decomposed into its elementary counterparts before physical implementation. For example, consider the circuit shown in Figure 2(a) which consist of CNOTs and MCT gates. Decomposing the circuit into primitive gates results in circuit shown in Figure 2(b) using tool proposed in [29]. In technologies such as trapped-ions [30] and liquid-state NMR [31], realization of any design is restricted to only physically adjacent qubits. If the control-target qubits of a gate are physically apart, then SWAP gates must be introduced in order to bring them adjacent to one

3 another. The number of SWAP gates introduced is dependent on how far apart the control-target lines are. SWAP gates are introduced in pairs where the first set is introduced before the gate (to bring qubits together), and the second set is after the gate to restore original qubit order thus maintaining same circuit functionality prior to SWAP introduction. Each SWAP gate consists of three CNOT gates, thus adding such gate to realize LNN increases circuit cost. Therefore, it is important to avoid the introduction of such gates to keep circuit cost and latency low. (a) Original Circuit (b) Decomposed Circuit Figure 2: Benchmark Circuit 4mod5-v1_22 3. Problem Formulation A circuit with n inputs line can be described as a fully connected graph G(V,E jk,w jk (x,y)) with n nodes where V = {1, 2, 3,..., m} are its nodes, E jk an edge between node j and k, and w(x,y) is weight of E jk. Edge weight is given using two values, x which represents number of times two lines interact with each other as target-control pair, whereas y represents distance of the two nodes in the LNN architecture. If the two input lines do not interact with each other, x in this case is equal to 0. As for y, it is calculated using the formula: y jk y y 1 (1) j k where y i refers to nodes j and k index in a linear ordered array. In linear array, non-adjacent node cannot interact with each other directly and must communicate using other nodes. For example, consider node P 1 shown in Figure 3(b), this node can not communicate with node P 4 directly and must go through node P 2 and P 3. Thus the distance value, i.e. y, for this node pair is equal to 2. For example, for the circuit shown in Figure 2(b), graph G is shown in Figure 3(a) where the inputs a through e are ordered linearly (input a assigned node P 1, input b assigned to node P 2...etc). In this graph only five edges have nonzero value for x representing circuit structure, which is fixed, whereas y values are calculated using input order assignment V={1,2,3,4,5}={a,b,c,d,e,f} which would change if input assignment we chosen differently. In order to minimize the cost of a given circuit when implemented in LNN architecture, we proposed input order assignment in such a way to reduce overall SWAP cost SC(G) defined as: n 1 n SC ( G) x jk y jk (2) j 1 k j 1 A harmony search based algorithm that finds input line assignment that minimizes number of

4 swap gates for LNN realization has been previously proposed [1]. In this work, we extend that work by including a local swap insertion heuristic which eliminates the need for swap pairs when possible. This heuristic optimize circuit cost by deciding the best way to perform swap operation for gates with distant qubits as a post processing step after the running the harmony search algorithm to find best global line ordering. Unlike the previous approach used in [1], the proposed algorithm maintains line order after swap gate insertion without performing swapping back. As a motivational example on the impact of the local heuristic, consider the circuit given in Figure 2(b) with input line assignment V={1,2,3,4,5} {a,b,c,d,e,f}. For LNN realization of this circuit, 3 swap pairs (i.e. total of 6 swap gates) are needed in addition to the original 9 gates resulting in total quantum cost to 27. On the other hand, if line reordering is used and inputs are assigned as V={1,2,3,4,5} {a,c,d,e,b} [1], the number of SWAP gates is reduced to two swap pair resulting in total cost of 21 (22% cost reduction) as can be seen in Figure 4(a). Now, if the same circuit is optimized using the proposed algorithm with local optimization, then the number of SWAPs needed would be reduced to only 1 gate (not pairs) as shown in Figure 4(b). This translates to an additional saving of approximately 34% on top of saving found by [1] (or 56% overall saving) which demonstrates the attractiveness of the proposed approach. 0 a e b c 0 3 d 3 (a) Interaction Graph (IG) (b) Processor Graph Figure 3: Interaction and Processor Graph for Benchmark 4mod5-v1_22 4. Proposed Algorithm Harmony Search (HS) is a population-based phenomenon-mimicking algorithm (PMA) which imitates the process of improvising instrument pitches searching for a perfect state of harmony [32]. The search process is performed using factors such as randomness or experience or variation of it. Unlike traditional gradient-based optimization algorithms, HS performs well for both continuous and discrete valued variables [33]. HS algorithm has been applied to various optimization problems such as broadcast scheduling in packet radio networks [34], task assignment in heterogeneous computing systems [35], and line assignment for nearest neighbor realization in LNN architecture [1]. In [1], the HS algorithm has been applied to find input line ordering to optimize quantum circuit by minimizing the swap gates needed to reach LNN realization; however, swaps were introduced in the final realization as pairs where swaps before and after all non-adjacent gates

5 are used as shown in Figure 4(a). In this work, we extend the work in [1] by introducing a local optimization function which optimize global solution (found by HS algorithm) by evaluating the best way to introduce swap gates to realize LNN compatible circuit. The goal of this local function is to eliminate the need for swap gates to restore input lines order to what it was before swap gate insertion. Such optimization might alter the global input order seen by gates as was shown in Figure 4(b). In contrast, in [1], will always restore original line order before processing gates in the circuit if swaps were introduced for earlier ones as it is apparent in Figure 4(a). (a) Solution from [1] (b) Proposed Algorithm Solution Figure 4: Ordered LNN Circuit Realization for 4mod5-v1_22 A top level pseudo code for the proposed algorithm is shown in Algorithm 1. A solution vector is represented by M elements where each element is an integer value between 0 and N-1. M represents the number of tasks and N represent the number of processors. Both N and M have the same value in our formulation of the LNN realization as task assignment problem. The proposed algorithm starts by initializing the Harmony Memory (HM) with a number of valid solutions equal to the Harmony Memory Size (HMS). Initial solutions are generated randomly by permuting integers in the solution array followed by executing the HS procedure to generate a new assignment (i.e. solutions). If the fitness of the newly generated assignment is better than the worst assignment in HM, then the newly generated one replaces the worst one. This process is repeated until the maximum number of iteration is reached. The generation of a new solution starts by selecting a solution from HM and copying it to a candidate new assignment. The candidate new assignment is initially filled with values from HM and is then altered by applying three HS rules which are: memory considerations, pitch adjustments, and randomization. Memory consideration, pitch adjustment, and randomness are applied with a rate equal to Harmony Memory Considering Rate (HMCR), Pitch Adjusting Rate (PAR), and (1-HMCR) respectively. The fitness function used is in the HS algorithm is as described in equation 2. These steps are concisely given in Algorithm 1 using the first and second for loop shown. The best assignment is then is labeled as X best and is used as input to the local optimization heuristic which is described next. Once global lines (qubits) assignment is found (i.e. X best ), every gate in the circuit is processed in order to check if it requires a swap before placing it in the final circuit realization (i.e. final solution). Before inserting a swap, there are choices to be made on how to perform the swap operation in terms of whether control or target line should be moved. For

6 example, consider gate g 2 in Figure 4(a) with its control line located at qubit b and target line located at qubit d. Since the control-target lines are far apart, a SWAP gate is needed to make them adjacent. To do so, we can either move the target qubit down, or move control qubit up. Moving the control line up will directly effect gate g 3 by increasing the distance between its target and control and thus requires another swap gate to be inserted as shown in Figure 5(a). However, if the target qubit of g 2 is moved down instead, this movement will not require a swap gate to be inserted before g 3 as can be seen in Figure 5(b). Therefore, in this case of g 2 gate, moving the target qubit to make it adjacent control one is the better choice here. Finding the best qubit to be moved is the main objective of the local optimization heuristic in the proposed algorithm. (a) Moving Control Qubit (b) Moving Target Qubit Figure 5: Comparison of SWAP choices Algorithm 1: HS Algorithm Input: DAG of circuit; HMS, HMCR, PAR ; N g = Number of iteration; n = Number of qubits; GC= Gate count in netlist ; d i = swaps needed for gate i under current assignment; X best = Best solution found by HS; c i, t i = Control/target qubits of gate i; Output: X Circuit netlist with SWAP gates inserted; For i 1 to HMS Do X i = Randomly permutated the assignment of tasks (nodes) to processors (qubits); fitness[i]=calculate fitness of X i using equation 2; For t 1 to N g Do Apply HS procedures; Xbest Best solution found by HS; For (i = 1 to GC) In X best do d i = Calculate distance between (c i, t i ) of gate i; While (d i 0) Do Find all SWAP options that reduce distance between c i and t i by 1; Choose best SWAP option; Let (s 1, s 2 ) qubits of best SWAP option; X best Insert SWAP gate between qubits (s 1, s 2 ) and before gate i (in order); d i = Calculate distance between (c i, t i ) of gate i after swap insertion;

7 5. EXPERIMENTAL RESULTS The proposed algorithm was implemented in C++ and run on a PC with Intel Core Due 2 processor running at 2.20 GHz with 3GB of RAM under windows 7 operating system. For HS algorithm, parameters were set as follows: HMS=20, HMCR=0.90, PAR=0.3, and termination criterion set to 100,000 function evaluations (FEs). Benchmark circuits from RevLib [36] were used as test cases and we only present the results for a subset of the circuits available. Results of executing the proposed algorithm on the benchmark circuits are shown in Table I. In the table, the second till fifth column give original circuit characteristics where columns Name, GC, QC give name, gate count, and quantum cost of the original circuit after decomposition. The number of SWAPs and cost of LNN realization are given as # Swap and LNN respectively. The remaining columns give # swaps and NCC, and percent reduction in quantum cost for algorithm [1] as compared to original circuit. Results obtained from our proposed algorithm are shown from column #9 to #12, where Red. & diff represent the percent of reduction in quantum cost for our proposed algorithm as compare to the original decompose circuit and as compare to results found by [1] respectively. From the table, it can be seen that on average, the proposed algorithm was able to reduce the LNN cost by 63% as compare to original circuit and by 53% as compared to results found by [1]. The algorithms require negligible run time to find its solution, hence not an issue to be concerned with. Table 1: Reordering Results On Rivlib Benchmarks After Decomposition Results from [1] Proposed Algorithm Name GC QC # Swap NNC # Swap NNC Red. #Swap NNC Red. diff 4mod5-v1_ % % 50% 4_49_ % % 42% 4gt5_ % % 42% 4gt13-v1_ % % 28% 4mod7-v0_ % % 38% alu-v4_ % % 31% rd73_ % % 56% rd53_ % % 41% rd84_ % % 53% cnt3-5_180l % % 58% ham7_ % % 38% cycle10_2_ % % 59% hwb7_ % % 59% sym9_ % % 57% urf2_ % % 61% hwb9_ % % 59%

8 plus63mod4096_ % % 63% urf5_ % % 66% urf6_ % % 63% urf1_ % % 62% plus127mod8192_ % % 68% urf3_ % % 66% Average 28% 67% 53% 6. Conclusion This paper proposes a harmony search with local heuristic to minimize quantum cost of reversible circuits for Linear Nearest Neighbor realization. The proposed algorithm is an extension of our earlier work where a local improvement heuristics is used to further enhance the cost of the realized circuit. The algorithm performance on benchmark circuits was found to reduce quantum by approximately 63% for LNN realization and by 53% as compared to our work in [1]. REFERENCES [1] M. AlFailakawi, L. AlTerkawi, I. Ahmad, and S. Hamdan, Line ordering of reversible circuits for linear nearest neighbor realization, Quantum Information Processing, pp. 1 21, [2] P. Shor, Polynomial time algorithms for prime factorization and discrete logarithms on a quantum computer, SIAM Journal on Computing, vol. 26, no. 5, pp , October [3] L. Grover, Quantum computers can search arbitrarily large databases by a single query, Physical Review Letters, vol. 79, no. 23, pp , [4] F. Magniez, M. Santha, and M. Szegedy, Quantum algorithms for the triangle problem, in 16th annual ACM-SIAM symposium on discrete algorithms, 2005, pp [5] M. Nielsen and I. Chuang, Quantum Computation and Quantum Information. Cambridge University Press, [6] V. Shende, A. Prasad, I.m Markov, and J. Hayes, Synthesis of reversible logic circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp , [7] M. Saeedi and I. Markov, Synthesis and optimization of reversible circuits a survey, ACM Computing Surveys, vol. 45, no. 2, June [8] V. Shende, S. Bullock, I. Markov, Synthesis of quantum-logic circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 6, pp , [9] K. Patel, I. Markov, and J. Hayes, Optimal synthesis of linear reversible circuits, Quantum Information & Computing, vol. 8, no. 3, pp , 2008.

9 [10] O. Golubitsky and D. Maslov, A study of optimal 4-bit reversible toffoli circuits and their synthesis, IEEE Transactions on Computers, vol. 61, no. 9, pp , September [11] R. Wille and R. Drechsler, Bdd-based synthesis of reversible logic for large functions, in 46th Annual Design Automation Conference, 2009, pp [12] R. Drechsler and R. Wille, Reversible circuits: Recent accomplishments and future challenges for an emerging technology, in Progress in VLSI Design and Test, 2012, pp [13] P. Kerntopf, M. Perkowski, and K. Podlaski, Synthesis of reversible circuits: A view on the state-of-the-art, in 12th IEEE Conference on Nanotechnology, August 2012, pp [14] A. Younes and J. Miller, Representation of boolean quantum circuits as reed muller expansions, International Journal of Electronics, vol. 91, no. 7, pp , [15] D. Maslov, G. Dueck, and D. Miller, Techniques for the synthesis of reversible toffoli networks, ACM Transactions on Design Automation of Electronic Systems, vol. 12, no. 4, no.42, [16] Y. Takahashi, N. Kunihiro, and K. Ohta, The quantum fourier transform on a linear nearest neighbor architecture, Quantum Information & Computation, vol. 7, no. 4, pp , [17] Y. Takahashi, N. Kunihiro, and K. Ohta, The quantum fourier transform on a linear nearest neighbor architecture, Quantum Information & Computation, vol. 7, no. 4, pp , [18] S. Kutin, Shor s algorithm on a nearest-neighbor machine, in Asian Conference on Quantum Information Science, [19] B. Choi and R. Meter, On the effect of quantum interaction distance on quantum addition circuits, ACM Journal on Emerging Technologies in Computing Systems, vol.7, no.3, no.11,2011. [20] A. Fowler, C. Hill, and L. Hollenberg, Quantum error correction on linear nearest neighbor qubit arrays, Physical Review A, vol. 69, no. 4, pp , [21] D. Cheung, D. Maslov, and S. Severini, Translation techniques between quantum circuit architectures, in Workshop on Quantum Information Processing, [22] K. Patel, I. Markov, and J. Hayes, Efficient synthesis of linear reversible circuits, in International Workshop on Logic Synthesis, June 2004, pp [23] B. Schaeffer and M. Perkowski, Linear reversible circuit synthesis in the linear nearest-neighbor model, in 42 nd IEEE International Symposium on Multiple-Valued Logic, 2012, pp [24] Y. Hirata, M. Nakanishi, S. Yamashita, and Y. Nakashima, An efficient method to convert arbitrary quantum circuits to ones on a linear nearest neighbor architecture, in

10 Third International Conference on Quantum, Nano and Micro Technologies, February 2009, pp [25] M. Saeedi, R. Wille, and R. Drechsler, Synthesis of quantum circuits for linear nearest neighbor architectures, Quantum Information Processing, vol. 10, no. 3, pp , June [26] M. Perkowski, M. Lukac, D. Shah, and M. Kameyama, Synthesis of quantum circuits in linear nearest neighbor model using positive davio lattices, Electronics and Energetics, vol. 24, no. 1, pp , [27] A. Chakrabarti, S. Sur-Kolay, and A. Chaudhury, Linear nearest neighbor synthesis of reversible circuits by graph partitioning, vol. v2[cs.et], [28] M. Arabzadeh, M. Saeedi, and M. S. Zamani, Rule-based optimization of reversible circuits, in 15th Asia and South Pacific Design Automation Conference, January 2010, pp [29] V. Shende and I. Markov, On the cnot-cost of toffoli gates, Quantum Info. Comput., vol. 9, no. 5, pp , [30] M. Arabzadeh and M. Saeedi, RCViewer+, available at [31] H. H affner, W. H ansel, C. F. Roos, J. Benhelm, D. C. al kar, M. Chwalla, T. K orber, U. D. Rapol, M. Riebe1, P. O. Schmidt, C. Becher, O. G uhne, W. D ur, and R. Blatt, Scalable multiparticle entanglement of trapped ions, Nature, vol. 438, no. 7068, pp , Dec [32] C. Negrevergne, T. S. Mahesh, C. A. Ryan, M. Ditty, F. Cyr-Racine, W. Power, N. Boulant, T. Havel, D. G. Cory, and R. Laflamme, Benchmarking quantum control methods on a 12-qubit system, Physical Review Letter, vol. 96, p , [33] Z. W. Geem, J. Kim, and G. Loganathan, A new heuristic optimization algorithm, SIMULATION, vol. 76, no. 2, pp , [34] Z. W. Geem, Music-Inspired Harmony Search Algorithm: Theory and Applications. Springer,2009. [35] I. Ahmad, M. Mohammad, A. Salman, and S. Hamdan, Broadcast scheduling in packet radio networks using harmony search algorithm, Expert Systems with Applications, vol. 39, no. 1, pp , [36] A. A. Salman, I. Ahmad, H. Al-Rushood, and S. Hamdan, Solving the task assignment problem using harmony search algorithm, Evolving Systems, [37] R. Wille, D. Grosse, L. Teuber, G. W. Dueck, and R. Drechsler, Revlib: An online resource for reversible functions and reversible circuits, in 38th IEEE International Symposium on Multiple Valued Logic, May 2008, pp