!. 2) 3. '45 ( !"#!$%!&&' 9,.. : Cavity QED . / 3., /*. Ion trap 6..,%, Magnetic resonance Superconductor

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Verity Chloe Flowers
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1 0 1!"#!$%!&&' ()*+,-! 2) 3 '45 ( 0 9, : 3, * 6,%, Cavity QED Magnetic resonance Ion trap Superconductor

2 7 : ) :; 1 ( 6 7<7,! 97 =&&&>? 2 + ' - < *6 97 <%, A 4#7,5 B1&&C:5C:D A<,,%E&#"&F <7-7<7 11<7 %1! ) 3,, ) 6 %, -,5 % 7B D 7 7, G 6 775, -% , H 9 3, 7 <7 G<@

#- L400µ m W4µ m H10µ m s2 1µ m l300µ m t0 25µ m w 4µ m Qubits are represented in the electron spin of ions; the ions are physically moved around to bring them together to perform two-qubit gates

3 #- L400µ m W4µ m H10µ m s2 1µ m l300µ m t0 25µ m w 4µ m Qubits are represented in the electron spin of ions; the ions are physically moved around to bring them together to perform two-qubit gates Gates are laser pulses that cause the qubits to rotate -73 db z dz = 14 Tµm B 0 = 7 T Active region 100µm x 02µm 3, 4 The behavior of those two systems is completely different! We need a way to describe architecture, the way DiVincenzo describes technology 36,,,<7 I 7 B=?D

4 36,B!D, <J0 5 7, *6, B% D 6 < )7#, < B 5,<7 I77,D Two-qubit operation for charge qubit Closer look Two-qubit device (preliminary) Qubit 1 Qubit 2 Where will you put qubit 3? A Barenco, D Deutsch, A Ekert, and R Jozsa, Phys Rev Lett 74, 4083 (1995) cf Two-qubit CNOT gate in superconducting charge qubit T Yamamoto, Nature 425, 941 (2003) Measurement device not included in this one! (see next slide) Control leads

35 - #*3 Γ L ~ Γ R (V δ = 0) Bandwidth ~ 100 MHz Sensitivity ~ 3x10-6 ehz -12 (C c1 C c2 )C Σ = 001 003 Charge detection time: ~ 10-100 ns (optimistic

) A Aassime et al, Phys Rev Lett 86, 3376 (2001) S Gardelis et al, Phys Rev B 67, 073302 (2003) J Elzerman et al, Phys Rev B 67, R161308 (2003) L C L

Science 280, 1238 (1998) H D Cheong et al, Appl Phys Lett 81, 3257 (2002) L = 100 nh C ~ 06 pf f res ~ 650 MHz C c C Σ ~ 001 charge detection limit

phosphorus atoms embedded in a zero-spin silicon substrate Standard VLSI gates on top control electric field, allowing electrons to read nuclear state

5 35 - #*3 Γ L ~ Γ R (V δ = 0) Bandwidth ~ 100 MHz Sensitivity ~ 3x10-6 ehz -12 (C c1 C c2 )C Σ = Charge detection time: ~ ns (optimistic expectation) (T 1 = 10 ns 1 µs?) A Aassime et al, Phys Rev Lett 86, 3376 (2001) S Gardelis et al, Phys Rev B 67, (2003) J Elzerman et al, Phys Rev B 67, R (2003) L C L Hollenberg et al, Phys Rev B 69, (2004) L DiCarlo et al, cond-mat RFSET: radio-frequency single-electron transistor R Schoelkopf et al, Science 280, 1238 (1998) H D Cheong et al, Appl Phys Lett 81, 3257 (2002) L = 100 nh C ~ 06 pf f res ~ 650 MHz C c C Σ ~ 001 charge detection limit (@~10kHz) ~ 5x10-5 ehz 12 for RFSET ~ 5x10-3 ehz 12 for the upper QD (BW ~ 40 khz) K- #-4 KJ0 Qubits are stored in the spin of the nucleus of phosphorus atoms embedded in a zero-spin silicon substrate Standard VLSI gates on top control electric field, allowing electrons to read nuclear state and transfer that state to another P atom Kane, Nature, 393(133), 1998 Black dots are location of P atoms Small rectangles are quantum-scale leads Large squares are standard-size VLSI leads Fitting it all in is tough! This is the role of system architecture Oskin et al, ISCA, 2003

6 1D chain ) 7!), 2xN 3xN Triangular ladder Next-nearestneighbor (same as trilad) Even achieving scalable form of any of these will be an accomplishment!,* *< 6-5 6%< 35 5 < *5 6## 7, *55 7, B5D, ( ,7 4<! *6, *< < C,< * < 6, <7 6 7% <,7 3% #, <, <7

-7 3 One of the few architectures that separates storage space from action space; that is, memory and

(Other groups including Oxford also doing small-scale ion trap) 3#9 02 mm Wineland group, NIST Boulder

&&'D -73 I Scaling: mictrotraps (WinelandNIST) Large-scale QC?

Substrate Ion RF Paul Trap Segments Substrates with attached electrodes for ion trapping and control

7 -7 3 One of the few architectures that separates storage space from action space; that is, memory and CPU Main group is Wineland group at NIST (USA); Chuang group at MIT also making excellent progress (Other groups including Oxford also doing small-scale ion trap) 3#9 02 mm Wineland group, NIST Boulder )# : H A %4!1%L B!&&2D <7 ( %99 ''1B!&&1D H ( 5%!%!'" B!&&!D 2#<7 83 %- 2&LB!&&'D -73 I Scaling: mictrotraps (WinelandNIST) Large-scale QC? Teleportation can be used for wiring & code conversion Gate errors ~ O(10-4 ) possible Electrode Substrate Ion RF Paul Trap Segments Substrates with attached electrodes for ion trapping and control Ions in linear chains Space Qubits are hyperfine states Qubits are coupled through collective vibrations Lasers implement logic gates and measurement Kielpinski et al, Nature v417, p 709, 2002

8 A 3,, 35#<7 <7 7 BD data Quantum Circuit Layout and Physical Operations P M 0 P M P = Prepare M = Measure 0 = Initialize 3 A E P M P M Error Syndrome R Layout to Any Rec ursion Depth 9 +, 9 : CPU Entropy Exchange Unit Memory

) A) 8% -7 9 7 8) )5, )5 8 Taking a page from the design of classical computers 359-7, 359-7, Caltech

clearly won But the real lesson is not One Big v Lots of Little; the lesson is that a group of computers

in a network to create a larger system Cray 1, 80MFLOPS, 8MB RAM, $9M, 1976 Two choices: Make it bigger,

9 ) A) 8% ) )5, )5 8 Taking a page from the design of classical computers 359-7, 359-7, Caltech Cosmic Cube, 64 processors (80867) 3MFLOPS, 8MB RAM, 1982 (prototype) Paralleldistributed computing has clearly won But the real lesson is not One Big v Lots of Little; the lesson is that a group of computers can solve problems that an individual computer cannot Even the biggest individual computer can be combined in a network to create a larger system Cray 1, 80MFLOPS, 8MB RAM, $9M, 1976 Two choices: Make it bigger, or figure out how to connect more than one smaller unit hopefully achieving both speed and storage capacity increases

10 35 9, 9-7, %, ), 7 =? # < Two choices: Make it bigger, or figure out how to connect more than one smaller unit hopefully achieving both speed and storage capacity increases , # 5 5, % 7 % - M,% < 0B N!D 7 7, 3 I 0B N2D 5 0B N! 7 7 B?I = 8 5 # : C 5 M % B 83D 83% 7 D, B, 6, 31& D % D 5J 6,

11 ) 7 ( -M I C5, 7#,I 3 6,7B5D, 6 %H%A%O, : 7 % % 7% : *P 7%5J3 35#<7, 435#<7 % 7, 431),%4 70,,# Swap Swap gate Swap gate Swap gate O(n) latency on all architectures Carry ripples one bit at a time (Can use concurrent gates here, but limited above) Position first, then do action gates Only 1 new neighbor after each swap What's the performance penalty? (Variants used in both major exponentiation algorithms, VBE (quant-ph ) and BCDP (quant-ph ))

12 O(n) latency on all architectures Carry ripples one bit at a time,# (Can use concurrent gates in first time slot, then limited) (Variants used in both major exponentiation algorithms, VBE (quant-ph ) and BCDP (quant-ph )) #- O(log n) latency when long-distance gates are easy O(n) when swap required (NTC architecture) -- with a big constant! Better use of concurrent gates (total still O(n) or larger) (Carry-save and carry-lookahead are other types that reach O(log n) See quant-ph , quant-ph ) #-BD #-B43D O(log n) latency when long-distance gates are easy O(n) when swap required (NTC architecture) -- with a big constant! Better use of concurrent gates (total still O(n) or larger) O(log n) latency when long-distance gates are free O(n) when swap required (NTC architecture) -- with a big constant! Better use of concurrent gates (total still O(n) or larger) (Carry-save and carry-lookahead are other types that reach O(log n) See quant-ph , quant-ph ) (Carry-save and carry-lookahead are other types that reach O(log n) See quant-ph , quant-ph )

13 ,*6B1!L7 D AC gates perf TC gates perf NTC gates perf VBE 125E E E+08 1 BCDP 496E E E VBE (100n) 756E E E BCDP (100n) 253E E E A 265E E E B 371E E E C 122E E E D 219E NA NA B, C, D, E, VBE(100n), BCDP(100n) use 100n storage; others use 5n-7n gates for AC are CCNOT, others are CNOT 8 47 '"E7 5 %'1!7 1&9% '1!7 < '%, B H)9 D!L&&C: "LC:!#<7 1&&%, B *%D 112C: &C:!#<

14 8 47 -, H 6 0BN2D5J 00BN!D %, 9"1%&'!2!&% <#J&&L&&E 85&&!1$EQ) &&L&L1 0!), *, Does it give us an asymptotic change in O()? Single line layout 3xM layout 0 A lot is known about the computational complexity of circuits on arbitrary-interconnect machines; a little is known about circuit depth 2-qubit gate Neighbor only operations require swapping qubits swap qubit values 3xM layout roughly twice as efficient 3 new neighbors after each swap = 23 reduction in swaps We and a few others (Fowler et al) have investigated circuits on linear nearest neighbor (LNN or NTC) architectures Almost nothing is known about efficient circuits for 2D layout, lattices, scalable ion trap, etc

15 3 ) 7 7, 5, K,,%R<7 %, H % % 5@ B,D -7%,7

Short Course in Quantum Information Lecture 8 Physical Implementations

Short Course in Quantum Information Lecture 8 Physical Implementations Course Info All materials downloadable @ website http://info.phys.unm.edu/~deutschgroup/deutschclasses.html Syllabus Lecture : Intro