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1 Th docuet dowloaded fro DR-NTU, Nayag Techologcal Uverty Lbrary, Sgapore. Ttle A New Ufed Modular Adder/Subtractor for Arbtrary Modul Author() Tay, Tha Fatt; Chag, Chp-Hog Ctato Tay, T. F., & Chag, C.-H. (5). A New Ufed Modular Adder/Subtractor for Arbtrary Modul. 5 IEEE Iteratoal Sypou o Crcut ad Syte (ISCAS), Date 5 URL Rght 5 IEEE. Peroal ue of th ateral pertted. Pero fro IEEE ut be obtaed for all other ue, ay curret or future eda, cludg reprtg/republhg th ateral for advertg or prootoal purpoe, creatg ew collectve work, for reale or redtrbuto to erver or lt, or reue of ay copyrghted copoet of th work other work. The publhed vero avalable at: [

2 A New Ufed Modular Adder/Subtractor for Arbtrary Modul Tha Fatt Tay ad Chp-Hog Chag School of Electrcal ad Electroc Egeerg, Nayag Techologcal Uverty, Sgapore. Abtract Effcet odular adder ad ubtractor for arbtrary odul are key booter of coputatoal peed for hghcardalty Redue Nuber Syte a they rely o arbtrary odul et to expad the dyac rage. Th paper propoe a ew ufed odular adder/ubtractor that poee a regular tructure for ay odulu. Copared to the latet odular adder/ubtractor, whch work for odulu the for of ±k, the propoed deg o average.8% fater ad coue 5.85% le hardware area ad.5% lower power for ragg fro 4 to 8. I. INTRODUCTION Redue Nuber Syte (RNS) ha becoe a prog alteratve uber yte for dgtal yte pleetato recet year. The key ucce for RNS-baed coputato t carry-free addto ad ubtracto redue doa. Bede, RNS-baed coputato are alo heretly faulttolerat. Attept to leverage RNS for the accelerato of fat Fourer trafor (FFT) ad dcrete coe trafor (DFT) coputato have bee ade []-[3]. The deg [] pleet odular ubtracto by ubtractg the ubtrahed fro the correpodg odulu followed by the odular addto. Th ethod avod the ue of fued adder/ubtractor but requre addtoal cotat ubtracto, whch pact the peed. The data path of deg [] ad [3] are heavly occuped by addto ad ubtracto. The overall peed of the yte thu predoated by how well thee odular adder ad ubtractor are optzed. Modular adder ad ubtractor for arbtrary odulu are geerally ore coplex tha ther tadard bary couterpart, whch lead to the log-tadg teret the odul et {,, +}. Due to the ed-aroud ad copleetary ed-aroud carry properte, hardware pleetato of odular ± addto ad ubtracto ca be ade a effcet a ther bary couterpart. The proble wth th pecal odul et t lted dyac rage or parallel. I order to expad the dyac rage of the RNS wth al egatve pact o the arthetc peed, extra copre odul of coparable word-legth have to be added. Th ake obtag balaced hgh-cardalty odul et wthout coderg other for of odul poble. It becoe apparet that a ufor ad effcet pleetato of odular adder ad ubtractor for arbtrary odul are very portat for large dyac rage applcato. A odular addto ad ubtracto ay ot be ued cocurretly, t wll be beefcal to ufy the to a gle fuctoal ut wth a pleetato cot lower tha the cobed cot of a odular adder ad a odular ubtractor. Several ufed odular adder/ubtractor have bee reported [4]-[6]. The ufed odular adder/ubtractor [4] deged for arbtrary odul. It cotructed ug decoder, odfed barrel hfter, ad read-oly-eory (ROM). The rotate logc coue eorou hardware area, whch hghly effcet for large odul. The a cotrbuto of [5] the propoal of parallel prefx dhed- odulo + ubtractor that ca hadle zero operad. The propoed ubtractor ca be ealy trafored to a ufed adder/ubtractor wth addtoal logc gate. It ha ple ad regular tructure but dedcated to odulo + operato oly. The tate-of-the-art ufed odular adder/ubtractor [6] deged for odul the for of ±k. The odulo k adder/ubtractor ha exactly the ae archtecture a that of odulo +k operator, cotg of ultple carry ave adder (CSA), ultplexer (MUX) ad bary adder, except for the correcto factor. It overall peed lted by the ultlevel carry ave addto. I th paper, a ew ufed odular adder/ubtractor for arbtrary odul propoed. The propoed odular adder/ubtractor ca be ealy odfed to pleet odulo addto/ubtracto for dfferet odul wth the ae by chagg the put cofgurato of MUX. Owg to t plcty, the propoed deg fater tha the le veratle tate-of-the-art deg [6] for all odul of = 4 to 8. II. PROPOSED UNIFIED MODULAR ADDER/SUBTRACTOR A. Backgroud I a RNS fored by N copre teger {,,..., N }, a teger X ca be repreeted by ug a N-tuple (x, x,, x N ), where ad x are kow a odulu ad redue dgt, repectvely. x coputed by fdg the leat o-egatve reader of X dvded by ( x = X ). Let Z be the reult of a arthetc operato acted upo teger, X ad Y. The ( z, z,, zn ) = ( x y, x y,, x N yn ) () N where deote addto, ubtracto or ultplcato. B. Algorth Forulato Let be a arbtrary potve teger the rage [ +, ], where = log ad. the greatet teger fucto. The ubtracto of y fro x odulo ca be forulated a: + f < = () x y f x y where x ad y are teger the rage [, ].

3 The vald rage of ay odulo operato ha to be [, ]. Upo detectg that x y le th, added to ap the reult to the rage [, ]. Equato () ca thu be trafored to the odular addto of three teger a follow: ( ) ( ) ( ) = x+ y = x+ y+ + = x+ y+ c where y the oe' copleet of y ad c = + a cotat. Sce x+ y + c [ +, 3 ], () ca be rewrtte a: x+ y + c f x+ y + c< 3 = (4) x + y + c f + x + y + c < The detecto of the rage of x + y+ c (4) dffcult to pleet o hardware. It volve the coparo of ultple bt depedg o the word-legth of. Lea : ca be coputed by: + x+ y + f x+ y+ + = (5) x y f x y + < < Proof: Whe + x+ y + +, x+ y+ = x+ y + + = x+ y + + (6) = x+ y + c+ ( + ) = x+ y + c + Whe x+ y + + <, x+ y + + = x+ y + + = x+ y + c+ ( + + ) (7) = x+ y + c Hece, the rage for (4) ca be ubttuted by thoe of (5). The rage detecto crcut ca be further plfed by otcg that whe + x+ y + +, x+ y+ + wll ever fall to the rage (, +), whch ca be proved by + x+ y + + x+ y (8) x+ y Therefore, (5) ca be plfed to: + x+ y+ f x+ y + + = (9) x y otherwe. The codto of (9) ca be detected by the ot gfcat bt (MSB) of ( x+ y+ + ), whch ca be ealy pleeted o hardware. O the other had, the odulo addto of x ad y ca be forulated by [7]: x+ y+ f x+ y+ x+ y = () x + y otherwe. (3) Whe x + y + <, x+ y = x+ y alway true. Thu, () ca be rewrtte a: x+ y f x+ y+ + < x+ y = () x y otherwe. where + =. The codto of () ca be ealy detected by the MSB of x+ y+ +. Coparg (9) ad (), t oberved that the coputato of ad x+ y hare oe coo ter. By troducg a bary varable, the odular addto ad ubtracto ca be ufed to: f = '' ad v< w + x+ ( ) y = or = '' ad w () v otherwe. w x y v = x+ y + = ad ( ) where ( ) ( ) ( ) +. Modular addto perfored by ettg = '' ad odular ubtracto by = ''. The operato a perfor a btwe excluve-or of every bt of a wth. Exaple : Coder =. = log = 4. Let x = 8 ad y = 5. If = '', the w = = 9 ad v = = 8. Fro (), ce = '' ad v > = 6, v = 8 = coputed, whch the ae a x+ y = =. If = '', the w = = 35 ad v = = 3. Sce = '' ad w > + = 3, w = 35 = 3 elected, whch equal to = = 3. C. Crcut Archtecture Fg. depct the coputato of w ad v fro () for = ad = 4. The ter dotted-le boxe are ued oly for the detecto of the codto of v < ad w +. They are ot volved the addto operato for w ad v. The coputato of w ad v cot of two level of addto. The frt level volve the addto of the frt x y x+ y + + ad ( ) three ter,.e., ( ) ( ) ( ) +, for the coputato of w ad v, repectvely. Sce oe of the ter a cotat, th frt level of addto ca be pleeted ug half-adder-lke () cell propoed [8]. The pleetato how Stage of Fg., where a ad b + are the u ad carry ter, repectvely ad the cotat bt at poto. The ecod level of addto Fg. volve a for, b for, ad the fourth ter w ad v coputato, whch for w coputato ad for v coputato. It ca be pleeted ug two parallel prefx adder (PPA) a how Stage of Fg.. The PPA for v coputato requre addtoal ut of -to- put MUX becaue the u ad carry ter to be added whe = '' are dfferet fro thoe whe = '', a how Fg.. The fal tage of the ufed odular adder/ubtractor elect ether w or v a output. The codto ()

4 ca be pleeted by ple logc gate depcted Stage 3 of Fg.. The ufed odular adder/ubtractor archtecture ha a regular tructure. It ca pleet odular addto or ubtracto for ay the rage [ 3 +, 4 ] by chagg the put cofgurato of the MUX Stage. Stage Stage Stage 3 w coputato w x ( y ) ( ) ='' ='' : + + x x y 3 y y a a b b + w w w x x y 3 y y a a b b + w w w v coputato v= x+ y + + ='' ='' : : = ( ) ( ) x x + y 3 y y a a + b b v v v x x + y 3 y y a a + b b v v v Fg. : Coputato of w ad v for = ad =4. y 3 a 3 b a w x y a b a w a w b x y a b a b b a a v b b b v b a a w3 w w v v w v z 3 z z z Fg. : The propoed ufed odular adder/ubtractor for = ad =4. III. EVLUATION AND COMPARISON I th ecto, the propoed ufed odular adder/ubtractor depcted Fg. evaluated ad copared agat the latet deg [6]. The deg are frt aalyzed ug ut-gate odel [9] before they are ythezed ad optzed. Two deg are propoed [6], whch are Adder/ubtractor I ad Adder/ubtractor II. The forer ca be pleeted for odul the for of k ad + k but the latter lted to oly odul of for + k for odd k ad ha o peed ad area advatage whe le tha accordg to the ythe reult Fg. 6 of [6]. Therefore, the adder/ubtractor I for odul k pleeted for coparo. The perforace of the propoed deg ad adder/ubtractor I are aalyzed wth = 4, 5, 6, 7, ad 8. For each, three odul the for of + 3, ad 3 are choe. A. Ut-gate Aaly The ut-gate aaly perfored baed o the odel [9], where a two-put ootoc logc gate, uch a AND, OR, NAND ad NOR, codered to have oe ut of area ad oe ut of delay; Both XOR gate ad MUX have two ut of area ad two ut of delay; The area ad delay of a verter are aued to be eglgble [9]. I addto, the area ad delay of a full adder are couted a eve ut ad four v ut, repectvely []. Each cell Stage of the propoed ufed adder/ubtractor ha four ut of area ad two ut of delay each [8]. Sce Stage cot of cell ad XOR gate, t total area ad delay are 6 ut ad 4 ut, repectvely. I Stage, two PPA are requred for w ad v coputato. Sce there oly oe put at the leat gfcat bt (LSB) poto, the propagate, geerate ad half-u geerato of PPA for v coputato ca be plfed. Thu, the total area ad delay of Stage cluve of the MUX are 3 log ut ad log + 5ut, repectvely. Stage 3 cot of two OR gate, two AND gate, oe NOR gate ad MUX. Thu, Stage 3 ha +5 ut of area ad 3 ut of delay. All all, the propoed ufed odular adder/ubtractor ha a overall area of 3 log ut ad a delay of log + ut a how Table I. Table I: Ut-Gate Area (A) ad Delay (D) of the Propoed Deg. Stage Stage Stage 3 Total XOR MUX PPA (for w) PPA(for v) gate MUX A log.5 log 5 3 log D log log + Table II how the ut-gate area ad delay of adder/ubtractor I calculated baed o the archtecture depcted Fg. ad Fg. (b) of [6]. A uggeted [6], the bary adder add 3: ca ether be pleeted ug PPA or carry propagate adder (CPA). The PPA adder/ubtractor I aued to have the ae ut gate area ad delay a our propoed deg. Fro Table II, the total area ad delay of the PPA odel are 3 log ut ad log + 4 ut, repectvely, wherea the total area ad delay of the CPA odel are ut ad 4 9 ut, repectvely. By coparg Table I ad II, the propoed deg ut ad 3 log + 7 ut aller tha the PPA ad CPA pleetato of adder/ubtractor I, repectvely, ad ut ad 4 log + 7 ut fater tha the PPA ad CPA vero of adder/ubtractor I, repectvely. Table II: Ut-Gate Area (A) ad Delay (D) of Adder/Subtractor I [6] add 3: MUX XOR Total CSA Logc Logc MUX Adder A B A (PPA) 3 log 3 log A (CPA) D (PPA) log log D (CPA) B. Logc Sythe Reult The propoed deg ad the PPA ad CPA vero of [6] are pecfed Verlog HDL at gate level, fuctoally verfed ug ModelS, ad ythezed ad techology apped to STM 65 CMOS techology tadard cell lbrary

5 ug Syopy Deg Copler. Each deg depedetly ad recurvely optzed for u achevable delay. The ythezed area ad delay of the propoed deg, [6] (PPA), ad [6] (CPA) are tabulated Table III. Copared wth [6] (PPA), the propoed deg at leat 4.48%, 6.%, 3.89%, 3.8% ad.74% aller for = 4, 5, 6, 7 ad 8, repectvely. Copared wth [6] (CPA) wth odul the for of + 3 ad 3, the propoed deg at leat 5.8%, 9.85%, 9.3%, 6.4% ad.37% aller for = 4, 5, 6, 7 ad 8, repectvely. For odul the for of, accordg to (9) of [6], the cotat k ad k are the for of l, where l a teger le tha. Sce k ad k are fed a oe of the three put, the tructure of the CSA ad MUX add 3: ca be ealy optzed to acheve aller area. Furtherore, CPA geerally coue aller hardware area copared to the PPA pleeted our propoed deg. Thee expla the aller area of [6] (CPA) tha our propoed deg for odul whe = 6, 7 ad 8. I ter of delay, our propoed deg at leat.96%, 6.76%, 7.79%, 7.69% ad 6.33% fater tha [6] (PPA) for = 4, 5, 6, 7 ad 8, repectvely. The peed proveet of the propoed deg over [6] (CPA) are ore tha 7.5%, 5.56%, 7.89%, 8.86% ad 9.76% for = 4, 5, 6, 7 ad 8, repectvely. Table III: Coparo of Sythezed Area ad Delay (Value Parethe Idcate the Percetage Reducto of Propoed Deg Over the Coteder) Sythezed Area (μ ) Sythezed Delay () Th [6] (PPA) [6] (CPA) Th [6] (PPA) [6] (CPA) (35.36) 666(5.8).64.73(.33).74(3.5) (4.48) 65(5.69).64.73(.33).69(7.5) (3.9) 65(6.98).65.73(.96).7(9.7) (33.67) 83(4.78).68.75(9.33).78(.8) (6.) 778(.6).68.76(.53).7(5.56) (9.) 834(9.85).69.74(6.76).76(9.) (9.5) 4(3.96).7.77(9.9).8(4.63) (3.89) 876( 6.9).7.77(9.9).76(7.89) (3.74) 97(9.3).7.77(7.79).8(3.4) (3.4) 85(6.4).7.79(8.86).88(8.8) (3.8) 37(.65).7.78(7.69).79(8.86) (9.47) 4(9.6).7.8(.).86(6.8) (.74) 7(.37).73.8(8.75).9(9.78) (4.48) ( 4.5).74.79(6.33).8(9.76) (6.98) 3(3.7).73.8(8.75).9(8.89) Table IV how the total power dpato ad leakage power of the propoed deg ad the coteder. The power coupto are eaured ug Syopy PreTe PX at the ae upply voltage of V ad the ae clock rate detered by the lowet deg of Table III for each. Mote Carlo ulato ethod [] adopted where a fte uber of radoly geerated tet patter are erted to etate the average power dpato wth 99% cofdece that the error bouded belo%. Fro Table IV, the total power coupto of the propoed deg are ore tha thoe of [6] (PPA) ad [6] (CPA) wth odul due aly to the ore favorable logc optzato of [6] (PPA) ad [6] (CPA) archtecture explaed earler. Noethele, for odul +3 ad 3, the propoed deg coue le power copared to the coteder for all. I ter of leakage power, the propoed deg coue le power copared to [6] (PPA) for all except for =. Copared wth [6] (CPA), the leakage power of the propoed deg lower for all except for =, 48 ad 9. Table IV: Coparo of Total ad Leakage Power (Value Parethe Idcate the Percetage Reducto of Propoed Deg Over the Coteder) Total Power (μw) Leakage Power (μw) Th [6] (PPA) [6] CPA Th [6] (PPA) [6] (CPA) (3.89) 94(9.9) (38.55) 39.83(9.8) ( 5.) 85(.37) (.6) 35.5( 3.7) (.5) 863(8.6) (3.77) 36.6(3.46) (.3) (.7) (35.59) 5.(.58) (.7) 986( 4.) (.6) 47.(7.5) (.57) 46(.44) (3.43) 5.(.9) (.) 34(9.8) (34.3) 6.6(7.69) (.36) 57( 3.6) (.57) 5.39( 7.88) (7.8) 33(.8) (33.75) 59.3(3.66) (8.99) 57() (36.) 59.39(3.3) (.87) 7(.5) (9.73) 6.75(.) (8.7) 59(8.9) (3.74) 7.88(6.59) (.59) 58( 6.98) (9.78) 75.83(.79) (.78) 56( 3.8) (3.8) 6.6( 7.9) (6.6) 553(.48) (3.76) 73.7(8.74) IV. CONCLUSION By chagg the rage electo crtera of odular ubtracto, odular addto ad ubtracto for ay odulu ca be elegatly erged. The plfcato of rage detecto crtera lead to a regular ufed odular adder/ubtractor archtecture. I ot cae, the propoed deg fater, aller ad coue le power tha the latet deg [6]. Referece [] R. B. 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