Speaker. Low- Pass Filter. D/A Converter. Power Amp. Counter. Memory. Clock

Transcription

1 Maachuett Intitute of Technology Department of Electrical Engineering and Computer Science 6.00 { Electronic Circuit Homework # Solution Handout F9806 Iued /0/98 { Due /4/98 Introduction Thi homework aignment focue on the analyi and deign of a ytem for playing back a digitallytored audio ignal. Additionally, thi aignment ere a the prelab exercie for Lab #4, which will inole the contruction, teting and demontration of the audio playback ytem. Conequently, you hould ae a copy of your reult for ue during Lab #4. A block diagram of the audio playback ytemihown in Figure. At the center of the ytem i a digital memory in which 3,768 ample of the audio ignal are tored. Each ample in the memory ha a unique numerical addre between 0 and 3,767, incluie. Conecutie ample are tored at conecutie addree. To obtain 3,768 conecutie ample of the audio ignal, econd of continuou analog audio ignal are rt ampled at an 8kHz rate. The analog audio ample are then digitized by an 8bit analogtodigital conerter. That i, the ample are quantized to take on one of 56 poible dicrete digital alue between 0 and 55, incluie. Here, the digital alue of 0 correpond to the mot poitie ignal oltage, and the digital alue of 55 correpond to the mot negatie ignal oltage. The reulting digital data i then written into the memory. To retriee the tored audio ignal ample in equence at the proper rate, the memory i addreed by a counter which count from 0 to 3,767 at an 8kHz rate etablihed by an external clock. After counting to 3,767 the counter return to 0, and the retrieal proce repeat itelf. A the memory addre increment, the correponding data appear at the memory output. Thi data i conerted back to an analog oltage in a piecewie contant manner by a digitaltoanalog conerter. During the coure of recording and playing back the analog audio ignal, the ignal i ampled in time, quantized in amplitude, and recontructed in a piecewie contant manner. A you will Speaker Clock Counter Memory D/A Conerter Low Pa Filter Power Amp Figure : block diagram of the audio playback ytem.

2 learn in 6.003, thi proce introduce undeirable highfrequency component into the ignal. To minimize the perceied impact of thee component, the ignal i ltered by a lowpa lter after it i recontructed by the digitaltoanalog conerter. Finally, the ignal i amplied by a power amplier which in turn drie a peaker. The power amplier i neceary becaue the lowpa lter i not capable of driing the peaker directly. In the coure of thi homework aignment you will analyze and deign four of the functional block hown in Figure. Thee block are the clock, the digitaltoanalog conerter, the lowpa lter and the power amplier. In Lab #4, you will contruct thee block and erify that they perform a deired. Then, you will combine them with the counter, the readonly memory and the peaker to contruct and demontrate the entire audio playback ytem.since you will contruct the ytem from the component in the 6.00 lab kit, your deign of the block mut account for the fact that the aailable component are limited. Problem : The Clock The circuit hown in Figure i a quarewae ocillator followed by a MOSFET inerter, which together function a the ytem clock. The opamp in the ocillator i powered between the upply oltage of 5 V, and o it output i retricted to fall within thi range. Otherwie, aume that it i ideal. Note that the ocillator employ poitie feedback around the opamp o that the opamp output OSC i alway drien to one of the power upply extreme, namely to 5 V or,5 V, depending on the ign of (,,) at the opamp input. The role of the MOSFET inerter i to limit the output oltage of the clock to that which can be tolerated by the counter which the clock drie. The maximum tolerable input oltage to the counter i 5 V, and the minimum tolerable input oltage i 0 V. An input oltage outide thi range could damage the counter. Therefore, to guarantee that the clock output oltage CLK neer exceed thi range, the inerteripowered between 5 V and 0 V. (A) Aume that OSC =5V. Aboe what oltage mut CAP charge for OSC to witchto,5 V? Note that once the output witche, CAP will begin charging to,5 V. CAP C R 3 5V 5V R OSC 5V R 4 CLK Figure : the ytem clock.

3 Since = OSC R RR and we need, > for OSC to witch to 5V, we mut hae CAP = OSC R =5 R (B) Aume that OSC =,5 V. Below what oltage mut CAP charge for OSC to witch to 5 V? Note that once the output witche, CAP will begin chargingto5v. Now weneed, <, therefore CAP mut charge to CAP = OSC R =,5 R (C) Firt, aume that OSC ha jut witched to 5 V. Howmuch time elape before OSC witche to,5 V? Second, aume that OSC ha jut witched to,5 V. How much time elape before OSC witcheto5v? 5 5V R OSC 5 R 5V T T CAP = f, ( f, i )e,t= Note that the limit of CAP i 5V, not. Therefore, f =5. Thi lead to CAP =5, (5 5 )e,t=r 3C R At T, 5 =5, (5 5 )e,t =R3C R R 3

4 Sole for T get T = R 3 C ln =(R ), =(R ) Thi can be further implied to T = R 3 C ln R R By ymmetry, T = T = R 3 C ln R R (D) Determine the frequency of the ocillator in term of R,, R 3 and C. Alo, chooe alue for R,, R 3 and C o that the ocillator ocillate at or ery near 8kHz. Since ocillator frequency alone under pecie R,, R 3 and C, there i no ingle correct choice. Therefore, chooe alue for R,, R 3 and C that are eaily implemented with the component in the 6.00 lab kit. The period T = T T = R 3 C ln R R The frequency f, then, equal to T = R 3 C ln R R One poible et of alue that produce a frequency of 8 KHz i C R R 3.00 F 3 K 0 K 00 K (E) For the choice of R,, R 3 and C from Part (D), plot CAP and OSC againt time on a ingle graph oer one period of ocillation. See graph on next page. (F) Chooe a alue for R 4. Anyalue between k and 00k k hould work well; a malleralued reitor would draw unnecearily high current from the power upply while a largeralued reitor would reduce noie immunity at the input to the counter. Beyond thi, the only contraint i that the reitor be eaily implemented with the component in the 6.00 lab kit. It turn out that we need to keep the RC contant lowat CLK. Experiment how that R work well, but alue between k and 00 k do not. (G) On the graph from Part (E), plot the clock outputoltage CLK. See graph on next page. 4

5 5V OSC 4.65V CLK 5V 4.65V CAP t (u) 5V T = 6.5 u T = 6.5 u Problem : The DigitalToAnalog Conerter The circuit hown in Figure 3 i the digitaltoanalog conerter. The oltage ource DB0 through DB7 repreent the oltage upplied by the eight data bit of the digital memory, DB0 through DB7. Thee oltage will be approximately 5 V when the correponding data bit i a logical high, and approximately 0 V when the correponding data bit i a logical low. The oltage OFF, which i et by a potentiometer, i an oet oltage that i ued to center the output of the conerter around 0 V. Aume that the opamp in the conerter i ideal. (A) Determine DAC a a function of DB0 through DB7, and OFF. Hint: ue uperpoition. Set OF F = 0 and compute the current going through R 8, i, = 0, DAC, R 8 = 7X i=0 DBi R i R 8 R 0 DB0 R DB R 6 DB6 R 7 DB7 5V OFF DAC Figure 3: the digitaltoanalog conerter. 5

6 Thi gie u the portion of the output oltage contributed by the input, DAC, =, 7X i=0 R 8 R i DBi Now etting DBi =0,we get the portion of the output oltage contributed by OF F, where R, = R 0 jjr jj:::jjr 7. The total output oltage i DAC =, DAC = OF F ( R 8 R, ) DAC = DAC, DAC 7X i=0 R 8 R i DBi OF F ( R 8 R, ) (B) With OFF = 0 V, the output of the digitaltoanalog conerter hould pan the range of 0 V to,:5 V.Thu, the output of the conerter hould be gien by DAC =,:5 V 7X i=0 i 55 DBi where each data bit DBi take on the numerical alue of when high and 0 when low. In thi manner, each ucceie data bit from DB0 to DB7 i gien a oltage weighting twice that of the preceding data bit, making it poible for the conerter to output oltage from 0 V to,:5 V in tep of,:5=55 V. Gien thi, what mut be the relationhip between the alue of R 0 through R 7,andR 8? The oltage rating of the peaker i approximately.5 V. Since the lowpa lter and power amplier between the conerter and the peaker both hae unity oltage gain oer the frequency range of interet, the output range of the analogtodigital conerter mut be deigned to match the peaker rating. Thi i why the range i choentobe0vto.5v, with OFF =0. Note further that the output range of the conerter i negatie. Thi i becaue the conerter i baed upon the inerting amplier conguration. R 0 = =4 = ::: = 8R 7 Subtituting DB0=, we get,:5 55 =,R 8 R 0 5 ) R 8 R 0 = 50 (C) Theroleof OFF i to oet the output of the digitaltoanalog conerter o that it i centered around 0 V. That i, with DB0 through DB7 all low, DAC hould be.5 V, and with DB0 through DB7 all high, DAC hould be,:5 V. Gien thi, what mut be the alue of OFF? 6

7 R, = R 0 jjr jj:::jjr 7 = R 0 (jj jj jj:::jj ) 4 8 = R 0 =( 4 ::: 8) = R 0 =55 We want tohae V DAC =:5 when V DBi =0. Thi lead to :5 = OF F ( R 8 R, ) = OF F ( 55 R 8 OF F = :83V (D) Baed on the reult of Part (B), chooe alue for R 0 through R 7,andR 8. Since the reult of Part (B) under pecify R 0 through R 7, and R 8, there i no ingle correct choice. Further, ince arbitrary alued reitor are not aailable, the reult of Part (B) can not be atied exactly. Therefore, chooe alue for R 0 through R 7,andR 8 that are eaily implemented with the component in the 6.00 lab kit, and that atify the reult of Part (B) a bet a poible. The following i a et of poible alue. R0 ) Reitor ideal alue() actual alue () R 0 54K 50K R 76.8K 8K 38.4K 39K R 3 9.K 8K R 4 9.6K 0K R 5 4.8K 4.7K R 6.4K.K R 7.K.K R k 680 7

8 Problem 3: The LowPa Filter The circuit hown in Figure 4 i the lowpa filter. It i a econdorder filter, and i drien by the output of the digitaltoanalog conerter. It purpoe i to remoe the highfrequency component of the audio ignal that reult from the ampling, quantization and recontruction of that ignal. Aume that the opamp in the filter i ideal. C DAC R R C Figure 4: the lowpa filter. jωt (A) Aume that the lowpa filter operate in inuoidal teady tate with DAC R DACe and jωt = R{ e } where ṽ DAC and ṽ are complex amplitude. Find the inputoutput tranfer function H ω ( ω). ( ) of the filter where H DAC = { } Define the C RR node a V m and then write KCL at that node R R DAC m m ( ) = C d m () dt V m can be eliminated by writing KVL through the poitie opamp terminal to ground RC d m = () dt Combining Equation and and then rearranging term reult in DAC R CC d RC d = (3) dt dt Uing the aumed exponential olution form and ubtituting for the ariable produce the tranfer function DAC () H () = ()= R C C RC (4) 8

9 Subtituting for = jω H( ω)= RCCω jrcω (5) (B) Uing the reult of Part (A), find the magnitude and phae of H ( ω). ( ) = H ω φ = tan ( RCCω ) ( RCω) RC ω RCCω (6) (C) There i no bet deign for the lowpa filter to meet the need of the audio playback ytem. Howeer, with the appropriate choice of C, C, and R, the tranfer function of one good deign will take the form H ( ω ) = ( ωω ) (7) where ω i a pecified frequency. For thi deign, how that the lowfrequency and highfrequency aymptote of H ( ω) interect at ω = ω, and therefore that ω i the frequency that delineate the pa band of the lowpa amplifier. The low and highfrequency aymptote are calculated by including only the lowet and highet order ω term repectiely H H ( ω) low ( ω) high ( ωω ) (8) Thee aymptote equation are equal at ω = ω, the upper limit of the pa band for the lowpa filter. (D) What contraint mut be impoed on C, C, and R to obtain the lowpa filter tranfer function decribed in Part (C)? If the denominator of Equation 6 i multiplied out ( ) = H ω RCCω ( RCCω ) 4RC ω (9) It can be een that if C = C = C, then the magnitude become 9

10 ( ) = H ω RCω ( RCω ) = RCω (0) where ω = RC. (E) Gien that the lowpa filter i to be deigned a decribed in Part (C), ue the reult of Part (D) to chooe alue for C, C, and R o that ω π 4000 rad/. Since the reult of Part (D) under pecify C, C, and R, there i no ingle correct choice. Therefore, chooe C, C, and R o that they are eaily implemented with the component in the 6.00 lab kit. Since there are le capacitor in the kit one approach might be to pick the capacitor alue o that R = C ω () i a alue that i aailable in the kit. One poible election i C =.0µ F and R= 39. kω. (F) Gien the choice of C, C, and R from Part (E), determine ω, and plot both the logmagnitude and phae of H 5 ω π ω π rad/. ( ) againt logfrequency for 0 0 ω = ( π µ F )( k = rad /.. Ω ) () 0

11 0 0 Problem 3F Magnitude Frequency [rad/ec] 0 50 Phae Frequency [rad/ec] Problem 4: The Power Amplifier Figure 5A how the output of the lowpa filter driing the power amplifier, which in turn drie the peaker. The power amplifier i neceary becaue an opamp alone can not upply the current, and hence the power, required to drie the peaker. The power amplifier i contructed from an opamp, an nchannel MOSFET and a pchannel MOSFET. The peaker may be modeled by a reitor oer the frequency range of interet, and the MOSFET may be modeled a follow: ids = 0 for GS < Tn; n Channel MOSFET K n ids = ( ) for GS & DS GS ids = 0 for GS > Tp; p Channel MOSFET K p ids = ( ) for GS & DS GS GS Tn Tn Tn GS Tp Tp Tp Note that K n, K p, and Tn are all poitie, while Tp i negatie. For implicity, let Tn = Tp T and K = K K. n p ; ; (3)

12 5V 5V G D G D G S S OUT D FET G S S R S D OUT (A) 5V 5V (B) OUT =F( FET ) FET R S OUT (C) Figure 5: the power amplifier. (A) Conider the circuit hown in Figure 5B in which the reitor R model the peaker. Explain why OUT = 0 for FET < T. Further, explain why the nchannel MOSFET i turned on only for, and why the pchannel MOSFET i turned on only for. FET T Start by auming both MOSFET are off. Then there i no current through R from either MOSFET o OUT = 0. Since GS = G S = FET OUT = FET (4) for thi aumption, then neither MOSFET will turn on for FET < T. Thi i a elfconitent reult. Auming that OUT 0 produce an inconitent reult that one of the MOSFET i ON. For the econd part of the quetion, aume that OUT > 0 which can only be true if the current ource from the poitie upply (the nfet) i turned on. Thi can only occur if GS = FET OUT T which for OUT > 0 can only be true if FET T. Since the pfet i only turned on for GS = FET OUT T, the pfet mut be off for FET T. Conerely when OUT < 0 only the pfet could be ourcing the current, and FET T mut be true, and the n FET cannot be turned on becaue FET OUT T T. (B) Aume that the nchannel MOSFET operate in it aturation region. Find OUT a a function of FET for. Hint: ee Exercie 5.. FET T FET T

13 The equation can be copied directly from Exercie 5., Part (a), OUT = ( RK ) 4( FET T ) RK (5) (C) Oer what range of OUT i the reult of Part (B) alid? From Exercie 5(b) T FET V T (6) where V, i the poitie upply oltage. Subtituting thee limit back into Equation (5) ( RK) 4 V RK 0 OUT 0 OUT V ( RK ) 8V RK RK 0 OUT V ( VRK ) V RK (7) (D) Aume that the pchannel MOSFET operate in it aturation region. Find OUT a a function of FET for. Hint: make ue of ymmetry. FET T Uing ymmetry replace FET, OUT, and V by their negatie o that OUT = ( RK ) 4( FET T ) RK (8) (E) Oer what range of OUT i the reult of Part (D) alid? The ame ymmetry reaoning i ued 0 OUT V ( VRK ) V (9) RK (F) Combine the reult of Part (B) through (E) and plot OUT a a function of FET for R = 5Ω, Tn = Tn = V and Kn = Kp = 0. A/V. Thee alue for R, Tn, Tp, K n and K p are typical of thoe to be encountered in Lab #4. The figure below how the actie and cutoff region for the follower CMOS circuit that wa jut analyzed. 3

14 5 Problem 4F 0 5 Vout [V] Vfet [V] (G) Conider the circuit hown in Figure 5C in which the function F repreent the combined reult of Part (F). Aume that the opamp i ideal except for a finite gain A. In thi cae, how that F = OUT A ( ) OUT From Figure 5C OUT = F( ) (0) FET and F FET = ( ) OUT () From the ideal opamp model ( ) FET = A( )= A OUT () 4

15 Rearranging the term gie the reult hown in the problem tatement. (H) Let A = 000, for example. Combine the reult of Part (F) and (G), and plot OUT a a function of for 5. V. Ue reaonable engineering approximation. ( ) Since F OUT i the ame order of magnitude a OUT, diiding that term by A make it inignificant compared to the firt term o (3) OUT The plot i hown below. Note that there i a negligibly mall band around the origin where both MOSFET are off and OUT = 0..5 Problem 4H 0.5 Vout [V] Vlpf [V] Problem 5: Connecting The Block In the complete audio playback ytem the output of the digitaltoanalog conerter i connected directly to the input of the lowpa filter, and the output of the lowpa filter i connected directly to the input of the power amplifier, a hown in Figure. Thu, the filter load the conerter, and the 5

16 amplifier load the filter. Explain why thi loading could be ignored in Problem, 3 and 4. That i explain why the conerter, filter and amplifier may each be analyzed and deigned in iolation. There are a number of way to decribe thi, but notice firt that the circuit of Problem and 3 all employ an opamp at their repectie output port. One of the characteritic of the ideal opamp i that it ha zero output impedance. Thi mean that load or additional circuit connected to the output will not change the oltage at the output of the opamp. In other word the cacaded ytem cannot load down the preiou ubytem output oltage. The final circuit, in Problem 5 alo employ an opamp but trictly peaking it i the complementary MOSFET that are connected at the output to the peaker load. But the MOSFET, a long a they operate in the actie region, are alo ource (current ource in thi cae) with zero output impedance. The opamp feedback circuit in thi cae ere to automatically adjut the input oltage to the CMOS pair controlling the current ource to produce a unity gain follower at OUT. 6