Department of Physics and Astronomy

Transcription

1 Department of Physics and Astronomy University of Heidelberg Master thesis in Physics submitted by Raphael Philipp born in Heidelberg 2014

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3 Characterisation of High Voltage Monolithic Active Pixel Sensors for the Mu3e Experiment This Master thesis has been carried out by Raphael Philipp at the Physikalisches Institut Heidelberg under the supervision of Prof. Dr. André Schöning

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5 Charakterisierung von monolithischen aktiven Pixel-Sensoren in Hochspannungs- Technologie für das Mu3e-Experiment: Das Standardmodell der Teilchenphysik beschreibt die Elementarteilchen und ihre Wechselwirkungen erstaunlich gut. Jedoch entstehen Theorien jenseits des Standardmodells, da es noch viele offene Fragen gibt. Das Mu3e-Experiment sucht nach dem eptonenzahl-verletzenden Zerfall µ + e + e e +, der im Standardmodell stark unterdrückt ist. Deshalb wäre eine Beobachtung dieses Zerfalls ein klarer Hinweis auf neue Physik. Der Detektor muss für hohe Myonen-Zerfallsraten ausgelegt sein und minimale Vielfachstreuung bewirken um die geplante Sensitivität von < zu erreichen. Daher werden monolithische aktive Pixel-Sensoren in Hochspannungs-Technologie (HV- MAPS) verwendet. Dies sind neuartige dünne Silizium-Pixel-Sensoren, bei denen die Sensor- und Ausleseelektronik auf dem selben Chip sitzen. Aufgrund der angelegten Hochspannung haben sie eine schnelle adungssammlung und können gedünnt werden. In dieser Masterarbeit wurden HV-MAPS mit Photonen, β-strahlung und Elektronen bei mehreren Strahltests getestet. Das Signal-Rausch-Verhältnis wurde für verschiedene Temperaturen über Raumtemperatur ermittelt. Dabei wurden Signal-Rausch- Verhältnisse von über 21 gemessen. Die Effizienz des Mupix4-Prototyps, die aus den Strahltest-Daten berechnet wurde, ist > 99,5% und die Zeitauflösung ist mit einem Wert von 17 ns auch hervorragend. Außerdem wurden das erste Mal gedünnte Sensoren getestet und sie zeigen gute Betriebseigenschaften. Characterisation of High Voltage Monolithic Active Pixel Sensors for the Mu3e Experiment: The Standard Model of particle physics describes the elementary particles of matter and their interactions surprisingly well. However, theories beyond the Standard Model arise because there are many open questions. The Mu3e experiment searches for the lepton flavour violating decay µ + e + e e + which is highly suppressed in the Standard Model. Therefore, the observation of this decay would be a clear hint for new physics. The tracking detector has to deal with high muon decay rates and must have minimal multiple scattering in order to achieve the targeted sensitivity of < Hence, High Voltage Monolithic Active Pixel Sensors (HV-MAPS) are used. These are novel thin silicon pixel sensors where sensor and readout electronics are on the same chip. Due to the applied high voltage they have a fast charge collection and can be thinned. In this Master thesis HV-MAPS were tested with photons, β-radiation and electrons at several testbeams. The signal-to-noise ratio has been determined for different temperatures above room temperature and signal-to-noise ratios above 21 were measured. The efficiency of the MuPix4 prototype, determined from testbeam data, is > 99.5% and the timing resolution has also an excellent value of 17 ns. In addition, thinned chips have been tested for the first time and show good performance.

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7 Contents I Introduction 1 1 Introduction 3 2 Theory Standard Model of Particle Physics epton Flavour Violating Muon Decays Mu3e Experiment Current Experimental Situation SIDRUM Experiment MEG Experiment Muon Decays The Decay µ + e + e e Backgrounds Muon Beam and Target Detector Design Tracking Detector Timing Detector HV-MAPS 15 II MuPix Prototypes 17 5 MuPix Setup The Chip The Hardware Measurements Pulse Shapes Temperature Dependence Sr Source vii

8 6 MuPix Setup The Chip The Hardware Measurements Pulse Shape MuPix Setup The Chip Wire Bonding The Hardware Measurements Pulse Shapes Signal-to-oise Ratio Testbeam Campaigns March 2013 at DESY MuPix June 2013 at DESY Thick MuPix3 Chip Thinned MuPix3 Chip September 2013 at PSI MuPix MuPix MuPix October 2013 at DESY MuPix February 2014 at DESY MuPix III Discussion 61 9 Discussion and Outlook 63 IV Appendix 65 A ayouts of the MuPix Prototypes 67 B Schematics of the MuPix3 and MuPix4 PCBs 73 C Bonding Diagrams for the MuPix4 Chip 93 viii

9 D E Graphical User Interface of the Configuration and Data Readout Software 97 Mechanical Adapter for the Rotation Stage at the Telescope at DESY101 F ists 103 F.1 ist of Figures F.2 ist of Tables G Bibliography 107 ix

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11 Part I Introduction 1

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13 1 Introduction The Standard Model of particle physics describes all known particles and their interactions surprisingly well. Although the Standard Model has not been disproved yet, it cannot be the final theory because there are many open questions. The gravitation for example is not part of the Standard Model and it cannot explain the large asymmetry between matter and antimatter in the universe [Gri11]. Therefore, searches for theories beyond the Standard model are performed. The Mu3e experiment searches for the lepton flavour violating decay µ + e + e e +, which is highly suppressed in the Standard Model. The observation of this rare decay would be a clear hint for new physics beyond the Standard Model. The requirements of the detector are very high because high muon decay rates of 10 9 muons per second are necessary to achieve the target sensitivity of < in a reasonable time. The detector must have a high momentum and vertex resolution for background suppression. Therefore, thinned High Voltage Monolithic Active Pixel Sensors (HV-MAPS) are used to reduce multiple scattering. HV-MAPS are based on a charge collecting diode which is operated with high voltage and have a thin depletion zone. Therefore, the charge collection time is short and the chips can be thinned. In addition the sensor and readout electronics are on the same chip so that the material is further reduced. This leads to low multiple scattering which in turn results in a good momentum resolution of the detector. The momentum resolution at the low momenta of the decay electrons of (10-53) MeV is dominated by multiple scattering. In this Master thesis also thinned HV-MAPS prototypes are examined. 3

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15 2 Theory In the Standard Model of particle physics lepton flavour has to be conserved. However, neutral leptons, the neutrinos, can change from one flavour into another in a Standard Model extension. Therefore the search for charged lepton flavour violating processes like the decay µ + e + e e + is ongoing. This chapter introduces the Standard Model of particle physics and lepton flavour violating muon decays. 2.1 Standard Model of Particle Physics The Standard Model of particle physics is a theory that describes the elementary particles of matter and their interactions [Gri11]. There are two types of particles: six quarks and six leptons (and their antiparticles). Both the quarks and the leptons are fermions and are grouped in pairs (see figure 2.1). The first quark generation is composed of the up quark u and the down quark d, the second generation consists of the charm quark c and the strange quark s, and the third generation of the top quark t and the bottom quark b. The first lepton generation is composed of the negatively charged electron e and the neutral electron neutrino ν e, the second generation consists of the muon µ and the muon neutrino ν µ and the third generation of the tau τ and the tau neutrino ν τ. The lepton flavour numbers of the three generations are e, µ and τ. In the Standard Model the lepton flavour numbers are conserved. The gauge bosons mediate the interactions between these particles. The gluon is the force carrier of the strong force, the photon γ is the force carrier of the electromagnetic force and the W +, W and Z 0 bosons are the force carriers of the weak force. The gravitation is not part of the Standard Model up to now. The experiments CMS and ATAS at the arge Hadron Collider (HC) at CER found a scalar, neutral particle with a mass of ( ) GeV/c 2 which is most likely the Higgs boson [Hig12] which was predicted to generate the mass of the W +, W and Z 0 bosons (Higgs mechanism). 5

16 eutrino oscillations, during which one neutrino flavour is changed into another, are lepton flavour violating and have been observed [F + 98, A + 01, E + 03]. It can be incorporated into an extended Standard Model. Because of that, neutrinos must have a small but non-zero mass. The Standard Model can quite successfully describe all known particles and their interactions but there are still many unanswered questions. The Standard Model cannot explain the large asymmetry between matter and antimatter in the universe. or it can explain why there are three generations of elementary particles although all matter around us, namely the atoms, is only made of up and down quarks and electrons. Figure 2.1: Elementary particles of the Standard Model [sta14]. 2.2 epton Flavour Violating Muon Decays The lepton flavour violating decay µ + e + e e + is possible in the extended Standard Model via neutrino mixing (see figure 2.2). Due to the heavy mass of the W + (m w = 80.4 GeV/c 2 ) and the very small difference of squared masses of the neutrinos ( ( ) 10 mev), the factor m 2 2 ν m is very small and therefore this decay is heavily suppressed 2 W (BR < ). 6

17 + W γ * e - e + ν µ ν e µ + e + Figure 2.2: Feynman diagram of the lepton flavour violating decay µ + neutrino oscillations. e + e e + via If the decay µ + e + e e + is observed, this will be a clear hint for new physics beyond the Standard Model. µ + e + Z e + e - (a) µ + e + e e + mediated by a Z µ ~ e ~ µ + χ ~ 0 e + (b) µ + e + e e + with SUSY particles γ * e - e + Figure 2.3: Feynman diagrams of the decay µ + e + e e + with beyond Standard Model processes. There are many new models which allow charged lepton flavour violation by means of new, heavy particles. epton flavour violating processes could be possible by adding new particles that can couple to both the electron and the muon at tree-level (see figure 2.3a). This particle could be a new Z boson and models with extra dimensions [C05] predict such processes. In these models the lepton flavour violating decays are suppressed because of the high mass of these new particles. epton flavour violating decays at looplevel that have a higher branching ratio than the extended Standard Model decay with neutrino mixing, are possible if the neutrinos and the W boson are replaced by supersymmetric (SUSY) particles (see figure 2.3b). The superpartners of leptons are called sleptons and are bosons. Since SUSY particles have not been observed yet, they are expected to have high masses [Gri11]. Hence, their mass differences could be larger and therefore the branching ratio of the decay µ + e + e e + would be higher. 7

18 To be able to compare the new physics mass scale between the decays µ + e + e e + and µ + e + γ a simplified agrangian function can be chosen [dg09]: F V = m µ (κ + 1)Λ µ Rσ µν κ e 2 F µν + (κ + 1)Λ (µ γ µ e 2 )(e γ µ e ) (2.1) Λ is the common mass scale and κ is the amplitude ratio between the left and the right term. The left term describes dipole coupling (loop-level decays), the right term describes a contact interaction with left-left vector coupling (tree-level decays). oop-level decays dominate at low κ and the tree-level decays dominate at high κ. In figure 2.4 it can be seen that the Mu3e experiment has to be two orders of magnitude better in sensitivity than the MEG experiment to be able to go beyond the accessible mass scale. Figure 2.4: The expected branching ratios and the current experimental limits for the experiments SIDRUM, MEG and Mu3e [B + 12b]. 8

19 3 Mu3e Experiment The Mu3e experiment searches for the lepton flavour violating, and thus in the Standard Model forbidden, decay µ + e + e e + with a targeted sensitivity of < [B + 12b], which is four orders of magnitude better than the previous SIDRUM experiment [B + 88]. In order to reach such a high sensitivity in a reasonable time, high muon decay rates of 10 9 muons per second are needed. This leads to several requirements for the detector. 3.1 Current Experimental Situation SIDRUM Experiment The SIDRUM experiment was running from 1983 to 1986 at the Paul Scherrer Institute (PSI) in Switzerland and searched for the decay µ + e + e e +. Since no signal event for this decay was found, they set the limit on the branching ratio to BR(µ + e + e e + ) < at 90 % C [B + 88]. The detector consists of five concentric multiwire proportional chambers (MWPC) and a cylindrical array of 64 scintillation counters arranged in a homogeneous magnetic field of 0.33 T MEG Experiment The MEG experiment is running since 2008 at PSI and searches for the decay µ + e + γ. Since no signal was found up to now, they set the limit of the branching ratio to BR(µ + e + γ) < at 90 % C [A + 13]. The detector consists of drift chambers, timing counters inside a gradient magnetic field and a photon detector. The MEG experiment will analyse more data taken in te last two years and are currently upgrading the detector in order to achieve an even better sensitivity of [BCC + 13]. 9

20 3.2 Muon Decays The muon has a mass of MeV/c 2 and a mean lifetime of µs [B + 12a]. Due to its low mass and charge conservation, the muon can only decay into electrons, neutrinos and photons. The muon most likely decays via the lepton flavour conserving decay µ e ν µ ν e with a branching ratio of almost 100 % [B + 12a]. The muon also decays into µ e γν µ ν e with a branching ratio of and µ e e + e ν µ ν e with a branching ratio of [B + 12a]. Because of the very low rate of the signal decay µ + e + e e +, this background has to be suppressed The Decay µ + e + e e + All three decay particles of the µ + e + e e + decay come from the same vertex and are coincident in time. The total energy of the decay particles have to be equal to the mass of the antimuon: 3 E tot = E i = m µ c 2 (3.1) i=1 So, the energy of the positrons and the electron can be 53 MeV at most, which is equivalent to half of the muon mass. If the antimuon decays after it has been stopped, the vector sum of the momenta of the decay particles vanishes: p tot = 3 p i = 0 (3.2) These facts can be used to distinguish the signal decay from the background. i= Backgrounds There are two types of background: the internal conversion background and the accidental background. Internal Conversion Background The Standard Model decay with internal conversion µ + e + e e + ν e ν µ (BR = [B + 12a]) is the most serious background for the Mu3e experiment because the decay particles are coincident in time and originate from the same vertex. The Feynman diagram is shown in figure 3.1. However, the neutrinos cannot be detected in the detector and this 10

21 energy loss can be used to reduce this background. Therefore, the Mu3e detector needs a very good energy and momentum resolution. In order for the Mu3e experiment to reach a sensitivity of 10 16, a momentum resolution of the sum of the two positrons and the electron momenta of below 1 MeV is needed (see figure 3.2). Figure 3.1: Feynman diagram of the internal conversion decay µ + e + e e + ν e ν µ. Accidental Background A coincidence of particles from different processes could mimic the signal event. Positrons of two Michel decays and an electron from another decay superimposed can look like a signal decay (see figure 3.3). This electron can for example come from Bhabha scattering, a muon decay with internal conversion, photon conversion or could be a positron that is identified as an electron. Photon conversions can be reduced by minimising the detector material. Since the accidental background is neither coincident in time nor has one common vertex nor meet energy and momentum conservation it can be suppressed by a very good vertex, momentum and time resolution of the detector. The detector must in any case have as little material as possible to reduce multiple scattering. 3.3 Muon Beam and Target Since a high antimuon rate is required to reach the aimed sensitivity, the Mu3e experiment will be operated at PSI in Switzerland which runs the world s most intense proton beam with up to 2.4 ma of 590 MeV/c protons [PSI14]. For a first low intensity phase, the existing πe5 beamline will be used. This beamline can supply a rate of up to

22 Branching Ratio μ3e m μ - E (MeV) 6 tot Figure 3.2: Effective branching ratio for the decay µ + e + e e + ν e ν µ as a function of the energy of the neutrinos [D09]. e + e - Figure 3.3: Accidental background from two Michel decays and an electron, the dashed lines represent the neutrinos. e + 12

23 muons/s [B + 12b]. In order to reach the planned sensitivity of in reasonable time a muon rate of muons/s is required. Therefore a new, more intense beamline has to be built. The Swiss Spallation eutron Source (SIQ) at PSI generates a large amount of antimuons and a secondary beamline exploiting these muons is under study [B + 12b]. In the Mu3e detector, the muon beam is stopped by a hollow double cone target, which is made of aluminium (see figure 3.4). The front part of the target is 30 µm thick and the back part is 80 µm thick. The target has a total length of 100 mm and a diameter of 20 mm. 3.4 Detector Design The detector design is shown in figure 3.4. The final detector will have an additional recurl station on both sides, so that the whole detector will have a length of about 2 m Tracking Detector The detector is placed in a 1 T magnetic field so that the momenta of the electrons and positrons can be measured by the curvature of their tracks. The trajectories of the particles are measured by pairs of inner and outer pixel layers. The high vertex resolution is achieved by the inner pixel layers which is very close to the target where the antimuons are stopped. The good momentum resolution is obtained by measuring the bending of recurling tracks in the recurl stations and by reducing the detector material and hence multiple scattering. The pixels of these sensors will have a size of (80 80) µm 2 and therefore, the whole detector will have about 280 million pixels. The pixel sensors can be thinned down to 50 µm (see chapter 4) so that the radiation length of one layer is X/X %. In addition the support structure and the readout cable will be made of 25 µm thin apton R foil onto which the pixel sensors will be glued and wire bonded. Furthermore, the detector will be cooled with gaseous helium. This reduces the deflection of the positrons and electrons traversing the detector material (multiple scattering) which is limiting the momentum resolution. The RMS of the scattering angle Θ RMS = ( ( )) 13.6 MeV x x ln βcp X 0 X 0 (3.3) (see [B + 12a]) shows that the multiple scattering is larger for particles with low momentum p which is the case for the Mu3e experiment. β/c is the velocity of the positrons and the 13

24 electrons. Multiple scattering can be reduced by reducing the traversed material x and by using materials with high radiation lengths X 0. Recurl pixel layers Scintillator tiles Inner pixel layers μ Beam Target Scintillating fibres Outer pixel layers Figure 3.4: Schematic side view of the Mu3e detector with the first recurl station and overlayed transverse view. (a) Most inner pixel layer prototype of the detector (b) Prototype of a segment of an outer pixel layer Figure 3.5: Prototypes of the Mu3e pixel detector made of apton R ; instead of pixel sensors 50 µm glass plates are used Timing Detector The good timing resolution is accomplished by scintillating fibres and scintillating tile detectors. The fibres will be placed inside the central outer double pixel layers and the tiles will be placed at the recurl stations outside the active detector volume close to the beam pipe. The tiles can be bigger than the fibres because multiple scattering is no problem there (see figure 3.4). The scintillating fibres are expected to have a time resolution of less than 1 ns and the scintillating tiles are expected to have a time resolution of ( ) ns. 14

25 4 HV-MAPS The Mu3e experiment uses High Voltage Monolithic Active Pixel Sensors (HV-MAPS) for the tracking detector. These sensors were developed by Ivan Perić [Per12a, PF11, PT10, Per07]. These special silicon sensors have the advantages that they are fast and have only little material. Monolithic Active Pixel Sensors (MAPS) have sensor and readout electronics on the same chip and therefore a small material budget because no extra readout chip and no extra bump bonds are needed. HV-MAPS can be implemented in an inexpensive commercial high-voltage CMOS process which is highly available. Every pixel is implemented as a smart diode, that means that the pixel electronics, e. g. the charge sensitive amplifier (CSA), is placed inside a high voltage n-well. These n-wells are on a p-doped substrate (see figure 4.1). This n-well to p-substrate diode is operated in reverse direction such that the n-well is the charge collecting electrode. Incoming particles ionise the atoms in the depletion zone. In contrast to MAPS, HV-MAPS collect this charge via drift because of high bias voltages of over 50 V. The time of the charge collection is then reduced to less than 1 ns [Aug12] and charge recombination is strongly reduced. Since the depletion zone is about 9 µm [Per07] the HV-MAPS can be thinned down to 50 µm. Thus the material in the detector can further be reduced to minimise multiple scattering. -well E field P-substrate Particle Figure 4.1: Sketch of four HV-MAPS pixels [Per07]. 15

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27 Part II MuPix Prototypes 17

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29 5 MuPix2 The MuPix2 chip is the second HV-MAPS prototype for the Mu3e experiment designed by Ivan Perić (see [Per12a]). The MuPix2 chip has already been intensely characterised in [Aug12] and [Per12b]. Before measurements for the MuPix3 and the newest prototype MuPix4 were done, the MuPix2 chip was tested in this thesis. Also a thinned MuPix2 chip was tested (see section 8.3). 5.1 Setup The Chip The MuPix2 chip has a size of ( ) mm 2, its pixel matrix consists of pixels and each pixel has a size of (39 30) µm 2. Therefore the chip has an active area of 1.77 mm 2. In table 5.1 all MuPix prototypes but the MuPix1 are compared. Incoming particles ionise the atoms in the depletion zone and this charge is collected by the pixels. The sensor diode is connected to the charge sensitive amplifier (CSA) via a capacitor because the amount of charge is very small (see figure 5.1). This sensor signal can be imitated by the injection capacitor for test purposes. Every pixel is connected to this injection. There is a digital processing unit (DPU) for every pixel. The comparator in the DPU compares the pixel signal with an adjustable threshold and generates an output signal that is as long as the pixel signal is above the threshold (time over threshold, ToT). Every pixel has in addition to that global threshold a DAC (digital to analogue converter) that adds a voltage to this threshold to even out pixel variations. This DAC is called TDAC. The MuPix2 chip can be read out in the hit-flag mode or in the ToT mode, i. e. either the whole pixel matrix of the chip can be read out or the output signal of a selected single pixel can be analysed. The hit-flag mode gives only the information whether a pixel was hit and the signal was above the threshold. Every pixel is read out whether it registered a hit or not. The ToT mode gives in addition the time how long the signal of this pixel was above the threshold (time over threshold, ToT). While the chip is read out in the hit- 19

30 flag mode by the FPGA board, simultaneously the ToT signal of one single pixel can be measured via a probe on an oscilloscope. Pixel Periphery B Sensor CSA source follower Readout Injection tune DAC Comparator threshold integrate charge amplification drive high C of signal line AC coupling via CR filter digital output (ToT) set individual threshold Figure 5.1: Electronics of all MuPix prototypes inside each pixel and on the chip periphery. The voltages that can be changed are marked in green. [Per12b] Figure 5.2: Picture of a MuPix2 chip The Hardware The test setup consists of a PCB with a socket for the chip and a FPGA board (Uxibo, see [uxi14]) that is connected via a ribbon cable to the PCB and via a USB cable to a computer. The chip is glued and wire bonded on a chip carrier that can be placed in the socket of the PCB (see figure 5.3). The FPGA is controlled via a C++ programme and can set the voltage of the threshold and the injection generated on the PCB. In addition 20

31 chip pixels pixel size chip size active area ToT signal MuPix (39 30) µm 2 ( ) mm mm 2 positive MuPix (92 80) µm 2 (4 5) mm mm 2 positive MuPix (92 80) µm 2 (4 5) mm mm 2 negative MuPix (103 80) µm 2 (4.4 5) mm mm 2 negative Table 5.1: Comparison of the MuPix prototypes, note that the MuPix6 prototype is the fifth HV-MAPS prototype for the Mu3e experiment. the readout sequence can be started. The readout mode is chosen by switching a jumper at the test PCB. Figure 5.3: Test setup of the MuPix2 chip: the FPGA board (left) and the PCB where the chip sits in (right). 5.2 Measurements The following measurements were done with an infrared laser diode 1 with a wavelength of 850 nm and a 90 Sr source. 1 For test purposes: The light of this diode is invisible but it can be seen through a camera of a mobile phone. 21

32 5.2.1 Pulse Shapes The pulse shapes for different settings can be compared in order to study the influence of these parameters on the performance of the chip. Since the signal of a pixel is compared to a threshold before this signal is output (ToT signal) and digitised, the pulse shape cannot be measured directly. However, the pulse shape can be reconstructed by scanning the pulse with increasing thresholds as shown in figure 5.5. The chip is lit with a ED that gets its signal from a pulse generator. Both the signal of the pulse generator and the ToT signal from a pixel are connected to an oscilloscope and the time difference between the rising edge of the ED signal and the rising edge of the ToT signal (latency) as well as the width of the ToT signal is determined. This ToT signal is shown in figure 5.4. Hence, for every threshold two measuring points are obtained. With increasing threshold the latency becomes longer and the ToT becomes shorter. Figure 5.4: ToT signal of a pixel of the MuPix2 chip measured via a probe on an oscilloscope. The pulse of an edge pixel is much higher than the pulse shape of a centre pixel (see figure 5.6). The pixels at the corner and at the edge of the chip collect more charge than a pixel at the centre of the chip, because at the edges there are less rival pixels and thus the charge can be collected from a larger volume (see figure 5.7). But this is only true if the chip is lit by an intense light source like a ED. If the chip is hit by particles like electrons with a low rate this effect is the other way round (see section 8.3). 22

33 Signal Threshold atency ToT Time Figure 5.5: Pulse shape measurement. 1,15 1,10 Threshold [V] 1,05 1,00 0,95 0,90 0, Time [µs] Figure 5.6: Pulse shapes of the MuPix2 chip for a centre pixel (blue) and a corner pixel (red). 23

34 light light pixel pixel Figure 5.7: The ToT of a corner pixel is longer and the latency is shorter than for a centre pixel if irradiated with light due to a larger amount of charge collection. chip Temperature Dependence The pulse shapes at different temperatures can be compared as shown in figure 5.8. The pulse at a temperature of 60 C is much smaller than the pulse at 30 C. The ToT at the lowest measured threshold of 0.85 V decreased from 5.4 µs to 2.3 µs and the latency increased from 180 ns to 310 ns. This temperature effect has been corrected for the subsequent prototypes. A temperature of 60 C was chosen because this value is expected as maximum temperature for the Mu3e experiment [Zim12] Sr Source Comparison of pulse shapes of different Mupix2 chips can lead to the wrong conclusion that some chips are much more sensitive / efficient than others. Since the pulse shapes of only a few pixels were measured, variations could also be due to pixel effects. Therefore, two different chips were irradiated with a 90 Sr source and the chips were read out in the hit-flag mode, i. e. the whole pixel matrix of the chips was read out. For different thresholds all hits of 1000 readout frames were counted, where one frame was 5 µs long. The two tested chips have almost the same efficiency. The result can be seen in figure 5.9. The differences are of the order of 10% but increase with lower thresholds. The MuPix2 chip has far too long shaping times for the Mu3e experiment which can be seen in the long ToT of several µs which is also the dead-time. In addition this chip is 24

35 1,05 1,00 Threshold [V] 0,95 0,90 0, Time [µs] Figure 5.8: Pulse shapes of the MuPix2 chip at 30 C (blue) and 60 C (red) at a high voltage of -70 V Hits / 1000 Frames ,8 0,9 1,0 1,1 1,2 1,3 Threshold [V] Figure 5.9: Hits of a 90 Sr source accumulated for 1000 frames (5 µs / frame) at different thresholds for two different MuPix2 chips. 25

36 very sensitive to temperature effects. However, the prototypes MuPix3 and MuPix4 that are discussed in the following chapters show better properties. The chip to chip variations of the MuPix2 chip seems to be very small which is important for the Mu3e experiment because the tracking detector will consist of 4860 chips [B + 12b]. 26

37 6 MuPix3 The MuPix3 is the third MuPix prototype developed by Ivan Perić. It is supposed to have a better timing than the MuPix2, because the shaping times, and therefore the ToT, are too long for the Mu3e experiment. But due to an issue with the pixel enabling procedure, which should allow to enable arbitrary pixel patterns, this could not be tested. The MuPix3 chip has, compared to the MuPix2, a zero suppressed readout. In this thesis also a thinned MuPix3 chip was tested during two testbeams (see section 8.2 and section 8.3). 6.1 Setup The Chip The MuPix3 chip has a size of (4 5) mm 2, its pixel matrix consists of pixels and each pixel has a size of (92 80) µm 2. Therefore the chip has an active area of 9.42 mm 2. In figure 6.1 a size comparison between the MuPix2 and the MuPix3 chip is shown. An arbitrary set of pixels can be enabled so that only these pixels can be read out both in the hit-flag mode and in the ToT mode. The ToT mode is different to the MuPix2 chip: ot only one single pixel can be analysed but an arbitrary set of pixels can be selected. Hence, not the output signal of one single pixel but the output of a logic OR of all enabled pixel signals is provided. However, enabling the pixels does not work properly, because by mistake in the design the RAM cells on the chip cannot store the information properly which pixel was selected. After switching on the setup pixels are enabled randomly. Pixels can be disabled without any problems but not enabled again, for enabling, a power cycle is required. Because of that issue, the MuPix3 prototype was not tested as intensely as the other prototypes. The MuPix3 chip can also be read out in the hit-flag mode. For this prototype, only the pixels that registered a hit are read out in the hit-flag mode (zero suppressed readout). The pixels are organised in columns and rows. To optimise the space on the chip, every pixel column is divided into two readout columns as shown in figure 6.2. The pixel address scheme reflects the location of the corresponding readout cells. 27

38 Figure 6.1: Picture of a MuPix3 (left) and a MuPix2 (right) chip. row 5 column 0 column 1 row 4 pixels row 3 row 2 row 1 row 0 readout cells Figure 6.2: Schematic of the readout cells of the MuPix3 and MuPix4. 28

39 6.1.2 The Hardware The setup consists of a MuPix PCB, designed by Dirk Wiedner, where the chip sits in a socket (see figure 6.3) and the Stratix IV GX FPGA Development it from Altera R (see [str14]) that is connected via two ribbon cables (slow control and readout) to the MuPix PCB. The schematic of this PCB can be seen in appendix B. The FPGA is mounted on a PCIe card sitting inside the readout PC. The ToT signal and the signals to set the PCB DACs for the threshold and the injection, for example, are on the slow control cable. The signals that are necessary for reading out the chip in the hit-flag mode are on the readout cable. The MuPix3 PCB has two injection DACs because for the MuPix3 there are two different injection signals. Injection 1 is connected to the first row, which is the lowest row, and to the second row and injection 2 is connected to the third and fourth row and so on, as can be seen in figure 7.1. The jumper J508 sitting between the readout cable and the chip socket has to be set at the position that is farther from the socket, otherwise no ToT signal can be seen. The ToT signal can be tapped at the EMO R connector marked with HB. The same way the injection 1 and 2 signals can be tapped at the connector marked with Injection1 and Injection Measurements Pulse Shape The pulse shape was measured with a threshold scan as described for the MuPix2 chip. Since no single pixel can be enabled separately, the pulse shape of all randomly enabled pixels is measured and that leads to big variations of the latency and the ToT (see figure 6.4). Therefore information which can be obtained from the pulse shapes of the MuPix3 chip is difficult to interpret. There was no useful result obtained for the MuPix3 chip at the tests in the laboratory because of the pixel enabling issue. 29

40 (a) Picture of the FPGA board inside the readout PC slow control readout 5V high voltage (b) Picture of the MuPix3 test PCB Figure 6.3: Figure 6.3a shows the FPGA board sitting inside the readout PC. The left ribbon cable has to be connected to the readout connector and the right cable has to be connected to the slow control connector of the MuPix3 PCB as shown in figure 6.3b. 30

41 Figure 6.4: Pulse shape of all enabled pixels of the MuPix3 chip [Fö14]. 31

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43 7 MuPix4 7.1 Setup The Chip The MuPix4 chip has a size of (4 5) mm 2, its pixel matrix consists of pixels and each pixel has a size of (92 80) µm 2. Therefore the chip has an active area of 9.42 mm 2. See also table 5.1. The MuPix4 prototype can be read out in the zero suppressed hit-flag mode and in the ToT mode, too. The readout cells are connected to the pixels the same way as in the MuPix3 chip (see figure 6.2). The readout of this prototype is similar to that of the MuPix2 chip: Pixels cannot be disabled for the hit-flag mode, and the ToT signal of a selected single pixel can be analysed. However, the readout in the hit-flag mode is zero suppressed as with the MuPix3. The chip has two input pads for two different injection signals like the MuPix3 chip. However, all rows to which the injection 1 is connected provide the wrong row address zero, so that every hit is shown in the lowest two rows by design mistake (see figure 7.1) Wire Bonding The MuPix4 chip has pads to input and output the signals. There are pads to supply the chip with power and HV, furthermore there are pads that are connected to the ground potential. Furthermore, there are pads to set the internal currents and voltages and to enable a pixel for the ToT mode. The voltage for the baseline, the threshold and the injection pulses are input, too. If the readout sequence is started by applying the digital readout signals on the readout chip pads, the addresses of the hit pixels are applied at the twelve bit lines, six for the column and the row address each. The chip has no integrated counter so that an external clock has to feed the timestamps via eight bit lines into the chip. The chip then applies together with the pixel addresses the value of the timestamps when the hit occurred. The bonding diagram can be seen in appendix C. 33

44 (a) injection 1 (b) injection 2 Figure 7.1: Readout in the hit-flag mode of the two injections of the MuPix4 chip: 7.1a shows the readout of injection 1 and 7.1b shows the readout of injection 2. MuPix2 and MuPix3 chips could be wire bonded without problems. But with the MuPix4 there was an issue in the beginning: The first chips were wire bonded from the chip carrier to the chip, which caused short circuits between some pins and the substrate. The concerned bonding wires came too flat to the chip, so that they touched the scribe line (see figure 7.2a), which is connected to the substrate. In our case the substrate is at the potential of the HV. By pulling the bonding wires upwards, with a special needle, the short circuits could only be removed temporarily. However, the problem reappeared after some time. It seemed, that the HV bent the bonding wires back towards the scribe line. The final solution was to bond from the chip to the chip carrier, because then the distance between the bonding wires and the scribe line was larger (see figure 7.2b) The Hardware The hardware is the same as for the MuPix3 chip. Both the pixel addresses in the hitflag mode and the ToT signal of one pixel are sent to the FPGA board. The tune DACs (TDACs) can only be set if the jumper J508 is at the position that is closer to the chip socket. In the beginning a large digital crosstalk was discovered of the readout signals on the 34

45 bonding wire bonding wire scribe line carrier pad chip pad (a) bonding from carrier to chip scribe line chip pad carrier pad (b) bonding from chip to carrier Figure 7.2: Drawing of the MuPix4 bonding problem: Figure 7.2a shows the bonding procedure that caused the short circuits between random signals and the substrate by touching the scribe line and figure 7.2b shows the solution of this problem. Figure 7.3: MuPix4 chip glued and directly wire bonded on a thinned PCB. 35

46 ToT signal, so that the readout in the hit-flag mode produced more and more hits at thresholds below 1.3 V. Under this condition no signals of a 90 Sr or 55 Fe source or of the injection pulses could be seen, only the signal of a laser diode could be detected. After a first step of debugging, where high-frequency parts of some signals were filtered by soldering capacitors directly at the pins of the chip socket between signals and ground, this crosstalk was only present at thresholds below 0.87 V. Some of these concerned signals were for example threshold, injections and baseline. The next step was to connect more power and ground pins of the MuPix4 chip via wire bonds to the chip carrier and hence to the PCB. That reduced the crosstalk below a threshold of 0.85 V. Connecting the analogue and digital ground to each other reduced the crosstalk further below a threshold of 0.82 V. In the first step (filtering the signals) the two grounds were also connected, so that it can be assumed that the connection of the analogue and digital ground leads to the largest improvement. 7.2 Measurements Pulse Shapes The pulse shapes are not directly measured by using an oscilloscope because the used FPGA firmware written by iklaus Berger has the option to make histograms of the ToT signal automatically, i. e. it counts how often each ToT was sampled with a binning of 20 ns which is the period of a 50 MHz cycle. This FPGA driven measurements have the advantages that the data can be better analysed and it is possible to do also large scans without doing every step by hand. Because the FPGA cannot show how the ToT signal looks like, the ToT signal taken with the oscilloscope is shown in figure 7.4. In addition the FPGA can trigger a pulse generator to which the ED is connected to obtain the latency. This information is stored in a text file and the pulse shape is obtained by means of a python programme. The ToT is about 1000 ns long at low thresholds which is much shorter than the ToT of the MuPix2 chip which was of the order of several µs [Per12b]. The pulse shapes for different temperatures (see figure 7.5) show that the temperature effect is very small for the MuPix Signal-to-oise Ratio A large signal-to-noise ratio ensures that at a well chosen threshold the signal efficiency is high while the noise is very low. 36

47 Figure 7.4: ToT signal of a centre pixel of the MuPix4 chip. Time [ns] Figure 7.5: Pulse shapes of the MuPix4 chip at 30 C (blue) and 60 C (red). 37

48 The signal-to-noise ratio (SR) was measured in two ways: Time over Threshold Mode The ToT mode was used to measure the noise of the baseline. The threshold was set above the baseline and then decreased below the baseline in steps. If there was no noise at all, the ToT signal would be always high 1 when the threshold is above the baseline and it would be always low 1 when the threshold is below the baseline. But noise leads to fluctuations (baseline, signal input, threshold) so that even if the threshold is slightly above the baseline there are noise hits seen. The FPGA generates a ToT histogram for each threshold for a fixed time. While the threshold decreases, the ToT signal becomes longer and longer until it is always low. Then the FPGA cannot detect the ToT signal anymore because the rising edge is missing. Then the ratio of the total ToT of a histogram to the generation time for this histogram is plotted against the threshold. From the obtained S-curve the noise can be determined by fitting an error function to it. The following function was used: f(x) = A erf ( ) 1 (x x c ) + c (7.1) 2 σ The width σ of this error function is a measure of the noise and the mean value x c is the value of the baseline (see figure 7.6). c is the vertical displacement of the function. For thresholds below 780 mv the ratio of the total ToT to the measuring time decreases again. This is due to the fact, that the FPGA cannot detect the ToT anymore, because it is always low and the rising edge is missing. The value of the baseline at a temperature of 24 C and at a HV of -70 V is 778 mv and the noise around the baseline is 2 mv. At a temperature of 70 C the baseline is slightly higher (780 mv) but the noise stays the same. Since the error function fit in figure 7.6 differs from the measured curve, the noise could be larger and thus the SR could be smaller. ot only the noise but also the signal must be measured in order to calculate the SR. Hence, the S-curve was measured again with an injection signal calibrated to the signal of a 55 Fe source. For every threshold 100 injection pulses are generated and the hits that were registered by a single pixel were counted by counting the entries of the ToT histogram of the FPGA. The ratio of registered hits to generated injections is plotted against the threshold (see figure 7.7). There are some points at thresholds below 800 mv 1 High means that there is no signal and low means that there is a signal because the signal of the ToT is inverted for the MiPix4 (see figure 7.4). 38

49 T o Tt o t / m e a s u r e t i m e T h r e s h o l d [ V ] Figure 7.6: S-curve of the baseline with error function fit at a temperature of 24 C and at a high voltage of -70 V. with a ratio of more than 100% because of noise. The mean value x c of the error function fit is 827 mv at -1 V and 852 mv at -70 V. The width σ of the error function fit is 6 mv at -1 V and 5 mv at -70 V. The width σ of this error function fit is not only due to the noise of the chip but also due to the noise and fluctuations of the injection signal. Hence, for calculating the SR of this signal not the width of figure 7.7 but the width of figure 7.6 is used for the value of the intrinsic noise. The SR is calculated by dividing the difference of the mean value x c and the baseline by the noise σ: SR = signal baseline noise (7.2) The values of the SR for two different temperatures and HV is shown in table 7.1. As expected, the SR is best for a high voltage of -70 V and at room temperature and it is worst for a very low high voltage of -1 V and at 70 C. Even at high temperatures of 70 C a good signal-to-noise ratio of SR = 31.5 (at HV = -70 V) can be obtained. Since the detector will operate at temperatures of about 40 C, a SR between 31.5 and 37.0 is expected. The MuPix2 chip has a similar SR between 21.5 and 35.7 (both values for room temperature, see [Per12b]). 39

50 Temperature / HV -1 V -70 V 24 C C Table 7.1: Signal-to-noise ratios for the MuPix4 chip at 24 C and 70 C and high voltages of -1 V and -70 V Ratio [%] Ratio [%] Threshold [V] (a) HV: -1 V Threshold [V] (b) HV: -70 V Figure 7.7: S-curves of the injection for the MuPix4 chip in the ToT mode at (a) -1 V and (b) -70 V at 70 C. 40

51 Hit-Flag Mode With the hit-flag mode, both the S-curve of one single pixel and the S-curve of the whole pixel matrix can be measured. Again, like in the ToT mode, 100 injection pulses are generated and the registered hits are counted. For the whole matrix 640 hits are expected per injection pulse because every injection reaches half of the chip (= ). Figure 7.8a shows the S-curve of one single pixel and figure 7.8b shows the S-curve of the whole pixel matrix with the highest possible injection pulse of 1.8 V. The mean values x c of the fitted error functions are 963 mv for one pixel and 985 mv for the whole matrix, the widths σ are 9 mv for one pixel and 32 mv for the whole matrix. The width for the whole pixel matrix is larger because of pixel to pixel variations. Every single pixel can be tuned in threshold, to obtain a more uniform response. o SR could be obtained because the readout created hits at thresholds below 820 mv because of the digital crosstalk; the baseline is at 778 mv Ratio [%] Ratio [%] Threshold [V] (a) one single pixel Threshold [V] (b) whole pixel matrix Figure 7.8: S-curves of the injection for the MuPix4 chip in the hit-flag mode for (a) one single pixel and (b) for the whole pixel matrix. The MuPix4 chip has much shorter shaping times and thus a shorter ToT (about 1 µs) as the MuPix2 chip (several µs). That means that the dead-time is also short. Furthermore, the temperature effect is very small compared to the MuPix2 chip. The SR of the MuPix4 chip is even at high temperatures of 70 C above

52

53 8 Testbeam Campaigns In the context of this master thesis five testbeam measurements were executed: four at the Deutsches Elektronen-Synchrotron (DESY) in Hamburg (Germany) and one at the Paul Scherrer Institute (PSI) in Villigen (Switzerland). 8.1 March 2013 at DESY The electrons or positrons in the DESY II synchrotron generate a beam of bremsstrahlung photons at a carbon fibre inside the synchrotron. These photons are then converted into electron / positron pairs at a metal plate. A dipole magnet is then used to separate the electrons and the positrons horizontally. The electron beam is extracted through a collimator to the testbeam area (see figure 8.1). The magnet current can be changed to control the energy of the electrons. The energy of the electrons can be varied between 1 GeV and 6 GeV, the maximum beam rate is obtained at approximately 3 GeV [B + 07]. All testbeam measurements at DESY were operated at the testbeam line T22. During this testbeam the MuPix2 chip was tested. e+/e Converter Fiber γ e+ e Magnet e+ Collimator e DESY II Spill Counter Figure 8.1: Schematic layout of a testbeam at DESY [DES14]. For the measurements the EUDET telescope [Rub12] was used. The main part of this telescope are six MIMOSA26 chips. The integration time of these chips is 115 µs. The 43

54 MIMOSA26 chips are read out in a rolling shutter mode. When a trigger signal is sent, the current frame is finished and one further frame is read out. This creates an integration time of the telescope of (2 115) µs. The telescope with the MuPix2 chip in the device under test (DUT) position can be seen in figure 8.2. In order to be able to mount the MuPix PCBs to the rotation stage of the telescope an adapter was made (see appendix E). Figure 8.2: Picture of the EUDET telescope ACOITE at DESY with the MuPix2 PCB mounted on the rotation stage MuPix2 The MuPix2 chip was operated in the device under test (DUT) position such that its efficiency could be determined from reconstructing the tracks. Therefore the MuPix2 chip was operated only in the hit-flag mode. The MuPix2 took data for only 1 µs after the trigger signal, much shorter than the integration time of the EUDET telescope, so that only a few hits of tracks were stored, which were also registered by the telescope. Furthermore, it is not known at which time during the rolling shutter readout of the MIMOSA26 chips, the trigger signal was sent. Because of this timing problem, no efficiency could be determined. 44

55 8.2 June 2013 at DESY During this testbeam a thick ( 600 µm) and a thinned ( 90 µm) MuPix3 chip were tested in the DUT position. The integration time of the MuPix3 chip was the whole time between two trigger signals to ensure that all hits of tracks were stored, which were also registered by the telescope. However, no efficiency was determined because of the pixel enabling issue. The chip was not only operated in the hit-flag mode but also in the ToT mode to measure pulse lengths Thick MuPix3 Chip From the ToT histograms the mean of the ToT distribution of all enabled pixels was obtained by fitting a Gaussian function to the data. Since it is not known which pixels were enabled, only estimations can be made. The ToT seems to decrease slightly with increasing high voltage (see figure 8.3), but it is expected to be the other way round, because more and more charge should be collected by the pixel electrodes with rising high voltage (see [Per12b]). This unexpected but not pronounced behaviour could be explained by the fact, that after every power cycle of the MuPix3 chip another set of random pixels is enabled. Figure 8.4 shows an almost linear decrease of the ToT with increasing threshold as expected Thinned MuPix3 Chip During this testbeam also a thinned MuPix3 chip was tested. A ToT histogram for a threshold of 0.83 V and a high voltage of -60 V can be seen in figure 8.5a. The peak 1 at low ToT could be due to a set of a few pixels that are less efficient because this peak only occurs at low thresholds below or equal to 0.83 V (see figure 8.6). The ToT is almost constant at high voltages between -60,V and -90 V at a threshold of 0.83 V (see figure 8.5b). The ToT is slightly longer for the thinned than for the thick chip. This could be explained by the fact that the electric field is inversely proportional to the distance d between the n-well and the p-substrate of the pixels (E = u/d). Because at strong electric fields the electrons generated by an ionising particle can ionise further atoms in the depletion layer. But it could also be a pixel or chip variation. For the thinned chip the ToT also decreases linearly with increasing threshold (see figure 8.6). Unfortunately the chips cannot be tested before and after thinning because they have to be glued and wire bonded to the chip carrier for testing and this procedure can only be done once per chip. 45

56 ToT [µs] HV [V] Figure 8.3: HV dependence of the ToT of the thick MuPix3 chip at a threshold of 0.83 V and at a beam energy of 3 GeV ToT [µs] ,82 0,83 0,84 0,85 0,86 0,87 0,88 0,89 0,90 0,91 Threshold [V] Figure 8.4: Threshold dependence of the ToT of the thick MuPix3 chip at a high voltage of -70 V and at a beam energy of 3 GeV. 46

57 40000 peak peak 2 Counts peak 2 ToT [µs] ToT [µs] (a) ToT histogram 1 0 peak HV [V] (b) HV dependence of ToT Figure 8.5: Figure 8.5a shows the ToT histogram of the thinned MuPix3 chip at a threshold of 0.83 V, at a high voltage of -60 V and at a beam energy of 3 GeV. Figure 8.5b shows the HV dependence of the ToT of the thinned MuPix3 chip at a threshold of 0.83 V and at a beam energy of 3 GeV peak 2 7 ToT [µs] peak 1 0 0,82 0,83 0,84 0,85 0,86 0,87 0,88 0,89 0,90 0,91 Threshold [V] Figure 8.6: Threshold dependence of the ToT of the thinned MuPix3 chip at a high voltage of -70 V and at a beam energy of 3 GeV. 47

58 8.3 September 2013 at PSI The third testbeam campaign was carried out at the pim1 beamline at PSI. The pim1 beamline provides pions with a momentum range between 100 MeV/c and 500 MeV/c [pim14], in this testbeam campaign an energy of MeV was used. The pions decay most likely into muons which furthermore decay into electrons so that the chip could also be tested with electrons. All chips were operated in the ToT mode because no telescope was available and therefore efficiency measurements were impossible. During this testbeam also the latency could be measured because upstream and downstream of the MuPix chips timing scintillating tiles were placed (see figure 8.8). The latency is defined as the time between the detection of a particle in the tiles and the detection of the same particle in the MuPix chip. The ToT signal and the time of the two tile signals were measured and stored. Measurements were done with a thick ( 600 µm) and a thinned ( 80 µm) MuPix2 and a thick ( 600 µm) and a thinned ( 90 µm) MuPix3 chip. The following measurements are limited to electrons. The signal size distribution of the front scintillating tile can be seen in figure 8.7. The measurements of the electrons were obtained by cutting on the electron signal. Figure 8.7: Beam composition obtained from the front scintillating tile. 48

59 Figure 8.8: Setup at the PSI testbeam: PCB with the MuPix2 chip and up and downstream scintillating tiles MuPix2 In order to measure the ToT signal in the counting hut, an additional EMO R cable had to be soldered to the PCB. This cable was then connected to an approximately 15 m long BC cable. All measurements were done at a fixed threshold of 840 mv. The ToT increases slightly with increasing high voltage for both the thick and the thinned chip (see figures 8.9 and 8.10). However, the thinned chip seems to not work properly 1 at a high voltage of -90 V. It is observed that pixels at the edge have a shorter ToT than pixels at the centre of the chip. That can be explained by the fact that electrons ionise atoms also at the edge of the chip outside the pixel matrix. This charge has a longer drift path and therefore less charge reaches the electrode (see figure 8.11). The ToT of the thinned chip is longer than the ToT of the thick chip (see figure 8.12) which is the case for all measured pixels, therefore it is most likely no pixel variation effect. This could maybe be explained by a higher electric field of the thinned chip between the p-substrate and the n-well assuming that the size of the depletion layer depends on the thickness of the substrate. The latency of the thick and the thinned chip is almost the same and shows no HV dependence (see figure 8.13), but it can be seen that the latency at -90 V for the thinned chip is slightly higher, which is consistent with the short ToT in figure The latency of a corner pixel is on average longer than of a centre pixel (see figure 8.14) because the charge that is 1 Since the chip could not be tested before thinning, that could also be attributed to a bad chip. 49

60 created outside the pixel matrix needs more time to reach the electrode (see figure 8.11). 1 ToT Entries Mean 2638 RMS ToT Entries Mean 2477 RMS 2084 Events / ToT V 80 V 85 V 90 V Events / ToT V 80 V 85 V 90 V ToT [ns] (a) centre ToT [ns] (b) edge Figure 8.9: ToT histograms of the thick MuPix2 chip for different HV and different pixels normalised to the maximum: 8.9a shows the histograms for centre pixels and 8.9b shows the histograms for edge pixels [Hut14] MuPix3 The ToT signal was tapped at the HB EMO R connector of the PCB. The measurements were done at a threshold of 830 mv and, if not denoted differently, without disabling pixels. Figure 8.15 shows a slight decrease of the ToT for both the thick and thinned chip with increasing high voltage which is not expected. The charge collection should be faster for higher high voltages. The latency decreases with increasing high voltage from 160 ns to 140 ns (see figure 8.16) as expected but the latency is longer (180 ns) for the thin chip. The pixel dependence of the ToT is undefined. As seen in figure 8.17 the ToT distribution is the smallest if no pixels are disabled. This implies that only a very small number of pixels are enabled after switching on the MuPix3 chip. In addition, after every power cycle another set of pixels is enabled. The thinned chip has almost no pixel dependence of the latency but has a higher latency than the thick chip (see figure 8.18). The latency of the thick chip is the longest if only the edge pixels are enabled and it is the shortest if all pixels are enabled which is consistent with the MuPix2 chip. If the edge pixels are 50

61 1 ToT Entries Mean 4136 RMS ToT Entries Mean 3480 RMS V 80 V V 80 V Events / ToT V 90 V Events / ToT V 90 V ToT [ns] (a) centre ToT [ns] (b) edge Figure 8.10: ToT histograms of the thinned MuPix2 chip for different HV and different pixels normalised to the maximum: 8.10a shows the histograms for centre pixels and 8.10b shows the histograms for edge pixels [Hut14]. e e pixel pixel Figure 8.11: The ToT of a corner pixel is shorter and the latency is longer than for a centre pixel if hit by a single particle, which in one case is outside abd in the other case inside the pixel cell. chip 51

62 1 ToT Entries Mean 4290 RMS thin Events / ToT thick ToT [ns] Figure 8.12: ToT histograms for the thick and the thinned MuPix2 chip at a HV of -85 V normalised to the maximum [Hut14] atency [ns] atency [ns] corner pixel centre pixel corner pixel centre pixel HV [V] HV [V] (a) thick (b) thinned Figure 8.13: HV dependence of the latency for a centre and a corner pixel of the MuPix2 chip: 8.13a shows the dependence for the thick chip and 8.13b shows the dependence for the thinned chip. 52

63 atency [ns] Pixel thin thick 0 / 0 17 / / / 19 Figure 8.14: atency for the thick and the thinned MuPix2 chip for different pixels. The numbers on the x-axis represent the pixel addresses (column / row). disabled, the latency should become shorter, because the contribution of the edge pixels with a longer latency is missing. However, this is not the case MuPix4 On the last day, right before packing, the MuPix4 chip was placed in the beam. But there was no time to switch the beam on due to trouble in the accelerator. However, while testing the connection of the ToT signal from the beam area to the hut with a 90 Sr source, the MuPix4 chip detected real particles the first time. 53

64 1 ToT Entries Mean 2286 RMS ToT Entries Mean 2016 RMS V 80 V V 80 V Events / ToT V 90 V Events / ToT V 90 V ToT [ns] (a) thick ToT [ns] (b) thinned Figure 8.15: ToT histograms of the MuPix3 chip for different HV normalised to the maximum: 8.15a shows the histograms for the thick chip and 8.15b shows the histograms for the thinned chip [Hut14]. atency [ns] HV [V] thin thick Figure 8.16: HV dependence of the latency of the thick and the thinned MuPix3 chip. 54

65 1 ToT Entries edgebpixelsbdisabled Mean 2010 RMS 1248 Eventsb/bToT onlybedgebpixelsbenabled allbpixelsbenabled ToT [ns] Figure 8.17: ToT histograms of the thick MuPix3 chip for different pixels at a HV of -85 V normalised to the maximum [Hut14]. 55

66 atency [ns] all without edge only edge Pixel thin thick Figure 8.18: Pixel dependence of the latency of the thick and the thinned Mupix3 chip at a HV of -85 V. 56

67 8.4 October 2013 at DESY The energy of the electron beam was 3 GeV because at this energy the electron rate was close to maximum. During this testbeam the MuPix4 setup of Ivan Perić was used, because the digital crosstalk was too large with our setup at that time (see section 7.1.3) MuPix4 The integration time for the MuPix4 chip readout was set to twice the integration time of the MIMOSA26 chips both before and after the trigger signal. For the timing measurements the integration time had to be shorter. Timing Measurements The timing resolution was obtained by making a histogram of the differences between the timestamps of the chip and the trigger signal from the trigger logic unit (TU). The timing resolution is about 17 ns which is the fastest ever achieved result for MAPS (see the parameter p2 in figure 8.19, note that this value is in units of 10 ns). Figure 8.19: Histogram of the difference between the MuPix4 timestamp and the trigger signal (plot made by iklaus Berger). 57

68 Efficiency Measurements The determination of the efficiency of the MuPix4 chip yielded a value of 99% (see figure 8.20). An improvement is expected, if the measurement is done by tuning the threshold of every pixel individually. Figure 8.20: Plot of the efficiency of the MuPix4 chip [ie15]. 8.5 February 2014 at DESY MuPix4 During this testbeam first the MuPix4 setup of Ivan Perić was used and then our setup was used in the device under test position. The integration time for the MuPix4 chip with our setup was between the last trigger signal and 200 µs after the current trigger signal. The efficiency measurements have only be analysed for the setup of Ivan Perić. Efficiency Measurements With the data taken during this testbeam the efficiency of the MuPix4 chip could be determined for different thresholds and rotation angles relative to the beam direction (see figure 8.21). Efficiencies of more than 96% could be achieved and the best efficiency was almost 100% at a threshold of 823 mv and a rotation angle of

69 Efficiency Rotatedtbyt45tdeg Rotatedtbyt22.5tdeg otrotation Thresholdt[mV] Figure 8.21: Efficiency of the MuPix4 for different rotation angles and thresholds at a HV of -70 V [vb14]. MuPix4 Telescope A first telescope consisting of four MuPix4 chips that are placed one after another has been tested [Hut14]. Correlations between the rows and columns of different chips could be seen and an offline track fitting is in process. The testbeam measurements show that the thinned MuPix2 and MuPix3 prototypes work almost as well as the thick ones but show some unexpected behaviours. It is not yet understood why the ToT of the thinned chips is longer than the ToT of the thick chips. Therefore, more chips has to be thinned and tested. The MuPix4 chip has a very good efficiency of almost 100% and an extremely good timing resolution of 17 ns. 59

70

71 Part III Discussion 61

72

73 9 Discussion and Outlook The proposed Mu3e experiment searches for the lepton flavour violating, and thus in the Standard model forbidden, decay µ + e + e e + with a target sensitivity of < which is four orders of magnitude better than previous experiments [B + 12b]. In the extended Standard model which includes neutrino mixing this decay is suppressed with a branching ratio of BR < Hence the observation of this decay would be a clear hint for new physics beyond the Standard Model. The Mu3e experiment uses HV-MAPS for the tracking detector because these sensors have important advantages. The HV-MAPS have a fast charge collection time and can be thinned down to 50 µm. Consequently the material of the detector can be minimised and therefore, the momentum resolution can be improved by reducing multiple scattering of the positrons and electrons. In this thesis three HV-MAPS prototypes (MuPix2, MuPix3, MuPix4) have been tested. In addition thinned MuPix2 and MuPix3 chips have been tested. The pulse shape of the MuPix2 chip has been measured for temperatures of 30 C and 60 C. The latency increases from 180 ns to 310 ns and the ToT decreased from 5400 ns at 30 C to 2300 ns at 60 C. The ToT measured at the PSI testbeam was about 2000 ns for the thick MuPix2 chip and for the thinned chip a two times higher value of about 4000 ns was measured. This could be explained by the fact that the distance between the p-substrate and the n-well electrode is smaller at the thinned chip and therefore the electric field is stronger. At a high voltage of 90 V the thinned chip seems not to work properly anymore. But since the chip could not be tested before thinning this measurement has to be repeated with more thinned chips. Otherwise, the thinned chip shows good functionality if the high voltage is below 90 V. o timing information of a single pixel could be obtained by measuring the pulse shape of the MuPix3 chip, because the measured ToT signal is always an OR of all enabled pixels. The common ToT signal was measured to have large fluctuations. The ToT measured at the second DESY testbeam with 3 GeV electrons was about 7000 ns at low thresh- 63

74 olds and decreased almost linearly with increasing thresholds. At the same time with increasing HV the ToT decreased slightly. The latency obtained at the PSI testbeam with electrons is for the thick chip between 140 ns and 160 ns whereas the thinned chip has a longer latency of about 180 ns. The ToT was about 2000 ns long. In principle the thinned chip shows the same behaviour as the thick chip. For these measurements only a few pixels were enabled. The MuPix4 chip has to be wire bonded from the chip to the chip carrier to avoid short circuits between the scribe line, which is at the potential of the high voltage, and the signal lines. The timing of the MuPix4 chip has been improved compared to the MuPix2: The ToT is much shorter but the pulse hight is comparable. The MuPix4 chip is also less effected by high temperatures, which can be seen in the SR: The SR for the expected operation conditions for the Mu3e experiment is larger than 31.5 for 70 C at HV = -70 V because temperatures of about 40 C are expected. ew MuPix4 PCBs have been designed where the digital crosstalk of the readout in the hit-flag mode is almost completely eliminated. In the future MuPix4 chips have to be thinned and tested. The efficiency of the MuPix4 chip calculated from the data of the testbeams is almost 100%. Furthermore an excellent timing resolution of 17 ns was determined. The first telescope consisting of four MuPix4 chips has been successfully tested and correlations between the columns and rows of different chips could be seen [Hut14]. The first MuPix6 1 prototype has been wire bonded and is now being tested. The issue of the wrong pixel addresses for every second double row, which the MuPix4 has, has been corrected. The high efficiency and very good spatial and timing resolution of the MuPix4 prototype fulfil already now the specifications of the Mu3e pixel detector. In the coming year larger prototypes with fully integrated digital readout will be designed and tested. 1 The MuPix6 is the fifth HV-MAPS prototype for the Mu3e experiment. 64

75 Part IV Appendix 65

76

77 A ayouts of the MuPix Prototypes In this chapter the layouts of the MuPix prototypes are shown. The lower part of the chip is the digital part where the readout cells are located. This part is also visible to the naked eye. That helps to glue the chip in the right direction on the chip carrier or on the PCB. This part is very large in the MuPix2 chip but has been reduced in the following prototypes. The pixels as well as the bonding pads can be seen. Using a microscope, the IBM R label in the upper left corner and the text MUPIXE in the upper right corner can be seen. 67

78 68 Figure A.1: ayout of the MuPix2 chip.

79 Figure A.2: ayout of the MuPix3 chip. 69

80 70 Figure A.3: ayout of the MuPix4 chip.

81 Figure A.4: ayout of the MuPix6 chip. 71

82

83 B Schematics of the MuPix3 and MuPix4 PCBs The schematics of the MuPix3 PCB and MuPix4 PCB, designed by Dirk Wiedner, are shown in this chapter. The MuPix3 and MuPix4 chip can both be used with the MuPix3 and the MuPix4 PCB. However, the MuPix4 PCB was only used during the DESY testbeam in February The MuPix4 PCB is designed to eliminate the digital crosstalk when the Mupix4 chip is used. The first page of the schematics (see figure B.1a and figure B.2a) shows the chip and its connections. The second page shows the connections of the chip socket (see figure B.1b and figure B.2b). The third page shows the pins of the readout and slow control connectors (see figure B.1c and figure B.2c). On the left side the pins of the readout connector are shown, in the middle the pins of the slow control connector corresponding to the Stratix IV GX FPGA Development it from Altera R are shown and on the right side the pins of the slow control connector corresponding to a Xilinx R FPGA board, which we do not use, are shown. 73

84 F G US S 88 9 VDD VDD 8= Z 84 VDD VDD 8F G 8G VDD VDD F 8 4 8Z VDD VDD = S VDD VDD SR 8R SS =8 VDD VDD S9 == MUPIX3 SZ =4 VDD VDD S =F SG =G VDD VDD SF = S4 =Z VDD VDD S= =9 S8 =S COADDROUTJ9[ ROWADDROUTJR[ 9R =R COADDROUTJS[ ROWADDROUTJS[ 9S 48 COADDROUTJR[ ROWADDROUTJ9[ 99 4= DPIX ROWADDROUTJZ[ 9Z 44 TSIJ4[ ROWADDROUTJ[ 9 4F TSIJF[ ROWADDROUTJG[ 9G 4G TSIJG[ TSOUTJR[ 9F 4 TSIJ[ TSOUTJS[ 94 4Z TSIJZ[ TSOUTJ9[ 9= 49 TSIJ9[ TSOUTJZ[ 98 4S TSIJS[ TSOUTJ[ ZR 4R TSIJR[ TSOUTJG[ ZS F8 DCO TSOUTJF[ Z9 F= RDCO TSOUTJ4[ ZZ F4 PUD COADDROUTJG[ Z HB FF ZG PRIOUT COADDROUTJ[ COADDROUTJZ[ FG Z 9 S REVISIOYRECORD TR ECOYO7 APPROVED7 DATE7 VersionYR>S Wiedner S=>R9>9RSZ VersionY9>R Wiedner SF>RG>9RSZ VCCY_YVDDY_YVDDAY_YVDDASV= COMPAY7 PhysikalischesYInstitutYderYUniYHeidelberg TITE7 DRAW7 DATED7 DirkYWiedner SF>G>9RSZ MuPixZYTestYBoardYV9 CHECED7 DATED7 JCheckedYBy[ JCheckedYDate[ QUAITYYCOTRO7 DATED7 JQCYBy[ JQCYDate[ CODE7 SIZE7 DRAWIGYO7 REV7 JCode[ B S S REEASED7 DATED7 JReleasedYBy[ JReleaseYDate[ SCAE7 JScale[ OF S 8 SHEET7Y D C B A ZF Z4 VCC Z= Z8 VCC R S VCC 9 Z VDD VDD G F C 4 C = C 8 C GR C GS C G9 C GZ SOUTD G SOUTC GG SI GF CD G4 CC G= DC G8 FR VCC FS F9 VCC FZ F VCC VDD SUB VDD SUB VDDA A VSSA VCASC VPBIASTDAC B TH HBVDD SUBSTRATE VDE VPDE C IJECT IJECT9 VSSA VDD VDD SUB VDD SUB S9= S94 S9F S9G S9 S9Z S99 S9S S9R SS8 SS= SS4 SSF SSG SS SSZ SS9 SSS SSR SR8 SR= SR4 SRF SRG SR SRZ SR9 SRS SRR [9g8] COADDOUT_9 [9g8] COADDOUT_S [9g8] COADDOUT_R [9g8] DPIX [9g8] TSI_4 [9g8] TSI_F [9g8] TSI_G [9g8] TSI_ [9g8] TSI_Z [9g8] TSI_9 [9g8] TSI_S [9g=g8] TSI_R [9g8] DCO [9g8] RDCO MUPIXZ_PART ROWADDOUT_R [9g8] ROWADDOUT_S [9g8] ROWADDOUT_9 [9g8] ROWADDOUT_Z [9g8] ROWADDOUT_ [9g8] ROWADDOUT_G [9g8] TSOUT_R [9g8] TSOUT_S [9g8] TSOUT_9 [9g8] TSOUT_Z [9g8] TSOUT_ [9g8] TSOUT_G [9g8] TSOUT_F [9g8] TSOUT_4 [9g8] COADDOUT_G [9g8] COADDOUT_ [9g8] COADDOUT_Z [9g8] [9g8] [9g8] [9g8] [9g8] [9g8] SOUT_D SOUT_C C_D C_C D_C VDDAS>=V[Sg9ggGgFg=] [Sg9gZgg4g=g8] SUBSTRATE [Sg9g] VDDAS>=V [Sg9ggGgFg=] [Sg9gZgg4g=g8] SUBSTRATE [Sg9g] VDDAS>=V[Sg9ggGgFg=] A [9ggGgFg=] VSSA [Sg9gg=] VCASC [9gFg=] VPBIASDAC [9gFg=] B [9gFg=] TH [9gGg=] HBVDD [9g=] SUBSTRATE [Sg9g] VDE [9gF] VPDE [9gF] IJECTS [9gGg=] IJECT9 [9gGg=] VSSA [Sg9gg=] [Sg9gZgg4g=g8] VDDAS>=V[Sg9ggGgFg=] VDDAS>=V[Sg9ggGgFg=] [Sg9gZgg4g=g8] SUBSTRATE [Sg9g] VDDAS>=V[Sg9ggGgFg=] [Sg9gZgg4g=g8] SUBSTRATE [Sg9g] [Sg9ggGgFg=] VDDAS>=V [Sg9gZgg4g=g8] [Sg9ggGgFg=] VDDAS>=V [Sg9gZgg4g=g8] [Sg9ggGgFg=] VDDAS>=V [Sg9gZgg4g=g8] [Sg9ggGgFg=] VDDAS>=V [Sg9gZgg4g=g8] [Sg9ggGgFg=] VDDAS>=V [Sg9gZgg4g=g8] [Sg9ggGgFg=] VDDAS>=V [Sg9gZgg4g=g8] [Sg9ggGgFg=] VDDAS>=V [Sg9gZgg4g=g8] [Sg9ggGgFg=] VDDAS>=V [Sg9gZgg4g=g8] [Sg9ggGgFg=] VDDAS>=V [Sg9gZgg4g=g8] [9g8] PU_DOW [9g=g8] HB [9g8] PRIOUT VDDAS>=V [Sg9ggGgFg=] [Sg9gZgg4g=g8] VDDAS>=V [Sg9ggGgFg=] [Sg9gZgg4g=g8] VDDAS>=V [Sg9ggGgFg=] [Sg9gZgg4g=g8] VDDAS>=V [Sg9ggGgFg=] [Sg9gZgg4g=g8] VDDAS>=V [Sg9ggGgFg=] [Sg9gZgg4g=g8] VDDAS>=V [Sg9ggGgFg=] [Sg9gZgg4g=g8] VDDAS>=V [Sg9ggGgFg=] [Sg9gZgg4g=g8] VDDAS>=V [Sg9ggGgFg=] [Sg9gZgg4g=g8] VDDAS>=V [Sg9ggGgFg=] [Sg9gZgg4g=g8] [Sg9gZgg4g=g8] [Sg9ggGgFg=] [Sg9gZgg4g=g8] [Sg9ggGgFg=] [Sg9gZgg4g=g8] [Sg9ggGgFg=] [Sg9gZgg4g=g8] D C B A [Sg9ggGgFg=] [Sg9ggGgFg=] [Sg9gZgg4g=g8] [9g8] [Sg9gZgg4g=g8] [Sg9ggGgFg=] [Sg9gZgg4g=g8] [Sg9ggGgFg=] [Sg9gZgg4g=g8] [Sg9ggGgFg=] VDDAS>=V VDDAS>=V VDDAS>=V VDDAS>=V VDDAS>=V SI VDDAS>=V VDDAS>=V VDDAS>=V 74 (a) Schematic of the MuPix3 PCB (page 1/9): The connections of the chip are shown.

85 F G Y REVISIOCRECORD TR ECOCO7 APPROVED7 DATE7 VersionCAZ Wiedner =ZAZA VersionCZA Wiedner FZAGZA =G U VCCC,CVDDC,CVDDAC,CVDDAV= COMPAY7 TITE7 DRAW7 DATED7 DirkCWiedner FZGZA PhysikalischesCInstitutCderCUniCHeidelberg MuPixCTestCBoardCV CHECED7 DATED7 [CheckedCBy] [CheckedCDate] QUAITYCCOTRO7 DATED7 [QCCBy] [QCCDate] CODE7 SIZE7 DRAWIGCO7 REV7 [Code] B REEASED7 DATED7 [ReleasedCBy] [ReleaseCDate] SCAE7 [Scale] 8 SHEET7C OF D C B A Y G F 4 = 8 YA Y Y Y YY YG YF Y4 Y= Y8 GA G G G A 8 = 4 F G Y =Y = = = =A 48 4= 44 4F 4G [E8] COADDOUT_ [E8] COADDOUT_ [E8] COADDOUT_A [E8] DPIX [E8] TSI_4 [E8] TSI_F [E8] TSI_G [E8] TSI_Y [E8] TSI_ [E8] TSI_ [E8] TSI_ [E=E8] TSI_A [E8] DCO [E8] RDCO [E8] PU_DOW [E=E8] HB [E8] PRIOUT PCC=Y_SOCET_PART [EEEYE4E=E8] [EEYEGEFE=] [EEEYE4E=E8] [EEYEGEFE=] [EEEYE4E=E8] [EEYEGEFE=] [EEEYE4E=E8] [EEYEGEFE=] [EEYEGEFE=] [EEEYE4E=E8] [E8] [E8] [E8] [E8] [E8] [E8] [EEEYE4E=E8] [EEYEGEFE=] [EEEYE4E=E8] [EEYEGEFE=] VDDAZ=V VDDAZ=V VDDAZ=V VDDAZ=V D C B A VDDAZ=V SOUT_D SOUT_C SI C_D C_C D_C VDDAZ=V VDDAZ=V VDDAZ=V [EEYEGEFE=] [EEEYE4E=E8] SUBSTRATE [EEY] VDDAZ=V [EEYEGEFE=] A [EYEGEFE=] VSSA [EEYE=] VCASC [EFE=] VPBIASDAC [EFE=] B [EFE=] TH [EGE=] HBVDD [E=] SUBSTRATE [EEY] VDE [EF] VPDE [EF] IJECT [EGE=] IJECT [EGE=] VSSA [EEYE=] [EEEYE4E=E8] VDDAZ=V [EEYEGEFE=] VDDAZ=V [EEYEGEFE=] [EEEYE4E=E8] [EEYEGEFE=]VDDAZ=V [EEEYE4E=E8] [EEYEGEFE=] VDDAZ=V [EEEYE4E=E8] 4Y VDDAZ=V [EEYEGEFE=] 4 [EEEYE4E=E8] Y 4 VDDAZ=V [EEYEGEFE=] G 4 [EEEYE4E=E8] F 4A ROWADDOUT_A [E8] 4 F8 ROWADDOUT_ [E8] = F= ROWADDOUT_ [E8] 8 F4 ROWADDOUT_ [E8] A FF ROWADDOUT_Y [E8] FG ROWADDOUT_G [E8] FY TSOUT_A [E8] F TSOUT_ [E8] Y F TSOUT_ [E8] G F TSOUT_ [E8] F FA TSOUT_Y [E8] 4 G8 TSOUT_G [E8] = G= TSOUT_F [E8] 8 G4 TSOUT_4 [E8] A GF COADDOUT_G [E8] GG COADDOUT_Y [E8] GY COADDOUT_ [E8] (b) Schematic of the MuPix3 PCB (page 2/9): The connections of the chip socket are shown. 75

86 P7[:FAOYA P7[:FAOYA F G YAuPinuHeaderEuadaptsutoJ 7T]R7uHSM_u[ebuguHeaderu/reakoutu/oarduJuand XilinxuFM_uXMAGu[ebugu_arduJ P7[ G[ [EEEYE4E,Ep] J: R]S]RV][_ J: R]TUR_ J: [PIX_VG [p] J:Y TSOUT_A_IV [p] J:G XIIX J:F TSOUT IV [p] J:4 [_O_VG [p] J:, TSOUT IV [p] J:p TSI_A_VG [p] J:A TSOUT IV [p] J: TSI VG [p] J: TSOUT_Y_IV [p] J: TSI VG [p] J:Y TSOUT_G_IV [p] J:G TSI VG [p] J:F TSOUT_F_IV [p] J:4 TSI_Y_VG [p] J:, TSOUT_4_IV [p] J:p TSI_G_VG [p] J:A _O7[[OUT_A_IV [p] J: TSI_F_VG [p] J: _O7[[OUT IV [p] J: TSI_4_VG [p] J:Y _O7[[OUT IV [p] J:G ROW7[[OUT_A_IV [p] J:F _O7[[OUT IV [p] J:4 ROW7[[OUT IV [p] J:, _O7[[OUT_Y_IV [p] J:p ROW7[[OUT IV [p] J:A XIIX J: ROW7[[OUT IV [p] J: _O7[[OUT_G_IV [p] J: ROW7[[OUT_Y_IV [p] J:Y XIIX Y J:G ROW7[[OUT_G_IV [p] J:F PU_[OW_VG [p] J:4 R[_O_VG [p] J:, PRIOUT_IV [p] J:p R]S]RV][_ J:YA R]TUR_ P7[ G[ [EEEYE4E,Ep] J:EuJ:pu_lkufromu7T]R7uFPG7 J:EuJ:YAu_lkutou7T]R7uFPG7 J:EJ:GEuJ:AEuJ:Yu_lkureserveduforuXilinxuFPG7 Y P7[:FAOYA P7[:FAOYA R]VISIOuR]_OR[ YAuPinuHeaderEuadaptsutoJ 7T]R7uHSM_u[ebuguHeaderu/reakoutu/oarduJuand TR ]_OuOJ 7PPROV][J [7T]J VersionuAZ Wiedner,ZAZA VersionuZA Wiedner FZAGZA P7[ G[ [EEEYE4E,Ep] YAuPinuHeaderEuadaptsutoJ XilinxuFM_uXMAGu[ebugu_arduJ J: R]S]RV][_ J: R]TUR_ J: XIIX G J: FPG7_][ [E,] FPG7_][ FPG7_][ [E,] J: J:Y FPG7_][ [E,] J: J:Y [E,] J:G FPG7_][ [E,] J:F FPG7_][Y [E,] J:G XIIX F J:F FPG7_][Y J:4 J:, T]STPUS]_ [EGE,] T]STPUS]_ [EGE,] FPG7_][ [E,] J:4 J:, [E,] H/_IV [E,Ep] J:p J:A J:p J:A T]STPUS]_ [EGE,] T]STPUS]_ [EGE,] J: SOUT_[_IV [Ep] J: SOUT IV [Ep] J: H/_IV [E,Ep] J: SI_VG [Ep] J: J:Y [ VG [Ep] J: J:Y SOUT_[_IV [Ep] SOUT IV [Ep] J:G J:F [_VG [Ep] VG [Ep] SI_VG [Ep] J:G J:F [ VG [Ep] J:4 J:, SPI_[I [EGE,] SPI [EGE,] [_VG [Ep] J:4 J:, VG [Ep] J:p SPI_[ [EGE,] J:A J:p SPI_[I [EGE,] J:A SPI [EGE,] FPG7_7UX_ J: J: FPG7_7UX_A [E,] FPG7_7UX_ [E,] SPI_[ [EGE,] J: J: [E,] FPG7_7UX_A FPG7_7UX_ J: J:Y FPG7_7UX_ [E,] FPG7_7UX_ [E,] J: J:Y [E,] [E,] FPG7_7UX_ FPG7_7UX_G J:G J:F FPG7_7UX_Y [E,] FPG7_7UX_G [E,] J:G J:F [E,] [E,] FPG7_7UX_Y J:4 J:, FPG7_7UX_F [E,] FPG7_7UX_4 [E,] FPG7_7UX_4 J:4 J:, [E,] [E,] FPG7_7UX_F J:p J:A [E,] FPG7_7UX_p [E,] FPG7_7UX_, J:p J:A XIIX 4 [E,] J: P [E4] J: RST_P [E4] J: FPG7_7UX_, J: FPG7_7UX_p [E,] [E,] J: [E4] J:Y RST_ [E4] J: P [E4] J:Y /USY_P [E4] J:G /USY_P [E4] J:F TRG_P [E4] J:G [E4] J:F /USY_ [E4] [ _ / 7 J:4 /USY_ [E4] J:, TRG_ [E4] J:4 RST_P [E4] J:, TRG_P [E4] J:p R]S]RV][_Y J:YA R]TUR_Y J:p RST_ [E4] J:YA TRG_ [E4] P7[Y G[ [EEEYE4E,Ep] J:EuJ:pu_lkufromu7T]R7uFPG7 J:EuJ:YAu_lkutou7T]R7uFPG7 _OMP7YJ J:EJ:GEuJ:Au_lkureserveduforuXilinxuFPG7 PhysikalischesuInstitutuderuUniuHeidelberg TIT]J [R7WJ [7T][J [irkuwiedner FZGZA MuPixuTestu/oarduV _H]_][J [7T][J -_heckedu/ym -_heckedu[atem QU7ITYu_OTROJ [7T][J -Q_u/ym -Q_u[atem _O[]J SIZ]J [R7WIGuOJ R]VJ -_odem / R]]7S][J [7T][J -Releasedu/ym -Releaseu[atem S_7]J -Scalem OF p SH]]TJu [ _ / 7 76 (c) Schematic of the MuPix3 PCB (page 3/9): The pins of the slow control and readout cables are shown.

87 + ], [ G Y V++u:uVu ]OOA AOOnF ]OO ROOA FuF :uk A ]OO AOnF A OUT_:V SESE G+,YP UOOA 8 I F G+ G G+ Y OT_SH+ TAFG ]OO AOOnF ]OOY FuF V++[u:V ]OAA AOOnF ]OA ROAA FuF :uk A ]OA AOnF A OUT_:V SESE G+,YP UOO 8 I F G+ G G+ Y OT_SH+ TAFG ]OA AOOnF ]OAY FuF ]OA AOOnF ]O ROA FuF :uk A ]O V++[uA:8uV A OUT_A:8V SESE G+,YP UOO 8 I F G+ G G+ Y OT_SH+ AOnF ]O AOOnF TAFGA8 ]OG AOOnF VSS[ ]OA AOOnF ]O ROA FuF :uk A VSS[_[+J ]O A OUT [+J G+,YP UOO 8 I F G+ G G+ Y OT_SH+ AOnF ]O AOOnF TAFG RO O A RO Auk A A connectuonlyuv++[yv SM[uPoweru]onnectors JOOA JOO TR REVISIOuRE]OR+ E]OuOf [PPROVE+f +[TEf VersionuO:A Wiedner A8:O:OA Versionu:O Wiedner AG:OY:OA JOO ]OOG AOOnF wao A HV_I SU,STR[TE [] [A9] ROYA ]OYA AOOnF ]OY AOOnF JOOEA JOOE ]OAG AOOnF ]OAF AOOnF ]OA8 AOOnF ]OAw AOOnF JOOE V]]u_uV++u_uV++[u_uV++[AV8 useuregulatorutougenerateuv++[:v ]anubeushorted inf ROGO O ROGA A A OGA A :FuH Vuforuinverters ]OMP[Yf PhysikalischesuInstitutuderuUniuHeidelberg TITEf +R[Wf +[TE+f +irkuwiedner AG:Y:OA MuPixuTestu,oarduV ]HE]E+f +[TE+f =]heckedu,y7 =]heckedu+ate7 QU[ITYu]OTROf +[TE+f =Q]u,y7 =Q]u+ate7 ]O+Ef SIZEf +R[WIGuOf REVf =]ode7, A A REE[SE+f +[TE+f =Releasedu,y7 =Releaseu+ate7 S][Ef =Scale7 OF w SHEETfu + ], [ ]OYO AOOuF V++:V [98] V++[:V [9Y98] V++[A:8V [A999Y9G98] V++:V V++[:V G+[ G+[ G+[ G+[ G+[ G+[ G+[ [A999Y9G98] [A999Y9G98] [A999Y9G98] [A999Y9G98] [A999Y9G98] [A999Y9G98] [A999Y9G98] G+[ [A999Y9G98] G+[ [A999Y9G98] G+[ [A999Y9G98] V++[A:8V G+[ [A999Y9G98] G+[ [A999Y9G98] G+[ [A999Y9G98] V++[YV [9Y] V++[A:8V [A999Y9G98] G+[ [A999Y9G98] VSS[ [A9998] VSS[ [A9998] VSS[ [] V++[YV [9Y] VSS[_[+J [] G+[ G+[ G+[ G+[ G+[ G+[ [A999Y9G98] [A999Y9G98] [A999Y9G98] [A999Y9G98] [A999Y9G98] [A999Y9G98] V++YV [98] V++[YV [9Y] ]OF AOOnF G+[ [A999Y9G98] V++YV [98] V++[YV [9Y] HV_I [] V++:V [98] G+[ [A999Y9G98] G+[ [A999Y9G98] G+[ [A999Y9G98] G+[ [A999Y9G98] V++[A:8V [A999Y9G98] V++[:V JOOE V++[:V [9Y98] [9Y98] VSS[ [A9998] G+[ [A999Y9G98] G+[ [A999Y9G98] G+[ [A999Y9G98] G+[ [A999Y9G98] V++:V [98] V++[YV [9Y] V++[:V [9Y98] V++YV [98] ]O8 AOOnF ]Ow AOOnF ]OO AOOnF ]OA AOOnF ]O AOOnF ]O AOOnF G+[ [A999Y9G98] 4V [] V++:V [98] O ROGY A 4V [] ]OGA AOOnF ]OG AOOnF ]OG AOOnF ]OG AOOnF (d) Schematic of the MuPix3 PCB (page 4/9). 77

88 J ], [ F G ThresholduJ[] ] JI J JOUT Y UA T]FGj j V]] 4 VOUT F REF G GJ RA k InjectionuJ[] ] JI J JOUT Y U T]FGj j V]] 4 VOUT F REF G GJ ]A AApF Y [EGEj] [Ej] [EGEj] SPI_] SPI_JI SPI_J J[]_JOUT [G] VJJ[ZV [YEGEj] REF_TH [G] GJ[ [EEYEGEFEj] TH_J[]_OUT A [EEYEGEFEj] VJJ[ZjV REF_TH [G] RA GJ[ [EEYEGEFEj] R k AA RA ] AApF ]A AAnF [G] [EGEj] SPI_] [G] J[]_JOUT [EGEj] SPI_J J[]_OUT VJJ[ZV [YEGEj] VJJ[ZjV[EEYEGEFEj] GJ[ [EEYEGEFEj] IJE]TIO_J[]_OUT GJ[ [EEYEGEFEj] ] JI J JOUT Y U T]FGj j V]] 4 VOUT F REF G GJ R k AA Rj ]4 ApF k R8 ]j nf U ]OM G V9 O GJ Y I SHOPPER_ M[XYGY GA RA AA R ] AApF ] AAnF [EGEj] [G] [EGEj] SPI_] J[]_OUT SPI_J J[]_OUT VJJ[ZV [YEGEj] VJJ[ZjV[EEYEGEFEj] GJ[ [EEYEGEFEj] IJE]TIO_J[]_OUT GJ[ [EEYEGEFEj] [G] V][_IJE]TIO [Ej] TESTPUSE_ [G] V][_IJE]TIO AA R ] AAnF k R8 [EEj] IJE]T STEP_ VJJ[ZV [YEGEj] IJE]T [EEj] AA Rj ]4 ApF GJ[ [EEYEGEFEj] STEP_ ]j nf GJ[ [EEYEGEFEj] TH_J[]_OUT_FITEREJ GJ[ [EEYEGEFEj] IJE]TIO_J[]_OUT_FITEREJ GJ[ [EEYEGEFEj] IJE]TIO_J[]_OUT_FITEREJ GJ[ [EEYEGEFEj] [Ej] TESTPUSE_ U ]OM G V9 O GJ Y I M[XYGY SHOPPER_ VJJ[ZV [YEGEj] GA RYA OUT V]]: I9 OUT V]]: I9 OUT V]]: I9 REVISIOuRE]ORJ TR E]OuO7 [PPROVEJ7 J[TE7 VersionuAZ Wiedner jzaza VersionuZA Wiedner FZAGZA A A A TH_[MP_OUT TH_FITEREJ TH_OUT TH [EEj] RAY RA4 RAj UA G V]]9 Y I: VJJ[GV [YEG] ]A AAnF ]AY nf inf RAG ]AG AAnF GA RAF ]AF AAnF ]A4 Y4uF MV4 GJ[ [EEYEGEFEj] GJ[ [EEYEGEFEj] IJE]TIO_[MP_OUT A A IJE]TIO_FITEREJ V][_IJE]TIO V][_IJE]TIO [G] RY R4 U G V]]9 Y I: VJJ[GV [YEG] R k ] nf inf ]Y RG AAnF k RF ]G AAnF ]F Y4uF MV4 GJ[ GJ[ [EEYEGEFEj] [EEYEGEFEj] A A IJE]TIO_[MP_OUT IJE]TIO_FITEREJ V][_IJE]TIO [G] RY R4 U G V]]9 Y I: VJJ[GV [YEG] R k ] nf inf ]Y RG AAnF k RF ]G AAnF ]F Y4uF MV4 GJ[ [EEYEGEFEj] GJ[ [EEYEGEFEj] ]OMP[Y7 PhysikalischesuInstitutuderuUniuHeidelberg TITE7 JR[W7 J[TEJ7 JirkuWiedner FZGZA MuPixuTestu,oarduV ]HE]EJ7 J[TEJ7 -]heckedu,yf -]heckedujatef QU[ITYu]OTRO7 J[TEJ7 -Q]u,yf -Q]uJatef ]OJE7 SIZE7 JR[WIGuO7 REV7 -]odef, REE[SEJ7 J[TEJ7 -Releasedu,yf -ReleaseuJatef S][E7 -Scalef OF G 8 SHEET7u J ], [ 78 (e) Schematic of the MuPix3 PCB (page 5/9).

89 D C B A F G Y VPBiasdac VCASC B VDDAZ8V [EEYEGEFE8] CA AAnF VDDAZ8V [EEYEGEFE8] C AAnF VDDAZ8V [EEYEGEFE8] C AAnF VPBIASDAC [EE8] P Ak VCASC [EE8] P Ak CA AAnF RA AAk C AAnF C AAnF A A A [EEYEGEFE8] [EEYEGEFE8] [EEYEGEFE8] VPDEuanduVDE VPDE VDE [E] [E] C AAnF C AAnF VDDAZ8V A [EEYEGEFE8] [EEYEGEFE8] DRAW, DATED, DirkuWiedner FZGZA CHECED, DATED, <CheckeduBy> <CheckeduDate> QUAITYuCOTRO, DATED, <QCuBy> <QCuDate> REEASED, DATED, <ReleaseduBy> <ReleaseuDate> REVISIOuRECORD TR ECOuO, APPROVED, DATE, VersionuAZ Wiedner 8ZAZA VersionuZA Wiedner FZAGZA B [EE8] COMPAY, PhysikalischesuInstitutuderuUniuHeidelberg TITE, MuPixuTestuBoarduV CODE, SIZE, DRAWIGuO, REV, <Code> B SCAE, <Scale> OF F [ SHEET,u D C B A (f) Schematic of the MuPix3 PCB (page 6/9). 79

90 D C B A G Y RJYuconnectorutouEudetuTriggeruogicuUnit DRAW8 DATED8 DirkuWiedner AG:Y:OA CHECED8 DATED8 _CheckeduBy] _CheckeduDate] QUAITYuCOTRO8 DATED8 _QCuBy] _QCuDate] REEASED8 DATED8 _ReleaseduBy] _ReleaseuDate] A REVISIOuRECORD TR ECOuO8 APPROVED8 DATE8 VersionuO:A Wiedner A4:O:OA Versionu:O Wiedner AG:OY:OA COMPAY8 PhysikalischesuInstitutuderuUniuHeidelberg TITE8 MuPixuTestuBoarduV CODE8 SIZE8 DRAWIGuO8 REV8 _Code] B A A SCAE8 _Scale] OF F J SHEET8u D C B A A Y G F 4 J AO JY BUE4ERJY [A9999F949J] C_ [] C_P [] BUSY_ [] RST_ [] RST_P [] BUSY_P [] TRG_ [] TRG_P [] [A9999F949J] 80 (g) Schematic of the MuPix3 PCB (page 7/9).

91 , ] [ / G Poweru_,s RYOA AOO [] _,YOA V,,YV RYO G4 _,YO [] V,,:V RYO G4 _,YO [9Y] V,,/:V RYO YA [A999Y9G94] V,,/A:4V _,YO RYOY YA _,YOY [A9994] VSS/ VSS/uA:YVu tooulowuforu_,u H[V,, H[V,, [A9] JYO4 V,,/A:4V [A999Y9G94] A ]YOA AOOpF G,/ [A999Y9G94] P/,YOA P/,EOOSZAOO T_STPUS A P/,YO P/,EOOSZAOO T_STPUS P/,YO P/,EOOSZAOO SPI_] P/,YO P/,EOOSZAOO SPI_,I SPI_, [9Y] [9Y] [9Y] [9Y] [9Y] Y P/,YAA P/,EGOZO P/,YA P/,EGOZO P/,YAY P/,EGOZO P/,YAF P/,EGOZO P/,YAp P/,EGOZO P/,YA P/,EGOZO P/,YA P/,EGOZO P/,YAG P/,EGOZO P/,YA4 P/,EGOZO P/,YO P/,EGOZO [A99G] [A99Y] [A99G] [A99G] [A9994] _MOuTestpoints JYOp JYOA H[ [A99p] H[_IV [9p] JYO IJ_]TA [A99Y] JYO IJ_]T [A99Y] JYO TSI_O [A99p] analogeutestpoints [ TH V]/S] VP[I/S,/] VSS/ JYOG AO JEXY G,/ [A999Y9G94] G,/ [A999Y9G94],R/Ww,/T_,w,irkuWiedner AG:Y:OA ]H_]_,w,/T_,w!]heckedu[y7!]heckedu,ate7 QU/ITYu]OTROw,/T_,w!Q]u[y7!Q]u,ate7 R /S_,w,/T_,w!Releasedu[y7!Releaseu,ate7 A R_VISIOuR_]OR, TR _]OuOw /PPROV_,w,/T_w VersionuO:A Wiedner A4:O:OA Versionu:O Wiedner AG:OY:OA ParalelluFPG/uauxilliaryubus [] [] [] [] [] FPG/_/UX_O FPG/_/UX_ FPG/_/UX_ FPG/_/UX_G FPG/_/UX_4 JYOF JEXY AO FPG/_/UX_A [] FPG/_/UX_ [] FPG/_/UX_Y [] FPG/_/UX_F [] FPG/_/UX_p [] RYAA G4 [] FPG/,A _,YAA RYA G4 [] FPG/, _,YA RYA G4 [] FPG/, _,YA RYA G4 [] FPG/, _,YA G, [A9999F9p] ]OMP/Yw PhysikalischesuInstitutuderuUniuHeidelberg TIT_w MuPixuTestu[oarduV ]O,_w SIZ_w,R/WIGuOw R_Vw!]ode7 [ A A S]/_w!Scale7 OF 4 p SH Twu, ] [ / A A Y F p G 4 A Y F p G 4 (h) Schematic of the MuPix3 PCB (page 8/9). 81

92 D C B A F G Y ZGVutouZ8VuCMOSuconversion RA 4A RA 4A RAG 4A RA4 4A RAv 4A R 4A R 4A RG 4A RA F8A RAY F8A RAF F8A RA8 F8A RA F8A R F8A RY F8A RF F8A R4 4A Rv 4A R 4A R 4A RG 4A R4 4A Rv 4A R 4A PU_DOW [E] R8 F8A RA F8A R F8A RY F8A RF F8A R8 F8A RA F8A R F8A REVISIOuRECORD Z8VutouZVuCMOSuconversion TR ECOuO7 APPROVED7 DATE7 VersionuAZ Wiedner 8ZAZA VersionuZA Wiedner FZAGZA UA:A UA:A UA:A UAY:A MC4YACAYSC MC4YACAYSC COADDOUT_A_IV MC4YACAYSC [] ROWADDOUT_A_IV MC4YACAYSC [] UA:B UA:B UA:B UAY:B Y Y Y Y MC4YACAYSC MC4YACAYSC COADDOUT IV MC4YACAYSC [] ROWADDOUT IV MC4YACAYSC [] UA:C UA:C UA:C UAY:C G F G F G F G F MC4YACAYSC MC4YACAYSC COADDOUT_ COADDOUT IV [E] MC4YACAYSC [] ROWADDOUT IV [] MC4YACAYSC UA:D UA:D UA:D UAY:D v 8 v 8 v 8 v 8 MC4YACAYSC MC4YACAYSC COADDOUT IV MC4YACAYSC [] ROWADDOUT IV MC4YACAYSC [] UA:E UA:E UA:E UAY:E A A A A MC4YACAYSC MC4YACAYSC COADDOUT_Y_IV MC4YACAYSC [] ROWADDOUT_Y_IV MC4YACAYSC [] UA:F UA:F UA:F UAY:F MC4YACAYSC MC4YACAYSC COADDOUT_G_IV MC4YACAYSC [] ROWADDOUT_G ROWADDOUT_G_IV [E] MC4YACAYSC [] InvertersuuseuVDDV COMPAY7 PhysikalischesuInstitutuderuUniuHeidelberg TITE7 DRAW7 DATED7 DirkuWiedner FZGZA MuPixuTestuBoarduV CHECED7 DATED7 _CheckeduBy] _CheckeduDate] QUAITYuCOTRO7 DATED7 _QCuBy] _QCuDate] CODE7 SIZE7 DRAWIGuO7 REV7 _Code] B REEASED7 DATED7 _ReleaseduBy] _ReleaseuDate] SCAE7 _Scale] OF v v SHEET7u D C B A TSI_A_VG [] TSI VG [] TSI VG [] TSI VG [] TSI_Y_VG [] TSI_G_VG [] TSI_F_VG [] TSI_4_VG [] TSI_A [EE8] TSI_ [E] TSI_ [E] TSI_ [E] TSI_Y [E] TSI_G [E] TSI_F [E] TSI_4 [E] [EEEYE4E8Ev] C_C_VG [] C_D_VG [] DCO_VG [] DPIX_VG [] D_C_VG [] PU_DOW_VG [] RDCO_VG [] SI_VG [] C_C [E] C_D [E] DCO [E] DPIX [E] D_C [E] RDCO [E] SI [E] [EEEYE4E8Ev] HB [EE8] PRIOUT [E] SOUT_C [E] SOUT_D [E] TSOUT_A [E] TSOUT_ [E] HB_IV [E8] TSOUT_ [E] TSOUT IV [] COADDOUT_A [E] ROWADDOUT_A [E] PRIOUT_IV [] TSOUT_ [E] TSOUT IV [] COADDOUT_ [E] ROWADDOUT_ [E] SOUT_C_IV [] TSOUT_Y [E] TSOUT_Y_IV [] ROWADDOUT_ [E] SOUT_D_IV [] TSOUT_G [E] TSOUT_G_IV [] COADDOUT_ [E] ROWADDOUT_ [E] TSOUT_A_IV [] TSOUT_F [E] TSOUT_F_IV [] COADDOUT_Y [E] ROWADDOUT_Y [E] TSOUT IV [] TSOUT_4 [E] TSOUT_4_IV [] COADDOUT_G [E] 82 (i) Schematic of the MuPix3 PCB (page 9/9). Figure B.1: Schematic of the MuPix3 PCB.

93 5 F G 9 TP_VPCOMP Z TP_VC]SC TP_I G TP_VSS] F TP_VDD] 5 TP_] 6 TP_DP_WE = TP_S_WE 8 TP_DR]I_PMOS 9S TP_G]TE_PMOS 99 TP_VDD_PIXE 9Z TP PIXE 9 TP PIXEZ 9G TP_G]TE_MOS9 9F TP_DR]I_MOS9 95 TP_OUT9 96 TP_OUTZ 9= TP_G]TE_MOSZ 98 TP_DR]I_MOSZ ZS TP_DPWEZ Z9 CO]DDROUTXZ? ZZ CO]DDROUTX9? Z CO]DDROUTXS? MuPixG VDD VDD VDD VDD VDD ]PDZS9_DC ]PDZS9_DC ]PDZS9_DC ]PDZS9_DC VDD VDD ROW]DDROUTXS? ROW]DDROUTX9? ROW]DDROUTXZ? ROW]DDROUTX? ZG DPIX ZF TSIX6? Z5 TSIX5? Z6 TSIXF? Z= TSIXG? Z8 TSIX? S TSIXZ? 9 TSIX9? Z TSIXS? DCO G RDCO F PUD 5 HB 6 PRIOUT ROW]DDROUTXG? ROW]DDROUTXF? TSOUTXS? TSOUTX9? TSOUTXZ? TSOUTX? TSOUTXG? TSOUTXF? TSOUTX5? TSOUTX6? CO]DDROUTXF? CO]DDROUTXG? CO]DDROUTX? 9S9 9SS 88 8= F 8G 8 8Z 89 8S =8 == =6 =5 =F =G = =Z =9 =S 68 6= F 6G 6 6Z 69 6S 58 5= 56 Z 9 REVISIODRECORD TR ECODO_ ]PPROVED_ D]TE_ VersionDSQ9 Wiedner 9ZQ9ZQZS9 VCCDJDVDDDJDVDD]DJDVDD]9V= CO]DDOUT_F [Z<8] COMP]Y_ CO]DDOUT_G [Z<8] CO]DDOUT_ [Z<8] PhysikalischesDInstitutDderDUniDHeidelberg TITE_ DR]W_ D]TED_ DirkDWiedner SGQ9ZQZS9 MuPixGDTestDBoardDV9 CHECED_ D]TED_ XCheckedDBy? XCheckedDDate? QU]ITYDCOTRO_ D]TED_ XQCDBy? XQCDDate? CODE_ SIZE_ DR]WIGDO_ REV_ XCode? B 9 9 REE]SED_ D]TED_ XReleasedDBy? XReleaseDDate? SC]E_ XScale? OF 9 8 SHEET_D D C B ] = 8 VDD GS G9 VDD GZ G VDD GG GF VDD G5 VDD G6 G= SUBSTR]TE G8 C FS C F9 C FZ C F C FG C FF SOUTD F5 SOUTC F6 SI F= CD F8 CC 5S DC 59 5Z VDD 5 5G VDD 5F 55 VDD TP_C TP_SI TP_IJ TP_SUBSTR]TE[ TP_SUBSTR]TE[ TP_SUBSTR]TE[ VDD] ] VSS] VC]SC VPBI]STD]C B TH VDDR]M SUBSTR]TE VDE VPDE C[ IJECT9 IJECTZ VSS] ] VDD] VDD SUBSTR]TE VDD SUBSTR]TE 9S 9Z8 9Z= 9Z6 9Z5 9ZF 9ZG 9Z 9ZZ 9Z9 9ZS = F 99G 99 99Z S 9S8 9S= 9S6 9S5 9SF 9SG 9S 9SZ U9 MUPIXG_P]RT [9<Z<<G<6<=<8] VDD]9Q=V [9<Z<G<F<5<=] [9<Z<<G<6<=<8] VDD]9Q=V [9<Z<G<F<5<=] [9<Z<<G<6<=<8] VDD]9Q=V [9<Z<G<F<5<=] [9<Z<<G<6<=<8] VDD]9Q=V [9<Z<G<F<5<=] [9<Z<<G<6<=<8] VDD]9Q=V [9<Z<G<F<5<=] [9<Z<<G<6<=<8] VDD]9Q=V [9<Z<G<F<5<=] [9<Z<<G<6<=<8] ROW]DDOUT_S [Z<8] ROW]DDOUT_9 [Z<8] ROW]DDOUT_Z [Z<8] ROW]DDOUT_ [Z<8] ROW]DDOUT_G [Z<8] ROW]DDOUT_F [Z<8] TSOUT_S [Z<8] TSOUT_9 [Z<8] TSOUT_Z [Z<8] TSOUT_ [Z<8] TSOUT_G [Z<8] TSOUT_F [Z<8] TSOUT_5 [Z<8] TSOUT_6 [Z<8] [9<Z<<G<6<=<8] [9<Z<G<F<5<=] [9<Z<<G<6<=<8] [9<Z<G<F<5<=] [9<Z<<G<6<=<8] [9<Z<G<F<5<=] [9<Z<<G<6<=<8] [9<Z<G<F<5<=] [9<Z<G<F<5<=] [9<Z<<G<6<=<8] [9<Z<G] [Z<8] [Z<8] [Z<8] [Z<8] [Z<8] [Z<8] [9<Z<<G<6<=<8] [9<Z<G<F<5<=] [9<Z<<G<6<=<8] [9<Z<G<F<5<=] [9<Z<<G<6<=<8] [9<Z<G<F<5<=] VDD]9Q=V VDD]9Q=V VDD]9Q=V VDD]9Q=V VDD]9Q=V SUBSTR]TE SOUT_D SOUT_C SI C_D C_C D_C VDD]9Q=V VDD]9Q=V VDD]9Q=V VDD]9Q=V ] VSS] VC]SC VPBI]SD]C B TH HBVDD SUBSTR]TE VDE VPDE IJECT9 IJECTZ VSS] ] VDD]9Q=V VDD]9Q=V SUBSTR]TE VDD]9Q=V SUBSTR]TE [9<Z<G<F<5<=] [9<Z<G<F<5<=] [9<Z<G<=] [Z<5<=] [Z<5<=] [Z<5<=] [Z<F<=] [Z<5] [9<Z<G] [Z<5] [Z<5] [Z<F<=] [Z<F<=] [9<Z<G<=] [9<Z<G<F<5<=] [9<Z<G<F<5<=] [9<Z<G<F<5<=] [9<Z<<G<6<=<8] [9<Z<G] [9<Z<G<F<5<=] [9<Z<<G<6<=<8] [9<Z<G] [Z<8] [Z<8] [Z<8] [Z<8] [Z<8] [Z<8] [Z<8] [Z<8] [Z<8] [Z<8] D C B ] [Z<8] [Z<=<8] [Z<8] [Z<8] [Z<8] [Z<=<8] [Z<8] CO]DDOUT_Z CO]DDOUT_9 CO]DDOUT_S DPIX TSI_6 TSI_5 TSI_F TSI_G TSI_ TSI_Z TSI_9 TSI_S DCO RDCO PU_DOW HB PRIOUT VDD]9Q=V [9<Z<G<F<5<=] (a) Schematic of the MuPix4 PCB (page 1/9): The connections of the chip are shown. 83

94 5 F G Y REVISIOBRECORD TR ECOBO7 APPROVED7 DATE7 VersionBO Wiedner =OOY VersionBO Wiedner 5OFOY VersionBYO Wiedner GOOY =F U VCCB,BVDDB,BVDDAB,BVDDAV= COMPAY7 TITE7 DRAW7 DATED7 DirkBWiedner GOOY PhysikalischesBInstitutBderBUniBHeidelberg MuPixGBTestBBoardBV CHECED7 DATED7 [CheckedBBy] [CheckedBDate] QUAITYBCOTRO7 DATED7 [QCBBy] [QCBDate] CODE7 SIZE7 DRAWIGBO7 REV7 [Code] B REEASED7 DATED7 [ReleasedBBy] [ReleaseBDate] SCAE7 [Scale] 8 SHEET7B OF D C B A YY YG YF Y5 Y6 Y= Y8 G G G GY GG GF G5 G6 G= G8 F F F FY 8 = 6 5 F G Y =G =Y = = = 68 6= F [:8] COADDOUT_ [:8] COADDOUT_ [:8] COADDOUT_ [:8] DPIX [:8] TSI_6 [:8] TSI_5 [:8] TSI_F [:8] TSI_G [:8] TSI_Y [:8] TSI_ [:8] TSI_ [:=:8] TSI_ [:8] DCO [:8] RDCO [:8] PU_DOW [:=:8] HB [:8] PRIOUT PCC=G_SOCET_PART [::Y:G:6:=:8] [::G:F:5:=] [::Y:G:6:=:8] [::G:F:5:=] [::Y:G:6:=:8] [::G:F:5:=] [::Y:G:6:=:8] [::G:F:5:=] [::G:F:5:=] [::Y:G:6:=:8] [:8] [:8] [:8] [:8] [:8] [:8] [::Y:G:6:=:8] [::G:F:5:=] [::Y:G:6:=:8] [::G:F:5:=] VDDAO=V VDDAO=V VDDAO=V VDDAO=V D C B A VDDAO=V SOUT_D SOUT_C SI C_D C_C D_C VDDAO=V VDDAO=V VDDAO=V [::G:F:5:=] [::Y:G:6:=:8] SUBSTRATE [::G] VDDAO=V [::G:F:5:=] A [:G:F:5:=] VSSA [::G:=] VCASC [:5:=] VPBIASDAC [:5:=] B [:5:=] TH [:F:=] HBVDD [:5] SUBSTRATE [::G] VDE [:5] VPDE [:5] IJECT [:F:=] IJECT [:F:=] VSSA [::G:=] [::Y:G:6:=:8] VDDAO=V [::G:F:5:=] VDDAO=V [::G:F:5:=] [::Y:G:6:=:8] [::G:F:5:=]VDDAO=V [::Y:G:6:=:8] [::G:F:5:=] VDDAO=V [::Y:G:6:=:8] 6G VDDAO=V [::G:F:5:=] Y 6Y [::Y:G:6:=:8] G 6 VDDAO=V [::G:F:5:=] F 6 [::Y:G:6:=:8] 5 6 ROWADDOUT_ [:8] 6 58 ROWADDOUT_ [:8] = 5= ROWADDOUT_ [:8] 8 56 ROWADDOUT_Y [:8] 55 ROWADDOUT_G [:8] 5F ROWADDOUT_F [:8] 5G TSOUT_ [:8] Y 5Y TSOUT_ [:8] G 5 TSOUT_ [:8] F 5 TSOUT_Y [:8] 5 5 TSOUT_G [:8] 6 F8 TSOUT_F [:8] = F= TSOUT_5 [:8] 8 F6 TSOUT_6 [:8] Y F5 COADDOUT_F [:8] Y FF COADDOUT_G [:8] Y FG COADDOUT_Y [:8] 84 (b) Schematic of the MuPix4 PCB (page 2/9): The connections of the chip socket are shown.

95 P7[Z5AG P7[Z5AG 5 F G>Pin>Header:>adapts>toJ 7T]R7>HSM_>[ebug>Header>/reakout>/oard>J>and Xilinx>FM_>XMF>[ebug>_ard>J P7[ G[ [::Y:G:6:,:p] JZ R]S]RV][_ JZ R]TUR_ JZY [PIX_VF [p] JZG TSOUT IV [p] JZF XIIX JZ5 TSOUT IV [p] JZ6 [_O_VF [p] JZ, TSOUT IV [p] JZp TSI VF [p] JZ TSOUT_Y_IV [p] JZ TSI VF [p] JZ TSOUT_G_IV [p] JZY TSI VF [p] JZG TSOUT_F_IV [p] JZF TSI_Y_VF [p] JZ5 TSOUT_5_IV [p] JZ6 TSI_G_VF [p] JZ, TSOUT_6_IV [p] JZp TSI_F_VF [p] JZ _O7[[OUT IV [p] JZ TSI_5_VF [p] JZ _O7[[OUT IV [p] JZY TSI_6_VF [p] JZG _O7[[OUT IV [p] JZF ROW7[[OUT IV [p] JZ5 _O7[[OUT_Y_IV [p] JZ6 ROW7[[OUT IV [p] JZ, _O7[[OUT_G_IV [p] JZp ROW7[[OUT IV [p] JZY XIIX Y JZY ROW7[[OUT_Y_IV [p] JZY _O7[[OUT_F_IV [p] JZYY ROW7[[OUT_G_IV [p] JZYG XIIX G JZYF ROW7[[OUT_F_IV [p] JZY5 PU_[OW_VF [p] JZY6 R[_O_VF [p] JZY, PRIOUT_IV [p] JZYp R]S]RV][_ JZG R]TUR_ P7[ G[ [::Y:G:6:,:p] JZ:>JZYp>_lk>from>7T]R7>FPG7 JZ:>JZG>_lk>to>7T]R7>FPG7 JZ:JZF:>JZY:>JZYG>_lk>reserved>for>Xilinx>FPG7 G P7[Z5AG P7[Z5AG Y R]VISIO>R]_OR[ G>Pin>Header:>adapts>toJ 7T]R7>HSM_>[ebug>Header>/reakout>/oard>J>and TR ]_O>OJ 7PPROV][J [7T]J Version>O Wiedner,OOY Version>O Wiedner 5OFOY Version>YO Wiedner GOOY P7[Y G[ [::Y:G:6:,:p] G>Pin>Header:>adapts>toJ Xilinx>FM_>XMF>[ebug>_ard>JY JZ R]S]RV][_Y JZ R]TUR_Y JYZ XIIX F JYZ FPG7_][ [Y:,] FPG7_][ FPG7_][ [Y:,] JZY JZG FPG7_][ [Y:,] JYZY JYZG [Y:,] JZF FPG7_][Y [Y:,] JZ5 FPG7_][G [Y:,] JYZF XIIX 5 JYZ5 FPG7_][G JZ6 JZ, T]STPUS]_ [Y:F:,] T]STPUS]_ [Y:F:,] FPG7_][Y [Y:,] JYZ6 JYZ, [Y:,] H/_IV [Y:,:p] JZp JZ JYZp JYZ T]STPUS]_ [Y:F:,] T]STPUS]_ [Y:F:,] JZ SOUT_[_IV [Y:p] JZ SOUT IV [Y:p] JYZ H/_IV [Y:,:p] JYZ SI_VF [Y:p] JZY JZG [ VF [Y:p] JYZY JYZG SOUT_[_IV [Y:p] SOUT IV [Y:p] JZF JZ5 [_VF [Y:p] VF [Y:p] SI_VF [Y:p] JYZF JYZ5 [ VF [Y:p] JZ6 JZ, SPI_[I [Y:F:,] SPI [Y:F:,] [_VF [Y:p] JYZ6 JYZ, VF [Y:p] JZp SPI_[ [Y:F:,] JZ JYZp SPI_[I [Y:F:,] JYZ SPI [Y:F:,] FPG7_7UX_ JZ JZ FPG7_7UX_ [Y:,] FPG7_7UX_ [Y:,] SPI_[ [Y:F:,] JYZ JYZ [Y:,] FPG7_7UX_ FPG7_7UX_Y JZY JZG FPG7_7UX_ [Y:,] FPG7_7UX_Y [Y:,] JYZY JYZG [Y:,] [Y:,] FPG7_7UX_ FPG7_7UX_F JZF JZ5 FPG7_7UX_G [Y:,] FPG7_7UX_F [Y:,] JYZF JYZ5 [Y:,] [Y:,] FPG7_7UX_G JZ6 JZ, FPG7_7UX_5 [Y:,] FPG7_7UX_6 [Y:,] FPG7_7UX_6 JYZ6 JYZ, [Y:,] [Y:,] FPG7_7UX_5 JZp JZY [Y:,] FPG7_7UX_p [Y:,] FPG7_7UX_, JYZp JYZY XIIX 6 [Y:,] JZY P [Y:6] JZY RST_P [Y:6] JYZY FPG7_7UX_, JYZY FPG7_7UX_p [Y:,] [Y:,] JZYY [Y:6] JZYG RST_ [Y:6] JYZYY P [Y:6] JYZYG /USY_P [Y:6] JZYF /USY_P [Y:6] JZY5 TRG_P [Y:6] JYZYF [Y:6] JYZY5 /USY_ [Y:6] [ _ / 7 JZY6 /USY_ [Y:6] JZY, TRG_ [Y:6] JYZY6 RST_P [Y:6] JYZY, TRG_P [Y:6] JZYp R]S]RV][_G JZG R]TUR_G JYZYp RST_ [Y:6] JYZG TRG_ [Y:6] P7[G G[ [::Y:G:6:,:p] JZ:>JZYp>_lk>from>7T]R7>FPG7 JZ:>JZG>_lk>to>7T]R7>FPG7 _OMP7YJ JYZ:JYZF:>JYZY>_lk>reserved>for>Xilinx>FPG7 Physikalisches>Institut>der>Uni>Heidelberg TIT]J [R7WJ [7T][J [irk>wiedner GOOY MuPixG>Test>/oard>V _H]_][J [7T][J -_hecked>/ym -_hecked>[atem QU7ITY>_OTROJ [7T][J -Q_>/ym -Q_>[atem _O[]J SIZ]J [R7WIG>OJ R]VJ -_odem / R]]7S][J [7T][J -Released>/ym -Release>[atem S_7]J -Scalem OF Y p SH]]TJ> [ _ / 7 85 (c) Schematic of the MuPix4 PCB (page 3/9): The pins of the slow control and readout cables are shown.

96 ], [ - 5, nf, R G6uF YOYUk, nf, R G6uF YOYUk G]- G]- [::G:F:5:8] [::G:F:5:8],G nf F G Y R YOYUk,Y nf,y nf,y V]]UYOYUVU OUT_YOYV S+S+ Y G] G [YP U I 8 6 G] G] 5 OT_SH] F T65YYY V]]-UYOYV OUT_YOYV S+S+ Y G] G [YP U I 8 6 G] G] 5 OT_SH] F T65YYY V]]-UO8UV OUT_O8V S+S+ Y G] G [YP UY I 8 6 G] G] 5 OT_SH] F T65Y8,G nf,g nf nf,g nf,f G6uF,F G6uF R5F,5 nf YVUforUinverters connectuonlyuv]]-fv,5 nf,5 nf,6 nf SM-UPowerU,onnectors J J JY,8 nf V,,UpUV]]UpUV]]-UpUV]]-V8 TR R+VISIOUR+,OR] +,OUOf w HV_I SU[STR-T+ [G] [:] JGZ RF,F nf,w nf,f nf +xtraucapacitorsuatumupixu,arrier,anubeushorted -PPROV+]f ]-T+f VersionUO Wiedner 8OOY VersionUO Wiedner 5OFOY VersionUYO Wiedner GOOY JGZ JGZY JGZG useuregulatorutougenerateuv]]-yoyv inf R5 R5 5 GO6uH Jw,OMP-Yf PhysikalischesUInstitutUderUUniUHeidelberg,G G6uF RG YOYUk VSS-_-]J,GY OUT -]J Y G] G [YP UG I 8 6 G] G] 5 OT_SH] F nf,gg nf T65Y RG RGY Uk ]R-Wf ]-T+]f,H+,+]f ]irkuwiedner =,heckedu[y_ =Q,U[y_ GOOY ]-T+]f QU-ITYU,OTROf ]-T+]f =,heckedu]ate_ =Q,U]ate_ TIT+f,O]+f SIZ+f MuPixGUTestU[oardUV ]R-WIGUOf =,ode_ [ R+Vf R++-S+]f ]-T+]f =ReleasedU[y_ =ReleaseU]ate_ S,-+f =Scale_ OF G w SH++TfU ], [ -,F uf V]]YOYV [G:8] V]]-YOYV [G:F:8] V]]-O8V [::G:F:5:8] VSS- [::G:8],GF uf,,, uf nf G6uF G]- G]- [::G:F:5:8] [::G:F:5:8],G5 uf,g6 uf V]]YOYV V]]-YOYV V]]-O8V V]]YOYV [G:8] V]]-FV [G:F] V]]-O8V [::G:F:5:8],6 nf V]]FV [G:8] V]]-FV [G:F] EYV [G],8 nf V]]YOYV [G:8] V]]-YOYV [G:F:8],w nf,y nf,y nf,y nf,yy nf V]]FV [G:8] V]]-FV [G:F] HV_I [G] VSS- [::G:8] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] V]]-O8V [::G:F:5:8] V]]-O8V [::G:F:5:8] V]]-O8V [::G:F:5:8], nf, uf,f uf,w uf,fy nf, uf,5 uf, uf,fg nf V]]YOYV [G:8] V]]-FV [G:F],Y uf,6 uf, uf,g uf,8 uf, uf J5 J6 J8 G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] V]]-O8V [::G:F:5:8] V]]-YOYV [G:F:8] V]]-YOYV [G:F:8] V]]FV [G:8] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] EYV [G] V]]-O8V [::G:F:5:8],Y uf,g uf,f uf G]- [::G:F:5:8] G]- [::G:F:5:8] G] [::Y:6:8:w] V]]-FV [G:F] VSS- VSS- [::G:8],5 nf,5 nf,5y nf,5g nf VSS- [G] VSS-_-]J [G] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- [::G:F:5:8] G]- G]- [::G:F:5:8] [::G:F:5:8] G]- [::G:F:5:8] 86 (d) Schematic of the MuPix4 PCB (page 4/9).

97 J ], [ F G ThresholdUJ[] ] JI J JOUT Y UA T]FGj j V]] 6 VOUT F REF G GJ RA k InjectionUJ[] ] JI J JOUT Y U T]FGj j V]] 6 VOUT F REF G GJ ]A AApF Y [EGEj] [Ej] [EGEj] SPI_] SPI_JI SPI_J J[]_JOUT [G] VJJ[ZV [YEGEj] REF_TH [G] GJ[ [EEYEGEFEj] TH_J[]_OUT A [EEYEGEFEj] VJJ[ZjV REF_TH [G] RA ]AA AuF GJ[ [EEYEGEFEj] GJ[ [EEYEGEFEj] R k AA RA ] AApF ]A AAnF [G] [EGEj] SPI_] [G] J[]_JOUT [EGEj] SPI_J J[]_OUT VJJ[ZV [YEGEj] VJJ[ZjV[EEYEGEFEj] GJ[ [EEYEGEFEj] IJE]TIO_J[]_OUT GJ[ [EEYEGEFEj] ] JI J JOUT Y U T]FGj j V]] 6 VOUT F REF G GJ R k AA Rj ]6 ApF k R8 ]j nf U ]OM G V9 O GJ Y I SHOPPER_ M[XYGY GA RA AA R ] AApF ] AAnF [EGEj] [G] [EGEj] SPI_] J[]_OUT SPI_J J[]_OUT VJJ[ZV [YEGEj] VJJ[ZjV[EEYEGEFEj] GJ[ [EEYEGEFEj] IJE]TIO_J[]_OUT GJ[ [EEYEGEFEj] [G] V][_IJE]TIO [Ej] TESTPUSE_ [G] V][_IJE]TIO AA R ] AAnF k R8 [EEj] IJE]T STEP_ VJJ[ZV [YEGEj] IJE]T [EEj] AA Rj ]6 ApF GJ[ [EEYEGEFEj] STEP_ ]j nf GJ[ [EEYEGEFEj] TH_J[]_OUT_FITEREJ GJ[ [EEYEGEFEj] IJE]TIO_J[]_OUT_FITEREJ GJ[ [EEYEGEFEj] IJE]TIO_J[]_OUT_FITEREJ GJ[ [EEYEGEFEj] [Ej] TESTPUSE_ U ]OM G V9 O GJ Y I M[XYGY SHOPPER_ VJJ[ZV [YEGEj] GA RYA OUT V]]: I9 OUT V]]: I9 OUT V]]: I9 REVISIOURE]ORJ TR E]OUO7 [PPROVEJ7 J[TE7 VersionUAZ Wiedner jzaza VersionUZA Wiedner VersionUZA Wiedner AYZZA FZAGZA A A A TH_[MP_OUT TH_FITEREJ TH_OUT RAY RA6 RAj TH [EEj] UA G V]]9 Y I: VJJ[GV [YEG] ]A AAnF ]AY nf inf RAG ]AG AAnF GA RAF ]AF AAnF ]A6 Y6uF ]Aj AuF ]A8 AuF MV6 GJ[ [EEYEGEFEj] GJ[ [EEYEGEFEj] IJE]TIO_[MP_OUT A A IJE]TIO_FITEREJ V][_IJE]TIO V][_IJE]TIO [G] RY R6 U G V]]9 Y I: VJJ[GV [YEG] R k ] nf inf ]Y RG AAnF k RF ]G AAnF ]F Y6uF MV6 GJ[ GJ[ [EEYEGEFEj] [EEYEGEFEj] A A IJE]TIO_[MP_OUT IJE]TIO_FITEREJ V][_IJE]TIO [G] RY R6 U G V]]9 Y I: VJJ[GV [YEG] R k ] nf inf ]Y RG AAnF k RF ]G AAnF ]F Y6uF MV6 GJ[ [EEYEGEFEj] GJ[ [EEYEGEFEj] ]OMP[Y7 PhysikalischesUInstitutUderUUniUHeidelberg TITE7 JR[W7 J[TEJ7 JirkUWiedner AYZZA MuPixYUTestU,oardUV ]HE]EJ7 J[TEJ7 -]heckedu,yf -]heckedujatef QU[ITYU]OTRO7 J[TEJ7 -Q]U,yf -Q]UJatef ]OJE7 SIZE7 JR[WIGUO7 REV7 -]odef, REE[SEJ7 J[TEJ7 -ReleasedU,yf -ReleaseUJatef S][E7 -Scalef OF G 8 SHEET7U J ], [ (e) Schematic of the MuPix4 PCB (page 5/9). 87

98 D C B A VPBIASDAC [EE8] F G Y VPBiasdac VCASC B VDDAZ8V [EEYEGEFE8] CA AAnF VDDAZ8V [EEYEGEFE8] C AAnF C AuF VDDAZ8V [EEYEGEFE8] C AAnF P Ak VCASC [EE8] P Ak CAY AuF CA AuF CA AAnF RA AAk C AAnF CY AuF CF AuF C AAnF A A A [EEYEGEFE8] [EEYEGEFE8] [EEYEGEFE8] VPDEUandUVDE VPDE VDE HBVDD [E] C AAnF C AuF [E] C AAnF HBVDD JGA8 CY [E] AuF VDDAZ8V [EEYEGEFE8] CGA AApF CGA AuF VDDAZ8V A [EEYEGEFE8] [EEYEGEFE8] A [EEYEGEFE8] DRAWp DATEDp DirkUWiedner AYZZA CHECEDp DATEDp,CheckedUBy>,CheckedUDate> QUAITYUCOTROp DATEDp,QCUBy>,QCUDate> REEASEDp DATEDp,ReleasedUBy>,ReleaseUDate> REVISIOURECORD TR ECOUOp APPROVEDp DATEp VersionUAZ Wiedner 8ZAZA VersionUZA Wiedner FZAGZA VersionUZA Wiedner AYZZA C AuF B [EE8] CY AuF CG AuF COMPAYp PhysikalischesUInstitutUderUUniUHeidelberg TITEp MuPixYUTestUBoardUV CODEp SIZEp DRAWIGUOp REVp,Code> B SCAEp,Scale> OF F J SHEETpU D C B A 88 (f) Schematic of the MuPix4 PCB (page 6/9).

99 D C B A F G RJYGUconnectorUtoUEudetUTriggerUogicUUnit Y DRAW8 DATED8 DirkUWiedner AYZZA CHECED8 DATED8 _CheckedUBy] _CheckedUDate] QUAITYUCOTRO8 DATED8 _QCUBy] _QCUDate] REEASED8 DATED8 _ReleasedUBy] _ReleaseUDate] REVISIOURECORD TR ECOUO8 APPROVED8 DATE8 VersionUAZ Wiedner 6ZAZA VersionUZA Wiedner FZAGZA VersionUZA Wiedner AYZZA COMPAY8 PhysikalischesUInstitutUderUUniUHeidelberg TITE8 MuPixYUTestUBoardUV CODE8 SIZE8 DRAWIGUO8 REV8 _Code] B SCAE8 _Scale] OF 5 J SHEET8U D C B A Y G F 5 6 J A JG BU:6:RJYG [EEEYE5E6EJ] C_ [] C_P [] BUSY_ [] RST_ [] RST_P [] BUSY_P [] TRG_ [] TRG_P [] [EEEYE5E6EJ] (g) Schematic of the MuPix4 PCB (page 7/9). 89

100 , ] [ / F PowerU_,s RGA AA [Y] _,GA V,,GV RGA F6 _,GA [Y] V,,ZV RGA F6 _,GA [YEG] V,,/ZV RGAY G [EEYEGEF] V,,/Z6V _,GAY RGAG G _,GAG [EEYE6] VSS/ VSS/UZGVU tooulowuforu_,h P/,GA P/,:AASOAA T_STPUS P/,GA P/,:AASOAA T_STPUS P/,GA P/,:AASOAA SPI_] P/,GAY P/,:AASOAA SPI_,I SPI_, [EG] [EG] [EG] [EG] [EG] G P/,G P/,:FAOYA P/,G P/,:FAOYA P/,GG P/,:FAOYA P/,G5 P/,:FAOYA P/,Gp P/,:FAOYA P/,G P/,:FAOYA P/,GY P/,:FAOYA P/,GF P/,:FAOYA P/,G6 P/,:FAOYA P/,GA P/,:FAOYA [EEF] [EEG] [EEF] [EEF] [EEYE6] Y _MOUTestpoints JGAp JGA H[ [EEp] H[_IV [Ep] JGA IJ_]T [EEG] JGA IJ_]T [EEG] JGAY TSI_A [EEp] [ TH V]/S] VP[I/S,/] VSS/ P/,:FAOYA P/,G P/,:FAOYA P/,F P/,:FAOYA P/,5 P/,:FAOYA P/,6 P/,:FAOYA P/,p P/,:FAOYA P/,A P/,:FAOYA P/, P/,:FAOYA P/, P/,:FAOYA P/, P/,:FAOYA P/,Y JGAF P/,:FAOYA P/,G P/,:FAOYA P/,F P/,:FAOYA P/,5 P/,:FAOYA P/,6 A P/,:FAOYA P/,p J:XG P/,:FAOYA P/,A analogeutestpoints G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G, [EEEYE5E6Ep] G,/ [EEYEGEFE6],R/Ww,/T_,w,irkUWiedner AYZZA G,/ ]H_]_,w,/T_,w [EEYEGEFE6]!]heckedU[y7!]heckedU,ate7 QU/ITYU]OTROw,/T_,w!Q]U[y7!Q]U,ate7 R /S_,w,/T_,w!ReleasedU[y7!ReleaseU,ate7 R_VISIOUR_]OR, TR _]OUOw /PPROV_,w,/T_w VersionUAZ Wiedner 6ZAZA VersionUZA Wiedner FZAGZA VersionUZA Wiedner AYZZA ParalellUFPG/UauxilliaryUbus [] [] [] [] [] FPG/_/UX_A FPG/_/UX_ FPG/_/UX_Y FPG/_/UX_F FPG/_/UX_6 JGA5 J:XG A FPG/_/UX_ [] FPG/_/UX_ [] FPG/_/UX_G [] FPG/_/UX_5 [] FPG/_/UX_p [] RG F6 [] FPG/, _,G RG F6 [] FPG/, _,G RG F6 [] FPG/, _,G RGY F6 [] FPG/,Y _,GY G, [EEEYE5E6Ep] ]OMP/Yw PhysikalischesUInstitutUderUUniUHeidelberg TIT_w MuPixYUTestU[oardUV ]O,_w SIZ_w,R/WIGUOw R_Vw!]ode7 [ S]/_w!Scale7 OF 6 p SH TwU, ] [ / G 5 p Y F 6 G 5 p Y F 6 90 (h) Schematic of the MuPix4 PCB (page 8/9).

101 D C B A 5 F G OFVUtoUO8VUCMOSUconversion R 6 RY 6 RF 6 R6 6 Rv 6 R 6 RY 6 RF 6 R 58 RG 58 R5 58 R8 58 R 58 R 58 RG 58 R5 58 R6 6 Rv 6 R 6 RY 6 RF 6 R6 6 Rv 6 RY 6 PU_DOW [:] R8 58 R 58 R 58 RG 58 R5 58 R8 58 RY 58 RY 58 Y REVISIOURECORD O8VUtoUYOYVUCMOSUconversion TR ECOUO7 APPROVED7 DATE7 VersionUO Wiedner 8OOY VersionUO Wiedner 5OFOY VersionUYO Wiedner GOOY UZA UZA UYZA UGZA MC6GACGSC MC6GACGSC COADDOUT IV MC6GACGSC [Y] ROWADDOUT IV MC6GACGSC [Y] UZB UZB UYZB UGZB Y G Y G Y G Y G MC6GACGSC MC6GACGSC COADDOUT IV MC6GACGSC [Y] ROWADDOUT IV MC6GACGSC [Y] UZC UZC UYZC UGZC F 5 F 5 F 5 F 5 MC6GACGSC MC6GACGSC COADDOUT_ COADDOUT IV [:] MC6GACGSC [Y] ROWADDOUT IV [Y] MC6GACGSC UZD UZD UYZD UGZD v 8 v 8 v 8 v 8 MC6GACGSC MC6GACGSC COADDOUT_Y_IV MC6GACGSC [Y] ROWADDOUT_Y_IV MC6GACGSC [Y] UZE UZE UYZE UGZE MC6GACGSC MC6GACGSC COADDOUT_G_IV MC6GACGSC [Y] ROWADDOUT_G_IV MC6GACGSC [Y] UZF UZF UYZF UGZF Y Y Y Y MC6GACGSC MC6GACGSC COADDOUT_F_IV MC6GACGSC [Y] ROWADDOUT_F ROWADDOUT_F_IV [:] MC6GACGSC [Y] InvertersUuseUVDDYVY COMPAY7 PhysikalischesUInstitutUderUUniUHeidelberg TITE7 DRAW7 DATED7 DirkUWiedner GOOY MuPixGUTestUBoardUV CHECED7 DATED7 _CheckedUBy] _CheckedUDate] QUAITYUCOTRO7 DATED7 _QCUBy] _QCUDate] CODE7 SIZE7 DRAWIGUO7 REV7 _Code] B REEASED7 DATED7 _ReleasedUBy] _ReleaseUDate] SCAE7 _Scale] OF v v SHEET7U D C B A TSI VF [Y] TSI VF [Y] TSI VF [Y] TSI_Y_VF [Y] TSI_G_VF [Y] TSI_F_VF [Y] TSI_5_VF [Y] TSI_6_VF [Y] TSI_ [::8] TSI_ [:] TSI_ [:] TSI_Y [:] TSI_G [:] TSI_F [:] TSI_5 [:] TSI_6 [:] [::Y:G:6:8:v] C_C_VF [Y] C_D_VF [Y] DCO_VF [Y] DPIX_VF [Y] D_C_VF [Y] PU_DOW_VF [Y] RDCO_VF [Y] SI_VF [Y] C_C [:] C_D [:] DCO [:] DPIX [:] D_C [:] RDCO [:] SI [:] [::Y:G:6:8:v] HB [::8] PRIOUT [:] SOUT_C [:] SOUT_D [:] TSOUT_ [:] TSOUT_ [:] HB_IV [Y:8] TSOUT_ [:] TSOUT IV [Y] COADDOUT_ [:] ROWADDOUT_ [:] PRIOUT_IV [Y] TSOUT_Y [:] TSOUT_Y_IV [Y] COADDOUT_ [:] ROWADDOUT_ [:] SOUT_C_IV [Y] TSOUT_G [:] TSOUT_G_IV [Y] ROWADDOUT_ [:] SOUT_D_IV [Y] TSOUT_F [:] TSOUT_F_IV [Y] COADDOUT_Y [:] ROWADDOUT_Y [:] TSOUT IV [Y] TSOUT_5 [:] TSOUT_5_IV [Y] COADDOUT_G [:] ROWADDOUT_G [:] TSOUT IV [Y] TSOUT_6 [:] TSOUT_6_IV [Y] COADDOUT_F [:] (i) Schematic of the MuPix4 PCB (page 9/9). 91 Figure B.2: Schematic of the MuPix4 PCB.

102

103 C Bonding Diagrams for the MuPix4 Chip Figure C.1 shows the bonding diagram to wire bond the MuPix4 chip to a carrier and figure C.2 shows the diagram to wire bond it directly on a MuPix4 PCB. The dashed lines symbolise the additional wires for power and ground to reduce the digital crosstalk. Since the carrier has less bonding pads than the chip, some power and ground pads of the chip have to be wire bonded to the same carrier pad. The bonding diagrams for both the MuPix3 and MuPix4 chip can also be obtained from the schematics of the MuPix3 and MuPix4 PCBs (see appendix B). 93

104 VpComp VCasc In vssa vdda gnda DPWell SWell Drain PMOS Gate PMOS VDD Pixel Gnd Pixel Gnd Pixel i Gate mosr Drain mosr Out r Out i Gate mosi Drain mosi sub sub sub h strateh strateh strateh vdda gnda vssa VCasc VPBias B Th VDD asubd VDel VPDel DAC RAM strate VDD sub VDD sub strate strate Injectr Injecti vssa gnda vdda DPWell i ColAddr Outbi- ColAddr Outbr- ColAddr Outbl- dpix TSInbk- TSInbu- TSInbx- TSInbt- TSInbM- TSInbi- TSInbr- TSInbl- dcol RdColh PullD HB PriOut gnd vdd vdd gnd VDD VDD VDD substrate h h h h h h RowAddr Outbl- RowAddr Outbr- RowAddr Outbi- RowAdrr OutbM- RowAddr Outbt- RowAddr Outbx- TSOut bl- TSOut br- TSOut bi- TSOut bm- TSOut bt- TSOut bx- TSOut bu- TSOut bk- ColAddr Outbx- ColAddr Outbt- ColAddr OutbM- SoutD SoutC SIn CkD CkC dc VDD VDD VDD VDD VDD VDD VDD VDD h h h h VDD VDD VDDArgjV [rvivtvxvuvj] [rvivmvtvkvjv<] SUBSTRATE [rvivt] VDDArgjV [rvivtvxvuvj] A [rvtvxvuvj] VSSA [rvivtvj] VCASC [rvuvj] VPBIASDAC [rvuvj] B [rvuvj] TH [rvxvj] HBVDD [rvj] SUBSTRATE [rvivt] VDE [rvu] VPDE [rvu] IJECTr [rvxvj] IJECTi [rvxvj] VSSA [rvivtvj] [rvivmvtvkvjv<] VDDArgjV [rvivtvxvuvj] VDDArgjV [rvivtvxvuvj] [rvivmvtvkvjv<] vm jx rr rl < j k u x t M i r jt jm ji jr jl k< kj kk ku kx Ui [rvivtvxvuvj]vddargjv [rvivmvtvkvjv<] [rv<] [rv<] [rv<] [rv<] [rv<] [rv<] [rv<] [rv<] [rv<] [rv<] [rv<] [rvjv<] [rv<] [rv<] [rv<] [rvjv<] [rv<] [rvivtvxvuvj] VDDArgjV [rvivmvtvkvjv<] COADDOUT_i COADDOUT_r COADDOUT_l DPIX TSI_k TSI_u TSI_x TSI_t TSI_M TSI_i TSI_r TSI_l DCO RDCO PU_DOW HB PRIOUT ri rm rt rx ru rk rj r< il ir ii im it ix iu ik ij i< Ml Mr Mi IBM Ck SIn Inj Test Pixel d Do ot Connect MUPIXBt APDilrM Do not connect kt km ki kr kl u< uj uk uu ux ut um ui ur ul x< xj xk xu xx xt VDDArgjV [rvivtvxvuvj] [rvivmvtvkvjv<] VDDArgjV [rvivtvxvuvj] [rvivmvtvkvjv<] ROWADDOUT_l [rv<] ROWADDOUT_r [rv<] ROWADDOUT_i [rv<] ROWADDOUT_M [rv<] ROWADDOUT_t [rv<] ROWADDOUT_x [rv<] TSOUT_l [rv<] TSOUT_r [rv<] TSOUT_i [rv<] TSOUT_M [rv<] TSOUT_t [rv<] TSOUT_x [rv<] TSOUT_u [rv<] TSOUT_k [rv<] COADDOUT_x [rv<] COADDOUT_t [rv<] COADDOUT_M [rv<] MM Mt Mx Mu Mk Mj M< tl tr ti tm tt tx tu tk tj t< xl xr xi xm PCCjt_SOCET_PART [rvivmvtvkvjv<] [rvivtvxvuvj] VDDArgjV [rvivmvtvkvjv<] [rvivtvxvuvj] VDDArgjV [rvivmvtvkvjv<] [rvivtvxvuvj] VDDArgjV [rvivmvtvkvjv<] [rvivtvxvuvj] VDDArgjV [rvivtvxvuvj] VDDArgjV [rvivmvtvkvjv<] [rv<] SOUT_D [rv<] SOUT_C [rv<] SI [rv<] C_D [rv<] C_C [rv<] D_C [rvivmvtvkvjv<] [rvivtvxvuvj] VDDArgjV [rvivmvtvkvjv<] [rvivtvxvuvj] VDDArgjV VDDA VSSA Figure C.1: Bonding diagram for the MuPix4 chip (bonding on a carrier), extra power and ground wires are dashed. 94

105 VpComp VCasc In vssa vdda gnda DPWell SWell Drain PMOS Gate PMOS VDD Pixel Gnd Pixel Gnd Pixel r Gate mosl Drain mosl Out l Out r Gate mosr Drain mosr DPWell r sub sub strate- strate- sub strate- gnd- Vdd- gnd- gnd- Vdd- Vdd- substrate Vdd- gnd- sub Vdd- gnd- sub strate- strate- Gnd- Vdd- Vdd- Gnd- Vdd- Gnd- Vdd- Gnd- Vdd- Gnd- Vdd Gnd- Vdd- Gnd- Gnd- Vdd- Gnd- Vdd- Gnd- Vdd- VDDAldjV[lnrntnxnunj] [lnrnintnknjn<] SUBSTRATE [lnrnt] VDDAldjV [lnrntnxnunj] [lnrnintnknjn<] SUBSTRATE [lnrnt] VDDAldjV[lnrntnxnunj] lrj lrk lru lrx lrt lri lrr lrl lre ll< llj llk llu llx llt lli llr lll lle le< lej lek leu lex let lei ler lel lee Ul [lnrntnxnunj] VDDAldjV [lnrnintnknjn<] [lnrntnxnunj] VDDAldjV [lnrnintnknjn<] [lnrntnxnunj] VDDAldjV [lnrnintnknjn<] [lnrntnxnunj] VDDAldjV [lnrnintnknjn<] [rn<] [rn<] [rn<] [rn<] [rn<] [rn<] [rn<] [rn<] [rn<] [rn<] [rn<] [rnjn<] [rn<] [rn<] [lnrntnxnunj] VDDAldjV [lnrnintnknjn<] [lnrntnxnunj] VDDAldjV [lnrnintnknjn<] [lnrntnxnunj] VDDAldjV [lnrnintnknjn<] [lnrntnxnunj] VDDAldjV [lnrnintnknjn<] [lnrntnxnunj] VDDAldjV [lnrnintnknjn<] COADDOUT_r COADDOUT_l COADDOUT_e DPIX TSI_k TSI_u TSI_x TSI_t TSI_i TSI_r TSI_l TSI_e DCO RDCO l r i t x u k j < le ll lr li lt lx lu lk lj l< re rl rr ri rt rx ru rk rj r< ie il ir ii it ix << <j <k <u <x <t <i <r <l <e j< jj jk ju jx jt ji jr jl je k< kj kk ku kx kt ki kr kl ke u< uj uk uu ux [lnrnintnknjn<] ROWADDOUT_e [rn<] ROWADDOUT_l [rn<] ROWADDOUT_r [rn<] ROWADDOUT_i [rn<] ROWADDOUT_t [rn<] ROWADDOUT_x [rn<] TSOUT_e [rn<] TSOUT_l [rn<] TSOUT_r [rn<] TSOUT_i [rn<] TSOUT_t [rn<] TSOUT_x [rn<] TSOUT_u [rn<] TSOUT_k [rn<] COADDOUT_x [rn<] COADDOUT_t [rn<] COADDOUT_i [rn<] iu ik ij i< te tl tr ti tt tx tu tk tj t< xe xl xr xi xt xx xu xk xj x< ue ul ur ui ut MUPIXi_PART [rn<] [rn<] [rn<] [rn<] [rn<] A [rntnxnunj] [rn<] SOUT_D SOUT_C SI C_D C_C D_C VSSA [lnrntnj] VCASC [rnunj] VPBIASDAC [rnunj] B [rnunj] TH [rnxnj] HBVDD [rnj] SUBSTRATE [lnrnt] VDE [rnu] VPDE [rnu] IJECTl [rnxnj] IJECTr [rnxnj] VSSA [lnrntnj] [lnrnintnknjn<] VDDAldjV[lnrntnxnunj] VDDAldjV[lnrntnxnunj] [lnrnintnknjn<] SUBSTRATE [lnrnt] VDDAldjV[lnrntnxnunj] [lnrnintnknjn<] SUBSTRATE [lnrnt] vr [rn<] [rnjn<] [rn<] PU_DOW HB PRIOUT IBM Ck SIn Inj Test.Pixel.v.Do.ot.Connect vdda gnda vssa VCasc VPBias B Th VDD asubv VDel VPDel Injectl Injectr vssa gnda vdda DAC RAM strate ColAddr RowAddr Outbr Outbe ColAddr RowAddr Outbl Outbl ColAddr RowAddr Outbe Outbr dpix RowAdrr Outbi TSInbk RowAddr Outbt TSInbu RowAddr Outbx TSInbx TSOut be TSInbt TSOut bl TSInbi TSOut br TSInbr TSOut bi TSInbl TSOut bt TSInbe TSOut bx dcol TSOut bu RdCol- TSOut bk PullD ColAddr Outbx HB ColAddr Outbt PriOut ColAddr Outbi gnd vdd vdd gnd SoutD SoutC SIn CkD CkC dc MUPIX.t VDDAldjV [lnrntnxnunj] [lnrnintnknjn<] VDDAldjV [lnrntnxnunj] [lnrnintnknjn<] VDDAldjV [lnrntnxnunj] [lnrnintnknjn<] VDDAldjV [lnrntnxnunj] [lnrnintnknjn<] VDDAldjV [lnrntnxnunj] [lnrnintnknjn<] VDDAldjV [lnrntnxnunj] [lnrnintnknjn<] VDDAldjV [lnrntnxnunj] [lnrnintnknjn<] VDDAldjV [lnrntnxnunj] [lnrnintnknjn<] VDDAldjV [lnrntnxnunj] [lnrnintnknjn<] [lnrntnxnunj] [lnrnintnknjn<] [lnrntnxnunj] [lnrnintnknjn<] [lnrntnxnunj] [lnrnintnknjn<] [lnrntnxnunj] [lnrntnxnunj] [lnrnintnknjn<] [lnrnintnknjn<] [lnrntnxnunj] [lnrnintnknjn<] [lnrntnxnunj] [lnrnintnknjn<] [lnrntnxnunj] VDDAldjV VDDAldjV VDDAldjV VDDAldjV VDDAldjV VDDAldjV VDDAldjV VDDAldjV APDreli Do.not.connect Figure C.2: Bonding diagram for the MuPix4 chip (bonding directly on a PCB), extra power and ground wires are dashed. 95

106

107 D Graphical User Interface of the Configuration and Data Readout Software The configuration and the data readout of the MuPix3 and MuPix4 chip is controlled by a programm written in C++. A screenshot of the graphical user interface can be seen in figure D.1. It is divided into several boxes: Board DACs The value of the threshold and of the two injections can be set. Chip DACs The values of the internal chip voltages can be set. Pixel Configuration Only the button Write Pixel Values is used for the MuPix4 chip. This sets the pixel which should be read out in the ToT mode. The pixel has to selected by clicking in the hit map before. Pixel avigation With the buttons up, down, left and right the pixel that should be read out in the ToT mode is changed. Injections The length of the two injection signals can be set and the signals can be injected to the chip by clicking the buttons. Pulse Shape By clicking the button an automatic pulse shape measurement is done. Readout The readout of the hit-flag mode can be started by clicking the Start Readout button. S curve Automatic S-curve measurements, where the threshold is changed in small steps, can be started here by clicking the Measure S-curve button. It can be chosen 97

108 which injection should be used by clicking the two check boxes Injection1 and / or Injection2. The numbers that are inserted into the HV or Temp text box will be in the name of the saved file. If all is selected, a S-curve measurement in the hit-flag mode will start, in which the number of hits which registered a hit are counted. If single is selected, a measurement in the hit-flag mode will start, in which 100 injection signals are generated and for every pixel the registered hits are counted. If one single is selected, the same measurement will be done but only for one previous selected pixel. If noise (ToT) is selected, a S-curve measurement in the ToT mode for a previous selected pixel will start, in which no injection signals are generated and the S-curve of the baseline is measured. If one single (ToT) is selected, a measurement in the ToT mode for a previously selected pixel will start, in which 100 injection signals are generated and for the selected pixel the registered hits are counted. If one single (ToT, Inj) is selected, a S-curve measurement in the ToT mode will start similar to the previous one, but the threshold will be kept constant and the hight of the injection signals will change in small steps. This option does not work yet. Drawmode or every 1000 th event. It can be chosen if no readout event should be drawn or every, every 10 th Eudaq set here. Settings required while measuring with the EUDET telescope at DESY can be 98

109 Figure D.1: Screenshot of the graphical user interface of the configuration and readout software of the MuPix4. 99

110

111 E Mechanical Adapter for the Rotation Stage at the Telescope at DESY A mechanical adapter for the rotation stage at the DESY telescope at the testbeam area T22 to mount the MuPix2 PCB was made (see figure E.2). The small board is needed so that the big board can rotate without getting stuck at the rotation stage (figure E.1). Hence, the big one is mounted on top of the small one as seen in figure 8.2. The big board has holes for immersed screws so that the MuPix PCBs do not touch the screws. The adapter is designed such that the chip is on top of the rotation axis of the rotation stage. There are holes for M5 and M4 screws in the upright part of the big board. The M5 holes are for the MuPix2 PCB and the M4 holes are for the MuPix3 and MuPix4 PCBs. Figure E.1: Picture of the mechanical adapter to mount the MuPix PCBs on the rotation stage at the testbeam area T22 at DESY. 101