Advanced Techniques for Power, Energy, and Thermal Management for Clustered Manycores

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1 Advanced Techniques for Power, Energy, and Thermal Management for Clustered Manycores

2 Santiago Pagani Jian-Jia Chen Muhammad Shafique Jörg Henkel Advanced Techniques for Power, Energy, and Thermal Management for Clustered Manycores 123

3 Santiago Pagani ARM Cambridge UK Jian-Jia Chen Technical University of Dortmund Dortmund, North Rhine-Westphalia Germany Muhammad Shafique Vienna University of Technology Vienna Austria Jörg Henkel Karlsruhe Institute of Technology Karlsruhe, Baden-Württemberg Germany ISBN ISBN (ebook) Library of Congress Control Number: Springer International Publishing AG, part of Springer Nature 2018 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. Printed on acid-free paper This Springer imprint is published by the registered company Springer International Publishing AG part of Springer Nature The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

4 Preface Efficient and effective system-level power, energy, and thermal management are very important issues in modern computing systems, e.g., to reduce the packaging cost, to prolong the battery lifetime of embedded systems, or to avoid the chip from possible overheating. These are some of the main motivations why computing systems have shifted from single-core to multicore/manycore platforms, mainly to balance the power consumption and computation performance. Furthermore, clustered architectures with multiple voltage islands, where the voltage on a cluster can change independently and all cores in a cluster share the same supply voltage at any given time, are an expected compromise between global and per-core Dynamic Voltage and Frequency Scaling (DVFS) for modern manycore systems. In this book, we focus on two of the most relevant problems for such architectures, particularly, optimizing performance under power/thermal constraints and minimizing energy under performance constraints. For performance optimization, we first present a novel thermal-aware power budgeting concept, called Thermal Safe Power (TSP), which is an abstraction that provides safe power and power density constraints as a function of the number of active cores. TSP conceptually changes the typical design that uses a single and constant value as power budget, e.g., the Thermal Design Power (TDP), and can also serve as a fundamental tool for guiding task partitioning and core mapping decisions. Second, we show that runtime decisions normally used to optimize resource usages (e.g., task migration, power gating, DVFS, etc.) can result in transient temperatures much higher than the normally considered steady-state scenarios. In order to be thermally safe, it is important to evaluate the transient peaks before making resource management decisions. To this end, we present a lightweight method for computing these transient peaks, called MatEx, based on analytically solving the system of thermal differential equations by using matrix exponentials and linear algebra, instead of using regular numerical methods. Third, we present an effective and lightweight runtime boosting technique based on transient temperature estimation, called seboost. Traditional boosting techniques select the boosting levels (for boosted cores) and the throttle-down levels (for non-boosted cores) arbitrarily or through step-wise control approaches, and might v

5 vi Preface result in unnecessary performance losses for the non-boosted cores or may fail to satisfy the required runtime performance surges. Contrarily, seboost relies on MatEx to select the boosting levels, and hence it guarantees meeting the required runtime performance surges, while maximizing the boosting time with minimum performance losses for the non-boosted cores. In regards to energy minimization, we first focus on a single cluster, and we propose to use the Double Largest Task First (DLTF) strategy for partitioning tasks to cores based on load balancing and idle energy reduction, combined with either the Single Frequency Approximation (SFA) scheme or the Single Voltage Approximation (SVA) scheme for deciding the DVFS levels for execution. Furthermore, we provide thorough theoretical analysis of both solutions, in terms of energy efficiency and peak power reduction, against the optimal task partitioning and optimal DVFS schedule, particularly for the state-of-the-art designs, that have a limited number of cores inside each cluster. In SFA, all the cores in a cluster run at a single voltage and frequency, such that all tasks meet their performance constraints. In SVA, all the cores in a cluster also run at the same single voltage as in SFA; however, the frequency of each core is individually chosen, such that the tasks in each core can meet their performance constraints, but without running at unnecessarily high frequencies. Finally, we extend our analysis for systems with multiple clusters, and present two task-to-core mapping solutions when using SFA on individual clusters, particularly, a dynamic programming algorithm that derives optimal solutions for homogeneous manycores, and a lightweight and efficient heuristic for heterogeneous manycores. Related Publications This book is based on the results published in several conferences, journals, workshops, and book chapters, particularly: [61] Pagani, S., Chen, J.J.: Energy efficiency analysis for the single frequency approximation (SFA) scheme. In: Proceedings of the 19th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp (2013). doi: /rtcsa [Best Paper Award]. [62] Pagani, S., Chen, J.J.: Energy efficient task partitioning based on the single frequency approximation scheme. In: Proceedings of the 34th IEEE Real-Time Systems Symposium (RTSS), pp (2013). doi: /rtss [70] Pagani, S., Khdr, H., Munawar, W., Chen, J.J., Shafique, M., Li, M., Henkel, J.: TSP: Thermal Safe Power - Efficient power budgeting for manycore systems in dark silicon. In: Proceedings of the 9th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES +ISSS), pp. 10:1 10:10 (2014). doi: / [Best Paper Award].

6 Preface vii [63] Pagani, S., Chen, J.J.: Energy efficiency analysis for the single frequency approximation (SFA) scheme. ACM Transactions on Embedded Computing Systems (TECS) 13(5s), 158:1 158:25 (2014). doi: / [66] Pagani, S., Chen, J.J., Shafique, M., Henkel, J.: MatEx: Efficient transient and peak temperature computation for compact thermal models. In: Proceedings of the 18th Design, Automation and Test in Europe (DATE), pp (2015). doi: /date [65] Pagani, S., Chen, J.J., Li, M.: Energy efficiency on multi-core architectures with multiple voltage islands. IEEE Transactions on Parallel and Distributed Systems (TPDS) 26(6), (2015). doi: /tpds [64] Pagani, S., Chen, J.J., Henkel, J.: Energy and peak power efficiency analysis for the single voltage approximation (SVA) scheme. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34(9), (2015). doi: /tcad [72] Pagani, S., Shafique, M., Khdr, H., Chen, J.J., Henkel, J.: seboost: Selective boosting for heterogeneous manycores. In: Proceedings of the 10th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp (2015). doi: /codesisss [67] Pagani, S., Chen, J.J., Shafique, M., Henkel, J.: Thermal-aware power budgeting for dark silicon chips. In: Proceedings of the 2nd Workshop on Low-Power Dependable Computing (LPDC) at the International Green and Sustainable Computing Conference (IGSC) (2015). [69] Pagani, S., Khdr, H., Chen, J.J., Shafique, M., Li, M., Henkel, J.: Thermal Safe Power (TSP): Efficient power budgeting for heterogeneous manycore systems in dark silicon. IEEE Transactions on Computers (TC) 66(1), (2017). doi: /tc [Feature Paper of the Month]. [71] Pagani, S., Pathania, A., Shafique, M., Chen, J.J., Henkel, J.: Energy efficiency for clustered heterogeneous multicores. IEEE Transactions on Parallel and Distributed Systems (TPDS) 28(5), (2017). doi: /tpds [68] Pagani, S., Khdr, H., Chen, J.J., Shafique, M., Li, M., Henkel, J.: Thermal Safe Power: Efficient thermal-aware power budgeting for manycore systems in dark silicon. In: A.M. Rahmani, P. Liljeberg, A. Hemani, A. Jantsch, H. Tenhunen (eds.) The Dark Side of Silicon. Springer (2017). [60] Pagani, S.: Power, energy, and thermal management for clustered manycores. Ph.D. thesis, Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany (2016). [Received Summa cum Laude and the ACM SIGBED Paul Caspi Memorial Dissertation Award].

7 viii Preface Acknowledgements This work was partly supported by the German Research Foundation (DFG) as part of the Transregional Collaborative Research Centre Invasive Computing [SFB/TR 89], by Baden Württemberg MWK Juniorprofessoren-Programms, and by a grant from the Research Grants Council of the Hong Kong Special Administrative Region, China [Project CityU ]. Cambridge, UK Dortmund, Germany Vienna, Austria Karlsruhe, Germany Santiago Pagani Jian-Jia Chen Muhammad Shafique Jörg Henkel

8 Contents 1 Introduction Optimization Goals and Constraints Computational Performance Power and Energy Consumption Temperature Optimization Knobs Core Heterogeneity Task-to-Core Assignment/Mapping Dynamic Power Management (DPM) Dynamic Voltage and Frequency Scaling (DVFS) Performance Optimization Under Power or Thermal Constraints Energy Minimization Under Performance Constraints Summary of the State-of-the-Art, Problems, and Challenges Book Contributions Performance Optimization Under Power and Thermal Constraints Energy Minimization Under Real-Time/Performance Constraints Book Outline Orientation Within Funding Projects Invasive Computing Power Management for Multicore Architecture with Voltage Islands References ix

9 x Contents 2 Background and Related Work Performance Optimization Under Power or Thermal Constraints Techniques Using Per-chip Power Constraints Techniques Using Thermal Constraints Temperature Estimation Energy Minimization Under Real-Time/Performance Constraints Per-core DVFS Techniques Global DVFS Techniques Clustered Manycores / Multiple Voltage Islands References System Model Application Model Hardware Model Power Model Energy Model Thermal Model References Experimental Framework Setup Detailed Mode Setup High-Level Mode Setup Architectures Homogeneous Architectures Heterogeneous Architectures Benchmarks References Thermal Safe Power (TSP) Overview Motivational Example Problem Definition Thermal Safe Power for Homogeneous Systems Given Core Mapping on Homogeneous Systems Worst-Case Mappings on Homogeneous Systems Thermal Safe Power for Heterogeneous Systems Given Core Mapping on Heterogeneous Systems Worst-Case Mappings on Heterogeneous Systems Transient-State Considerations Adjusting the Temperature for Computing TSP Nominal DVFS Operation for a Given Mapping... 81

10 Contents xi 5.5 Experimental Evaluations for Homogeneous Systems Power Constraints Execution Time of Online TSP Computation Dark Silicon Estimations Performance Simulations Experimental Evaluations for Heterogeneous Systems Power Constraints Performance Simulations Summary References Transient and Peak Temperature Computation Based on Matrix Exponentials (MatEx) Overview Motivational Example Problem Definition Computing All Transient Temperatures Computing Peaks in Transient Temperatures Experimental Evaluations Setup Results Summary References Selective Boosting for Multicore Systems (seboost) Overview Motivational Example Problem Definition Given Required Boosting Levels Unknown Required Boosting Levels Unknown Maximum Expected Boosting Time Concurrency and Closed-Loop Control-Based Boosting Experimental Evaluations Results Summary References Energy and Peak Power Efficiency Analysis for Simple Approximation Schemes Overview Problem Definition Largest Task First (LTF) Scheme Double Largest Task First (DLTF) Scheme

11 xii Contents Single Frequency Approximation (SFA) Scheme Single Voltage Approximation (SVA) Scheme Lower Bounds Lower Bound for the Energy Consumption Lower Bound for the Peak Power Consumption Approximation Factor Analysis: DLTF-SFA Energy Minimization Analysis for DLTF-SFA Peak Power Reduction Analysis for DLTF-SFA Approximation Factor Analysis: DLTF-SVA Energy Minimization Analysis for DLTF-SVA Peak Power Reduction Analysis for DLTF-SVA Comparing DLTF-SFA and DLTF-SVA Discrete Voltage and Frequency Pairs Experimental Evaluations Setup Results Summary References Energy-Efficient Task-to-Core Assignment for Homogeneous Clustered Manycores Overview Problem Definition Simple Heuristic Algorithms Description of Simple Heuristic Algorithms Approximation Factor for Simple Heuristics Numerical Examples for the Approximation Factor of Simple Heuristics Assignment Properties Given Highest Cycle Utilization Task Sets Assigned to Every Cluster All Possible Highest Cycle Utilization Task Sets Dynamic Programming Solution Description of the DYVIA Algorithm Complexity Analysis for the DYVIA Algorithm Optimal Task Set Assignment Under SFA Versus Optimal DVFS Experimental Evaluations on SCC Setup Measurement Errors Results

12 Contents xiii 9.6 Additional Experimental Evaluations Setup Results Summary References Energy-Efficient Task-to-Core Assignment for Heterogeneous Clustered Manycores Overview Motivational Example Problem Definition Assignment of Given Task Sets Example Special Case: Tasks Consume Equal Average Power on a Given Core and Voltage/Frequency Special Task Partitioning for Fixed Frequencies Potential DVFS Configurations for all Clusters in the Special Case General Case: Different Tasks Consume Different Average Power on the Same Core General Task Partitioning for Fixed Frequencies Potential DVFS Configurations for all Clusters in the General Case Experimental Evaluations Setup Results Summary References Conclusions Book Summary Current Impact of Our Contributions Future Works References Index

13 About the Authors Santiago Pagani is currently a Staff Firmware Engineer and Team Lead at ARM Ltd. (Cambridge, UK), where he runs an Agile firmware development team working on key components for the next-generation Mali GPU products. He received his Diploma in Electronics Engineering from the National Technological University (UTN), Argentina, in He received his Ph.D. in Computer Science from the Karlsruhe Institute of Technology (KIT) with Summa cum Laude in From 2003 until 2012, he worked as a hardware and software developer in the industry sector for several companies in Argentina, including 2 years as a technical group leader. From 2012 until 2017, he worked as a research scientist (doctoral researcher and later postdoc) as part of the research staff at KIT. He received two Best Paper Awards (IEEE RTCSA in 2013 and IEEE/ACM CODES+ISSS in 2014), one Feature Paper of the Month (IEEE Transactions on Computers in 2017), and three HiPEAC Paper Awards. He received the 2017 ACM SIGBED Paul Caspi Memorial Dissertation Award in recognition of an outstanding Ph.D. dissertation. His interests include embedded systems, real-time systems, energy-efficient scheduling, temperature-aware scheduling, and power-aware designs. xv

14 xvi About the Authors Jian-Jia Chen is a Professor of Computer Science at TU Dortmund, Germany. Prior to taking up his current position, he was with the Department of Informatics at Karlsruhe Institute of Technology (KIT) in Germany as a Junior Professor for Institute for Process Control and Robotics (IPR). He received his B.S. degree from the Department of Chemistry at National Taiwan University He obtained his Ph.D degree in June 2006 with Ph.D Dissertation Energy-Efficient Scheduling for Real-Time Tasks in Uniprocessor and Homogeneous Multiprocessor Systems. Between January 2008 and April 2010, he was a Postdoc Researcher at Computer Engineering and Networks Laboratory (TIK) in Swiss Federal Institute of Technology (ETH) Zurich, Switzerland. His research interests include real-time systems, embedded systems, energy-efficient and power-aware designs, reliability system designs, and design automation. He has published more than 175 research papers in prestigious journals and conferences in the areas of real-time embedded systems, lower power system designs, and distributed computing. He has served as TPC member in several international conferences in real-time and embedded systems such as RTSS, RTAS, RTCSA, DATE, ICCAD, etc., and associate editors and guest editors in international journals. Muhammad Shafique (M 11, SM 16) is a Full Professor at the Institute of Computer Engineering, Department of Informatics, Vienna University of Technology (TU Wien), Austria. He is directing the Group on Computer Architecture and Robust, Energy-Efficient Technologies (CARE-Tech). He was a Senior Research Group Leader at Karlsruhe Institute of Technology (KIT), Germany for more than 5 years. He received his Ph.D. in Computer Science from KIT in January Before, he was with Streaming Networks Pvt. Ltd. where he was involved in research and development of advanced video coding systems for several years. His research interests are in computer architecture, power- and energy-efficient systems, robust computing covering various aspects of dependability and fault-tolerance, hardware security, emerging computing trends like neuromorphic and approximate

15 About the Authors xvii computing, neurosciences, emerging technologies and nanosystems, self-learning and intelligent/cognitive systems, FPGAs, MPSoCs, and embedded systems. His research has a special focus on cross-layer analysis, modeling, design, and optimization of computing and memory systems covering various layers of the hardware and software stacks, as well as their integration in application use cases from Internet-of-Things (IoT), Cyber-Physical Systems (CPS), and ICT for Development (ICT4D) domains. He received the prestigious 2015 ACM/SIGDA Outstanding New Faculty Award, six gold medals in educational career, and several best paper awards and nominations at prestigious conferences like DATE, DAC, ICCAD, and CODES+ISSS, Best Master Thesis Award, and Best Lecturer Award. He has given several Invited Talks, Tutorials, and Keynotes. He has also organized many special sessions at premier venues (like DAC, ICCAD, DATE, and ESWeek) and served as the Guest Editor for IEEE Design and Test Magazine (D&T) and IEEE Transactions on Sustainable Computing (T-SUSC). He has served as the TPC Co-Chair of ESTIMedia and LPDC, General Chair of ESTIMedia, and Track Chair at DATE and FDL. He has served on the program committees of several IEEE/ACM conferences like ICCAD, ISCA, DATE, CASES, FPL, and ASPDAC. He is a Senior Member of the IEEE and IEEE Signal Processing Society (SPS), and a member of ACM, SIGARCH, SIGDA, SIGBED, and HiPEAC. He holds one US patent and over 180 papers in premier journals and conferences. Professor Jörg Henkel is with Karlsruhe Institute of Technology (KIT), Germany, where he is directing the Chair for Embedded Systems CES. Before, he was a Senior Research Staff Member at NEC Laboratories in Princeton, NJ. He received his Ph.D. from Braunschweig University with Summa cum Laude. He has/is organizing various embedded systems and low-power ACM/IEEE conferences/symposia as General Chair and Program Chair and was a Guest Editor on these topics in various journals like the IEEE Computer Magazine. He was Program Chair of CODES 01, RSP 02, ISLPED 06, SIPS 08, CASES 09, Estimedia 11, VLSI Design 12, ICCAD 12, PATMOS 13, NOCS 14 and served as

16 xviii About the Authors General Chair for CODES 02, ISLPED 09, Estimedia 12, ICCAD 13 and ESWeek 16. He is/has been a steering committee member of major conferences in the embedded systems field like at ICCAD, ESWeek, ISLPED, Codes+ISSS, CASES, and is/has been an editorial board member of various journals like the IEEE TVLSI, IEEE TCAD, IEEE TMSCS, ACM TCPS, JOLPE, etc. In recent years, he has given more than ten keynotes at various international conferences primarily with focus on embedded systems dependability. He has given full/half-day tutorials at leading conferences like DAC, ICCAD, DATE, etc. He received the 2008 DATE Best Paper Award, the 2009 IEEE/ACM William J. McCalla ICCAD Best Paper Award, the Codes+ISSS 2015, 2014, and 2011 Best Paper Awards, and the MaXentric Technologies AHS 2011 Best Paper Award as well as the DATE 2013 Best IP Award and the DAC 2014 Designer Track Best Poster Award. He is the Chairman of the IEEE Computer Society, Germany Section, and was the Editor-in-Chief of the ACM Transactions on Embedded Computing Systems (ACM TECS) for two consecutive terms. He is an initiator and the coordinator of the German Research Foundation s (DFG) program on Dependable Embedded Systems (SPP 1500). He is the site coordinator (Karlsruhe site) of the Three-University Collaborative Research Center on Invasive Computing (DFG TR89). He is the Editorin-Chief of the IEEE Design & Test Magazine. He holds ten US patents and is a Fellow of the IEEE.

17 Acronyms ADI Alternating Direction Implicit, 26 ARMA Autoregressive Moving Average, 28 blackscholes Application from the PARSEC benchmark suite, 3, 4, 28, 40, 83, 89, , 216, 233 bodytrack Application from the PARSEC benchmark suite, 3, 4, 28, 40, 83, 89, 113, 171, 216, 233 BUH Balanced Utilization Heuristic, 183, 184, , 200 CBGA Ceramic Ball Grid Array,28,249 CCH Consecutive Cores Heuristic, , 202, 208,210 DLTF Double Largest Task First,131,137, 139, 178, 242 DLTF-SFA Double Largest Task First combined with Single Frequency DLTF-SVA Approximation, 133, 142, 146, Double Largest Task First combined with Single Voltage Approximation, 132, 133, 142, 143, 146, 154, , DPM Dynamic Power Management, 11, 12, 16 19, 59, 77, 88, 91, 93, 102, , , 154, 160, 162, 166, , 209, 210, 213, 215, 241 DTM Dynamic Thermal Management, 6, 52, 53, 59 64, 68 DVFS Dynamic Voltage and Frequency Scaling, v, vi, xv, xvi, xvii, 8, 159, , , 179, , 196, 198, 202, 203, 210, 211, 213, 214, , 238, DYVIA Dynamic Voltage Island Assignment, 181, 183, 184, , , , 242, 244 EDF Earliest Deadline First, 36, 37, 137, 146, 178, 244 EOH Extremal Optimization Heuristic, 28, 30, 182, 182, 186, 188, 199, 203, 207, 209, 244 EWFD Equally-Worst-Fit-Decreasing, 29, 31, 228, 229, 230, 232, 233, 235 EXU Execution Unit, 38, 39 FEA Finite Element Analysis, 28, 38, 39 ferret Application from the PARSEC benchmark suite, 28 xix

18 xx Acronyms FFI-LTF Fixed Frequency Island-Aware Largest Task First, FFT Fast Fourier Transform, 203 FIT-LTF Fixed Frequency Island- and Task-Aware Largest Task First, 225, 226 gem5 gem5 multicore simulator, 2, 5, 22, 25, 233, 234 GIPS Giga Instructions per Second, 26, 114, 118, GIT Generalized Integral Transforms, 28 HI-LTF Heterogeneous Island-Aware Largest Task First, 229, 231 HIT-LTF Heterogeneous Island- and Task-Aware Largest Task First, 232 HotSpot HotSpot modeling and temperature computation tool, 16, 27, 28, 48, 51, 60 IFU Instruction Fetch Unit, 38, 39 ILP Instruction-Level Parallelism, 2, 24, 25 IPC Instructions per Cycle, 2 IPS Instructions per Second, 2, 86 LPF Low-Power First, 232, 235, 238 LPT Longest Processing Time,132, 137, 138 LSU Load and Store Unit, 38, 39 LTF Largest Task First, 14, 17, 29, 30, 131, 133, 137, 144, 145 LTR Left to Right, 154, 157, 162, 163 MatEx (From Matrix Exponentials) Transient and Peak Temperature Computation Tool for Compact Thermal Models, xxvi, 3, 16, 18, 74, 76, 89, 90, 92, 96, , , 112, 114, 118, 117, 122, 123 McPAT McPAT power consumption simulator, 3, 20, 25, 32, 41, NoC Network on Chip, 2, 52, 243 Odroid-XU3 Odroid-XU3 mobile platform, with an Exynos 5 Octa (5422) chip based on ARM s big.little architecture, 52, 56, 89, 124, 233 OOO Out-of-Order, 38, 55, 56, 89 PARSEC PARSEC benchmark suite,2, 4, 20, 25, 41, 172, 216, 218, 234 QoS Quality of Service, 31 SCC Single Chip Cloud computer, 9, 55, 182, 184, seboost Selective Boosting for Manycore Systems, 16, 18, 111, 112, 117, 118, 120, 124 SFA Single Frequency Approximation, 14, 16, 30, 132 SVA Single Voltage Approximation, vi, 17, 18, 132, 142 swaptions Application from the PARSEC benchmark suite, 3, 4, 28, 40, 83, 89, 113, 171, 216, 233, 234 TDP Thermal Design Power, v, 5, 13, 14, 24, 31, 74, 111, 241 TLP Thread-Level Parallelism, 2, 24 TSP Thermal Safe Power, v, vii, 14, 15, 111, 241, 243 VLSI Very Large-Scale Integration, 9, 27 x264 Application from the PARSEC benchmark suite, 41, 83, 89, 113

19 Symbols A a i;j DVFS ¼ SFA AFASG ¼ ANY energy overheads AFDLTF-SFA AF energy DLTFSFA peak power AFDLTFSFA Matrix A ¼[a i;j NN that contains the thermal capacitance values of an RC thermal network (generally a diagonal matrix, since thermal capacitances are modeled to ground), 47, 48, 52, 96, 104 Element in row i and column j inside the thermal capacitance matrix A, such that 1 i N and 1 j N, 47 Approximation factor for any task partition mapping heuristic M that uses K clusters with non-empty task sets, when using SFA to decide the DVFS levels on individual clusters, against the optimal assignment that also uses SFA in individual clusters, Approximation factor (i.e., the worst-case behavior) of DLTF-SFA for energy minimization in relation to the optimal task partitioning and optimal DVFS solution for energy minimization (i.e., the task partitioning and DVFS solution that result in the minimum energy consumption) when we consider negligible overheads for sleeping, , 159, 169 Approximation factor (i.e., the worst-case behavior) of DLTF-SFA for energy minimization in relation to the optimal task partitioning and optimal DVFS solution for energy minimization (i.e., the task partitioning and DVFS solution that result in the minimum energy consumption), 133, 134, , 174 Approximation factor (i.e., the worst-case behavior) of DLTF-SFA for peak power reduction in relation to the optimal task partitioning and optimal DVFS solution for peak power reduction (i.e., the task partitioning and DVFS solution that result in the minimum peak power consumption), 133, 134, xxi

20 xxii Symbols AF energy DLTFSVA peak power AFDLTFSVA a area core area type B 1 Approximation factor (i.e., the worst-case behavior) of DLTF-SVA for energy minimization in relation to the optimal task partitioning and optimal DVFS solution for energy minimization (i.e., the task partitioning and DVFS solution that result in the minimum energy consumption), 128, 129, 159, 170 Approximation factor (i.e., the worst-case behavior) of DLTF-SVA for peak power reduction in relation to the optimal task partitioning and optimal DVFS solution for peak power reduction (i.e., the task partitioning and DVFS solution that result in the minimum peak power consumption), 41, 134 For the approximated power consumption on a CMOS core, a constant including the effective switching capacitance, the average activity factor of the core, and a scaling factor for the linear relationship between the voltage of the cluster and the highest frequency in the cluster (i.e., V dd / f cluster ), 38, 47, 48 m Area of core m (among all M in the chip), 38, q Area of a core of type q, 48 Matrix B 1 ¼ ~b i;j is the inverse of matrix B, 47 NN B Matrix B ¼ b i;j that contains the thermal conductance NN values between vertical and lateral neighboring thermal nodes of an RC thermal network, 47, 48 ~b i;j Element in row i and column j inside matrix B 1, such that 1 i N and 1 j N, 47 b i;j Element in row i and column j inside the thermal conductance matrix B, such that 1 i N and 1 j N, 47, 48 b For the approximated power consumption on a CMOS core, b f cluster 0 represents the leakage power consumption on the core, 41 C Matrix of an RC thermal network, such that C ¼A 1 B,47 D Hyper-period, i.e., the least common multiple among all periods of all R tasks, 36, 43, 143, , 184, d n Period and implicit deadline of task s n, 36, 53, 143, , d d max 152, 154, 184, , 192 Variable of auxiliary function UðdÞ, used to choose a value of f dyn such that E# becomes a continuous function, in order to derive an approximation factor without unnecessary pessimism, , 164, 165, , 264 Value of d that maximizes auxiliary function UðdÞ, used to choose a value of f dyn such that E# becomes a continuous function, in order to derive an approximation factor without unnecessary pessimism,

21 Symbols DYVIA ði; jþ DYVIA back trackingði; jþ DYVIA #combinations E core ð f Þ E core ð f cluster ; f Þ e Ct E DVFS¼optimal ASG¼DYVIA E DVFS¼optimal ASG¼optimal DVFS E DVFS¼SFA ASG¼DYVIA xxiii Dynamic programming function, where i is the index of the first task set to be considered in this sub-problem, and j is the index of the last task set to be considered in this sub-problem, such that function DYVIA ði; jþ returns the minimum energy consumption for the assignment of task sets S i ; S i þ 1 ;...; S j1 ; S j onto cores, using v ¼ ji þ 1 K clusters (from Corollary 9.1, j i þ 1 will always be an integer multiple of K), , 265 Backtracking table in which entry DYVIAback trackingði; jþ contains the task sets indexes f 1 ; 2 ;...; K g that resulted in the minimum energy consumption for sub-problem DYVIA ði; jþ, 196, 197, 194 Total number of combinations that algorithm DYVIA needs to evaluate when building its dynamic programming table, 200 Approximated energy consumption on a CMOS core for the case in which the core runs at the same frequency which determines the voltage of the cluster, where f is the execution frequency of the core, 42, 135, 145 Approximated energy consumption on a CMOS core for the general case of having voltage scaling at a cluster level and frequency scaling at a core level, where f cluster is the highest execution frequency among all cores in the cluster (thus setting the voltage of the cluster), and f is the execution frequency of the core, 44, 135, 145 Matrix exponential e Ct ¼½e Ct i;j NN, 96, 97 Total energy consumption when using an optimal DVFS algorithm to decide the DVFS levels on individual clusters, and when using DYVIA for assigning task sets to clusters (i.e., the optimal task set assignment solution under SFA), 201, 202 Total energy consumption when using an optimal DVFS algorithm to decide the DVFS levels on individual clusters, and when assigning task sets to clusters by using an algorithm that is optimal when using an optimal DVFS algorithm to decide the DVFS levels on individual clusters, 200, 201 Total energy consumption when using SFA to decide the DVFS levels on individual clusters, and when using DYVIA for assigning task sets to clusters (i.e., the optimal task set assignment solution under SFA), 200, 201

22 xxiv E DVFS¼SFA ASG¼optimal DVFS E j DVFS¼SFA ASG¼CCH E j DVFS¼percore ASG¼ANY E j DVFS¼SFA ASG¼ANY E j DVFS¼SFA ASG¼SFA e q;n EðLÞ E # E OPT ~E s n q F type q;j Symbols Total energy consumption when using SFA to decide the DVFS levels on individual clusters, and when assigning task sets to clusters by using an algorithm that is optimal when using an optimal DVFS algorithm to decide the DVFS levels on individual clusters, 187, 200, 201 Energy consumption of cluster I j when using the CCH task partition mapping algorithm to map task sets to cores and clusters, and when using SFA to decide the DVFS levels on individual clusters, 189 Energy consumption of cluster I j when using any task partition mapping algorithm to map task sets to cores and clusters, and when having per-core DVFS, which will result in the lower bound for the energy consumption since having per-core DVFS is the optimal solution and the task set assignment plays no role for such a case, 189, 190 Energy consumption of cluster I j when using any task partition mapping algorithm to map task sets to cores and clusters, and when using SFA to decide the DVFS levels on individual clusters, 189 Energy consumption of cluster I j when using SFA to decide the DVFS levels on individual clusters, and when using the optimal task set assignment solution under SFA, 189 Worst-case execution cycles of task s n when being executed on a core of type, 35, 43, 136, 140, 141, 143, , 229, 234 Energy consumption of the highest DVFS level cluster for each combination, which is similar to Eq. (9.1), but for set L instead of set L j, Lower bound for the optimal energy consumption for the optimal task partition and any feasible DVFS schedule during a hyper-period D, 135, 136, 149, , 160, 168, 170, 176, 179, 256, 266, 273 Optimal energy consumption for the optimal task partition and optimal DVFS schedule during a hyper-period D, 135, 136 Energy consumed during one hyper-period for executing task s n on a core of type q at frequency index j (such that 0 j ^F q type ) in case that all tasks consume equivalent power when executing at the same frequency on a core of type q, i.e., P s1 q F type q;j ¼ P s2 q F type q;j ¼¼P sr q F type q;j ¼ P q F type q;j, 220

23 Symbols ~E s g q E s n q E DLTF SFA E DLTF SVA g f cluster f crit s n q f critq f crit f max dyn F type q;j F type q;j xxv Energy consumed during one hyper-period for executing task set S g on a core of type q at frequency index j (such that 0 j ^F q type ) in case that all tasks consume equivalent power when executing at the same frequency on a core of type q i.e., P s1 q F type q;j ¼ P s2 q F type q;j ¼¼P sr q F type q;j ¼ P q F type q;j, 220 Energy consumed during one hyper-period for executing task s n on a core of type q at frequency index j (such that 0 j ^F q type ), 43, 217, 218 Total energy consumption during a hyper-period D for partitioning tasks with DLTF and selecting the DVFS schedule with SFA,136, 145, 156 Total energy consumption during a hyper-period D for partitioning tasks with DLTF and selecting the DVFS schedule with SVA, 136, 146, 147, 155 Amount of power consumed by a cluster for being in the active state (since there is no voltage regulator with 100% efficiency) when at least one core inside the cluster has to execute some workload, , , 207, 205, 210 For the approximated power consumption on a CMOS core, f cluster is the highest execution frequency among all cores in the cluster, and therefore determines the minimum voltage of the cluster for stable execution, 4, 42, 45, 46, 136, 137, 146 Critical frequency of task s n running on a core of type q that minimizes the energy consumption for execution when the overhead for entering/leaving a low-power mode can be considered negligible, 43, 218 Critical frequency on a core of type q in case that all tasks consume equivalent power when executing at the same frequency on a core of type q, i.e., P s1 q F type q;j ¼ P s2 q F type q;j ¼¼P sr q F type q;j ¼ P q F type q;j such that s f 1 crit q ¼ f crit s 2 q ¼¼f crit s R q ¼ f crit q, 220, 268, 272 Critical frequency for the energy model in Eq. (3.6) (focusing on homogeneous systems and assuming that all tasks have similar average activity factors) that minimizes the energy consumption for execution when the overhead for entering/leaving a low-power mode can be considered negligible, 45, , 140, 141, 143, , 155, 161, , 169, 170, 171, 172, 180 Maximum value of the auxiliary frequency used to obtain an analytical expression for the lower bound of the energy consumption which can be used for general cases, 154,

24 xxvi Symbols f dyn F core i;^f i core ^F i core F max F min F type q;^f q type ^F q type Auxiliary frequency used to obtain an analytical expression for the lower bound of the energy consumption which can be used for general cases, Maximum frequency for core i,38, 118 Number of available frequencies for core i, 38, 118 Maximum frequency when considering homogeneous systems,135, 146, 149, 164, 171, 174, 183 Minimum frequency when considering homogeneous systems, 1345, 174, 183 Maximum frequency for a core of type q, 31, 218 Number of available frequencies for cores of type q, 31, 38, 218 G Column vector G¼[g i ] N1 that contains the values of the thermal conductances between each thermal node and the ambient temperature of an RC thermal network, 47, 48 66, 92 C 1 Matrix C 1 ¼½~C i;j NN represents the inverse of matrix C, 96, 97 C Matrix C ¼½C i;j NN represents a matrix containing the eigenvectors of matrix C for a given thermal model, 96, 97 c For the approximated power consumption on a CMOS core, c [ 1 is a constant related to the hardware (in CMOS processors, c is generally modeled equal to 3), 96,97, H q H I max K K h i Auxiliary matrix H q ¼ h q q;i;j QZM type q, used to compute the maximum amount of heat that any m q cores of type q can contribute to the temperature on node i, for all core types q ¼ 1; 2;...; Q, Auxiliary matrix H ¼[h i;j ] ZM, used to compute the maximum amount of heat that any m cores can contribute to the steady-state temperature on thermal node i, Maximum chip current constraint for the entire chip that cannot be exceeded (e.g., from the capacity of the power supply or the wire thickness), 40, , 122 Set K ¼fk 1 ; k 2 ;...; k M g that contains all the indexes of the thermal nodes that correspond to cores (among all cores, ignoring the types of the cores), 49, 64, 70 Total number of cores inside every cluster/island, for a system in which all the clusters have equal number of cores per cluster/island, , , 230 K q n Set K q ¼ k q 1 ; kq 2 ;...; kq Mq type o for all core types q ¼ 1; 2;...; Q, that contains the indexes of the thermal nodes that correspond to cores of type q, 49,76

25 Symbols xxvii j For the approximated power consumption on a CMOS core, j 0 represents the independent power consumption attributed to maintaining the core in execution mode (i.e., the voltage- and frequency-independent part of the power consumption), 41, 42, 44, 45, 135, 143, 210 L Set L ¼ f 1 ; 2 ;...; Z g that includes all the indexes of the thermal nodes that correspond to blocks in the floorplan (as opposed to thermal nodes that represent the heat sink, internal nodes of the heat spreader, the thermal interface material, etc.), 49, 62, 63, 65, 66, 70, 74, 76, 115, 117, 121, 195 k Lagrange multiplier inside the Lagrangian used when applying the Kuhn Tucker conditions, L Lagrangian used when applying the Kuhn Tucker conditions, 147 L Set containing the indexes of the task sets assigned to a general cluster (as opposed to set L j,defined for the particular cluster I j ), such that 1 \ 2 \ \ K, with 0 auxiliary and less than 1, 195, 262, 264 L j Set containing the indexes of the task sets assigned to cluster I j such that j;1 \ j;2 \ \ j;k with j ¼ 1; 2;...; V, it holds that j;i 2½1; M, and j;i is unique for all j, i, 183, 185, 191, 193, 194, 264, 266 K ði; jþ Set that contains all possible L sets that satisfy Theorem 9.2, i.e., K ði; jþ stores all the potentially optimal combinations, such that 0 ¼ i 1; K ¼ j and h ¼ h1 þ 1 þ n K for 0\h\K with h \j and n 2 N 0, 195, K Diagonal matrix K ¼diag ðe k1t ; e k2t ;...; e knt, where k 1 ; k 2 ;...; k N are the eigenvalues of matrix C for a given thermal model, 47 M Total number of cores in the system, 37 42, 52, M H Total number of task sets in which some task partitioning algorithm partitions the tasks, 187, 190, 192, 208 M Total number of task sets in which we partition the tasks, 37 42, 184, 187 m Set m ¼ m 1 ; m 2 ;...; m Q that represents the number of active cores for core types f1; 2;...; Qg respectively, 63, 75 77, 83, 84 Mk cluster Total number of cores inside cluster/island k, 37, 217, 219, 223 M cluster max M 6¼0 Maximum number of cores inside a cluster among all clusters, i.e., Mmax cluster ¼ max 1 k V Mk cluster, 227, When partitioning tasks using DLTF, the resulting number of cores after regrouping with cycle utilization larger than 0, i.e., the cores that remain active, 142, 145, ,

26 xxviii Symbols Mq type Total number of cores of type q, 37, 39, 49, 175, 177 N Total number of thermal nodes in the RC thermal network, such that there are at least as many thermal nodes in the RC thermal network as blocks in the floorplan, i.e., N Z, 45 48, 117 X Auxiliary matrix X ¼ X i;j, used to speed up the NN computation of the transient temperatures in MatEx, , 104, 269 X k;i Element in row k and column i inside auxiliary matrix X, such that 1 k N and 1 i N, P Column vector P ¼½p i NN that contains the values of the power consumption on every node of an RC thermal network, 46, 48, P blocks Column vector P blocks ¼ p blocks i that represents the N1 power consumption on other blocks in the floorplan that do not correspond to cores (e.g., a block of an L2 cache), 48, 49, 63, 63, 75 P core ð f Þ Approximated average power consumption on a CMOS core for the case in which the core runs at the same frequency which determines the voltage of the cluster, where f is the execution frequency of the core, 41, 134, 135, 142, 174 P core ðf cluster ; f Þ Approximated average power consumption on a CMOS core for the general case of having voltage scaling at a cluster level and frequency scaling at a core level, where f cluster is the highest execution frequency among all cores in the cluster (thus setting the voltage of the cluster), and f is the execution frequency of the core, 41, 136, 137, 147 P core inactj Power consumption of core j (among all M in the chip) when the core is inactive (i.e., idle or in a low-power mode), 74, 77 P core inactm Power consumption of core m (among all M in the chip) when the core is inactive (i.e., idle or in a low-power mode), 39 P core inact P core q max ðmþ P core q max ðxþ Power consumption of an inactive core (i.e., idle or in a low-power mode) for the special case of homogeneous manycore systems, 40, 65 67, 70, 71, 78 Auxiliary function used to assist in deriving the amount of power density that any m ¼ m 1 ; m 2 ;...; m Q active cores are allowed to consume, such that the total power consumption precisely reaches the value of P max,77 Auxiliary function used to assist in deriving the amount of power density that the active cores in mapping X are allowed to consume, such that the total power consumption precisely reaches the value of P max, 74, 75

27 Symbols P core max ðmþ P cores P q equal P equal ^P # P max ^P OPT P q P s n q P rest ^P DLTF SFA F type q;j F type q;j Auxiliary function used to assist in deriving the amount of power that any m active cores are allowed to consume, such that the total power consumption precisely reaches the value of P max, 67, 72, 73 Column vector P cores ¼½p cores i N1 represents the power consumption on the cores, 48, 49 For a heterogeneous or homogeneous manycore system, power density on all active cores when we assume that all active cores have equal power density at a given point in time, 74, 76 For a homogeneous manycore system, power consumption of all active cores when we assume that all active cores are consuming equal power at a given point in time, 65, 66, 68, 70 72, 85 Lower bound for the optimal peak power consumption for the optimal task partition and any feasible DVFS schedule during a hyper-period D, 135, 136, 156, 165, 171, 176, 179 Maximum chip power constraint for the entire chip that cannot be exceeded (e.g., from the capacity of the power supply or the wire thickness), 40, 52, 64 67, 70 72, 74 77, , 123 Optimal peak power consumption for the optimal task partition and optimal DVFS schedule during a hyper-period D, 123, 135, 136 Average power consumption on a core of type q running at frequency index j (such that 0 j ^F q type ), in case that all tasks consume equivalent power when executing at the same frequency on a core of type q i.e., in case that P s 1 q P s 2 q F type q;j ¼¼P s R q F type q;j ¼ P q F type q;j such that s f 1 crit q ¼ f crit s 2 q ¼¼f crit s R q ¼ f crit q,218, 230 F type q;j Average power consumption on a core of type q when executing task s n when executing task j (such that 0 j ^F q type ), 39, 43, 218, 219, 230 xxix ¼ Column vector P rest ¼ ½p rest N1 that represents the power consumption of thermal nodes that are on the floorplan (e.g., internal thermal nodes of the heat sink), for which it holds that p rest i ¼ 0 for all i, 48, 49 Total peak power consumption for partitioning tasks with DLTF and selecting the DVFS schedule with SFA, 134, 137, 145, 165

28 xxx Symbols ^P DLTF SVA P q TSP ðxþ P TSP ðxþ P qh TSP ðxþ P H TSP ðxþ P q worst TSP P worst TSP Total peak power consumption for partitioning tasks with DLTF and selecting the DVFS schedule with SVA, 136, 147, 171 Per-core power density budget for each active core in the specified core mapping (independent of the type of core) that results in a maximum steady-state temperature among all cores which does not exceed the critical threshold temperature for triggering DTM, for heterogeneous or homogeneous manycore systems, 63, Per-core power budget for each active core in the specified core mapping that results in a maximum steady-state temperature among all cores which does not exceed the critical threshold temperature for triggering DTM, for homogeneous manycore systems, 62 64, 67, 68 Per-core power density budget for each active core in the specified core mapping (independent of the type of core) while ignoring P max that results in a maximum steady-state temperature among all cores which does not exceed the critical threshold temperature for triggering DTM, for heterogeneous or homogeneous manycore systems, 74, 75 Per-core power budget for each active core in the specified core mapping while ignoring P max that results in a maximum steady-state temperature among all cores which does not exceed the critical threshold temperature for triggering DTM, for homogeneous manycore systems, ðmþ Per-core power density budget (independent of the type of core) for each active core in any possible core mapping with m ¼ m 1 ; m 2 ;...; m Q active cores for core types f1; 2;...; Qg, respectively, that results in a maximum steady-state temperature among all cores which does not exceed the critical threshold temperature for triggering DTM, for heterogeneous or homogeneous manycore systems, 63, 75, 77 ðmþ Per-core power budget for each active core in any possible core mapping with m simultaneously active cores that results in a maximum steady-state temperature among all cores which does not exceed the critical threshold temperature for triggering DTM, for homogeneous manycore systems, 62, 67, 68, 70, 72, 73, 83, 84

29 Symbols xxxi P qhworst TSP P Hworst TSP P type inact q ðmþ Per-core power density budget (independent of the type of core) for each active core in any possible core mapping with m ¼ m 1 ; m 2 ;...; m Q active cores for core types f1; 2;...; Qg, respectively, that results in a maximum steady-state temperature among all cores which does not exceed the critical threshold temperature for triggering DTM while ignoring P max, for heterogeneous or homogeneous manycore systems, 76, 77 ðmþ Per-core power budget for each active core in any possible core mapping with m simultaneously active cores while ignoring P max that results in a maximum steady-state temperature among all cores which does not exceed the critical threshold temperature for triggering DTM, for homogeneous manycore systems, 71, 72, 73 Power consumption of a core of type q when the core is inactive (i.e., idle or in a low-power mode), 39, 76, 77, 218 Q Number of different types of cores in the system, 37, 39, 49, 61 Q h Index identifying the types of cores inside cluster/island k, k 37, 217, 219 R Total number of tasks to be executed, q energy SFA peak power qsfa q SVA S DLTF i S LTF i Worst-case energy consumption and peak power consumption ratio for SFA when we consider discrete DVFS levels against the continuous cases, 176, 177 Worst-case energy consumption and peak power consumption ratio for SFA when we consider discrete DVFS levels against the continuous cases, 176, 177 Worst-case energy consumption and peak power consumption ratio for SVA when we consider discrete DVFS levels against the continuous cases, 177 Task set assigned to core i after partitioning the tasks using the DLTF strategy, 140, 141, 143, 147 Task set assigned to core i after partitioning the tasks using the LTF strategy, 139 S i Task set assigned to core i, xv, 37, 186, 197 T 0 Column vector T 0 ¼ Ti 0 ðþ t that accounts for the N1 first-order derivative of the temperature on each thermal node of an RC thermal network with respect to time 46, 48, 96 T Column vector T ¼ ½T i ðþ t N1 that represents the temperatures on the thermal nodes of an RC thermal network, T amb Ambient temperature, 16, 46, 47, 52, 59, 62 64, 68, 71, 73, 76, 80, 91, 95, 96, 124