Power System Stability Enhancement Under Three Phase Fault with FACTS Devices TCSC, STATCOM and UPFC
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1 S.Ttus* et l. / (IJITR) INTERNTIONL JOURNL OF INNOVTIVE TEHNOLOGY ND RESERH Volue No. 1, Issue No. 1, DeeerJnury 2013, Power Syste Stlty Enhneent Under Three Phse Fult wth FTS Dees TS, STTOM nd UPF Dr. S. Ttus Deprtent of EEE MM ollege of Engneerng Trhrppll, Ind.J.Vnothu Deprtent of EEE MM ollege of Engneerng Trhrppll, Ind I. Mr nn Nshnth Deprtent of EEE MM ollege of Engneerng Trhrppll, Ind strt Wth the eer nresng oplextes n power systes ross the gloe nd the growng need prode stle, seure, ontrolled, eono nd hgh qulty power espelly n the deregulted power rket. It s ensged tht FTS ontrollers wll ply tl role n power systes. Ths pper nestgtes the proeent of trnsent stlty of test syste under three phse fult usng fts dese. TS Thyrsr ontrolled Seres pr nd STTOM Stt Synhronous opensr re utlzed s seres nd shunt opensn respetely. UPFUnfed Power Flow ontroller s onsdered s shuntseres opensr. Keywords TS; STTOM; UPF; Trnsent stlty. I. INTRODUTION Tody s power syste s oplex network oprsng of generr, trnssson lnes, rety of lods nd trnsforers. Wth the eer nrese n power dend soe trnssson lne s ore loded thn ws plnned when they were ult [1]. Wth nresed lodng of long trnssson lne the prole of trnsent stlty fter jor dsturne, wll use the entre syste susde. Power syste stlty s the lty of eletr power syste, for gen ntl opertng ondn regn stte of opertng equlru fter eng sujeted physl dsturne, wth ost syste rles ounded so tht prtlly the entre syste rens ntt [2]. nd the n hllenges of odern power syste s trnsent stlty s referred s the plty of the syste ntn synhronous opern n the eent of lrge dsturne nd ths knd of stlty depends on preters of syste nd ntensty of dsturne [3] [4]. The reent deelopent of power eletrons ntrodues the use of flexle trnssson syste (FTS) ontrollers n power syste [5]. FTS tehnology prodes the opportunty [6] [7] Inrese lodng pty of trnssson lnes. Preent lkouts. Iproe genern produtty. Redue rultng rete power. Iproes syste stlty lt. Redue oltge flker. Redue syste dpng nd osllns. ontrol power flow so tht t flows through the desgnted routes. ongesn ngeent The onennl ontrol dees lke synhronous ondenser, sturted rer, thyrsr ontrolled rer, fxed pr thyrsr ontrolled rer, thyrsr swthed pr hng less syste stlty lt, less enhneent of syste dpng, less oltge flker ontrol when opred eergng fts dees lke TS, STTOM nd UPF [8][9]. Ths pper nestgtes the proeent of syste stlty wth rous eergng FTS dees nd ther oprsons. [10] [13] II. DESRIPTION OF FTS DEVIES. TS The s oneptul TS odule oprses seres pr,, n prllel wth thyrsrontrolled rer, LS, s shown n Fg.1. TS s seresontrolled pte retne tht n prode ontnuous ontrol of power on the lne oer wde rnge. The prnple of rleseres opensn s sply nrese the fundentlfrequeny oltge ross n fxed pr n seres opensted lne through pproprte rn of the frng ngle. Ths enhned oltge hnges the effete lue of the serespte retne nd ontrol the rete power [9] [14].. STTOM STTOM s ontrolled retepower soure. It prodes the desred retepower genern nd sorpn entrely y ens of eletron proessng of the oltge nd urrent wefors n oltgesoure onerter (VS). snglelne STTOM power rut s shown n ll rghts Resered. Pge 66
2 S.Ttus* et l. / (IJITR) INTERNTIONL JOURNL OF INNOVTIVE TEHNOLOGY ND RESERH Volue No. 1, Issue No. 1, DeeerJnury 2013, rel nd rete power flows n trnssson lne. It s onfgured s shown n Fg.3 nd oprses two VSs oupled through oon d ternl. One VSonerter 1 s onneted n shunt wth the lne through ouplng trnsforer, the other VSonerter 2 s nserted n seres wth the trnssson lne through n nterfe trnsforer. The d oltge for oth onerters s proded y oon pr nk. The seres onerter s ontrolled njet oltge phsor, Vpq, n seres wth the lne, whh n e red fro 0 Fgure1onfgurn of TS Fgure3onfgurn of UPF Fgure 2onfgurn of STTOM where VS s onneted utlty us through gnet ouplng. The exhnge of rete power etween the onerter nd the syste n e ontrolled y ryng the pltude of the 3phse output oltge, Es, of the onerter. Tht s, f the pltude of the output oltge s nresed oe tht of the utlty us oltge, Et, then urrent flows through the retne fro the onerter the syste nd the onerter genertes pterete power for the syste. If the pltude of the output oltge s deresed elow the utlty us oltge, then the urrent flows fro the syste the onerter nd the onerter sors nduterete power fro the syste. If the output oltge equls the syste oltge, the retepower exhnge eoes zero, n whh se the STTOM s sd e n flotng stte [9] [15] [16].. UPF The UPF s the ost erstle FTS ontroller deeloped so fr, wth ll enopssng pltes of oltge reguln, seres opensn, nd phse shftng. It n ndependently nd ery rpdly ontrol oth Vpq x. Moreoer, the phse ngle of Vpq n e ndependently red fro degree. In ths proess, the seres onerter exhnges oth rel nd rete power wth the trnssson lne. lthough the rete power s nternlly generted/ sored y the seres onerter, the relpower genern/ sorpn s de fesle y the denergy srge dee tht s, the pr. The shunnneted onerter 1 s used nly supply the relpower dend of onerter 2, whh deres fro the trnssson lne tself. The shunt onerter ntns onstnt oltge of the d us. Thus the net rel power drwn fro the syste s equl the losses of the two onerters nd ther ouplng trnsforers. In ddn, the shunt onerter ehes lke STTOM nd ndependently regultes the ternl oltge of the nteronneted us y genertng/ sorng requste ount of rete power [9] [17] []. III. MODEL OF TEST SYSTEM The elow test network s tested wth TS, STTOM, nd UPF seprtely nestgte the ehor wth fe preters suh s generr oltge (Vg), generr urrent (Ig), generted lod ngle (δ), oltge ner nfnte us (V) nd urrent ner nfnte us (I). These re done through MTL/SIMULINK wth followng ll rghts Resered. Pge 67
3 S.Ttus* et l. / (IJITR) INTERNTIONL JOURNL OF INNOVTIVE TEHNOLOGY ND RESERH Volue No. 1, Issue No. 1, DeeerJnury 2013, Infnte us Seres Fts Dees G2 2 1 Sendng end Fgure 4. Test syste wth seres FTS dee Rel power G1 Infnte us G2 Sendng end 1 Shunt Fts Dees 2 Fgure 5. Test syste wth shunt FTS dee Stge 1 To desgn test syste shown n fg 6. Stge 2 To esure fe preters under norl opertng ondn. Stge 3 To rete three phse fult ner nfnte us n test syste. Fult durn 0.6 seonds. Shown n fg 7. Stge 4 To esure fe preters under three phse fult ondns Stge 5 To desgn FTS dees (TS, STTOM nd UPF) Shown n fg 8, fg 9 nd fg 10 respetely. Stge 6 To onnet FTS dees ( seonds) n test syste under three phse fult ondn nd esure ehorl hnge of syste. The test syste spefn s Generr 1, 2 10KV, 110MW, 300 rp, TS 10MVR, 10KV, STTOM 10MVR, 10KV nd UPF 10MVR, 10KV. IV. RESULT ND DISUSSION In ordne wth the oe SIMULINK work the fe dfferent preters generr oltge (Vg), generr urrent (Ig), generted lod ngle (δ), oltge Generr Voltge (Vg) n olts G1 ner nfnte us (V) nd urrent ner nfnte us (I) of test syste s esured nd the settlng te of eh preter s lulted for syste stlty nd lso xze the power flow n trnssson lne. The suln result for generr oltge (Vg) of phse s shown n fg 11. It s ler tht under three phse fult, wthout FTS dee the oltge flutun of generr s ore, wheres, t s less when the FTS dees re noled. tle for generr oltge (Vg) under dfferent te nterl s onstruted fro the osered result. Durng the te nterl of 0.8 seonds nd seonds the oltge rses fro olts nd fro 8000 olts respetely whh s greter thn the generr oltge (Vg) wthout the noleent of FTS dee. So, when FTS dees re onneted the syste, t tkes 2.4 seonds for TS, 2.0 seonds for STTOM nd 1.4 seonds for UPF reh the stlty leel. TLE 1. GENERTOR VOLTGE (Vg) IN VOLTS Te n seonds Wthout FTS dee TS 0 STTOM 0 UPF The fg 12 shows the generr urrent (Ig) of phse. The generr urrent (Ig) s rehed stle t 4.4 seonds when the FTS dees re not onneted. fter norportng the FTS dees TS, STTOM nd UPF, the settlng te of generr urrent (Ig) s redued s 2.4, 3.4 nd 2.3 seonds respetely for rehng the stle ondn, Whh s undersod through tle 2. Generr urrent (Ig) n peres Rel power TLE 2. GENERTOR URRENT (Ig) IN MPS Te n seonds Wthout FTS dee TS STTOM UPF ll rghts Resered Pge 68
4 S.Ttus* et l. / (IJITR) INTERNTIONL JOURNL OF INNOVTIVE TEHNOLOGY ND RESERH Volue No. 1, Issue No. 1, DeeerJnury 2013, <Lod ngle K delt (deg)> <Output t e power Gn Dsply1 <Output ret e power Qeo (W)> Dsply2 Sope Inf nte us lod2 Synhronous Mhne1 lod3 fd1 Dsply3 es1 step1 Dsply es2 Dsrete, Ts = 5e005 s. pow ergu <Lod ngle Sope2 K delt (deg)> <Output t e power Gn1 <Output ret e power Qeo (W)> Sope3 Synhronous Mhne2 Sope1 Dsply4 fd2 step2 Fgure 6. Sulnk Model of Test Syste <Lod ngle K delt (deg)> <Output t e power G n D spl y1 <Output ret e power Qeo (W)> D spl y2 Sope Inf nte us ThreePhse Fult D sply es1 l od3 l od2 Synhronous M hne1 D spl y3 fd1 step1 es2 Dsrete, Ts = 5e005 s. pow ergu <Lod ngle Sope2 delt (deg)> <Output t e power KG n1 <Output ret e power Qeo (W)> Sope3 Synhronous Mh ne2 step2 Sope1 D spl y4 fd2 Fgure 7. Test Syste wth Three Phse ll rghts Resered. Pge 69
5 S.Ttus* et l. / (IJITR) INTERNTIONL JOURNL OF INNOVTIVE TEHNOLOGY ND RESERH Volue No. 1, Issue No. 1, DeeerJnury 2013, <Lod ngle delt (deg)> Sope13 K<Output t e power Sope7 Gn es1 lod3 Infnte us2 Gn2 Sope12 es4 Sope ThreePhse Fult1 ThreePhse reker1 10 kw3 lod4 fd2 step2 es3 Sope5 lod1 Synhronous Mhne3 fd3 Synhronous Mhne2 Infnte us1 step3 <Output ret e power Qeo (W)> <Output ret e power Qeo (W)> <Output t e power delt (deg)> Sope10 Sope2 <Output t e power Dsrete, Ts = 5e005 s. pow ergu <Lod ngle Sope9 <Lod ngle delt (deg)> Gn1 Sope4 K es2 Sope8 K Sope3 ThreePhse Fult lod2 Synhronous Mhne1 fd1 Sope1 step1 <Output ret e power Qeo (W)> 10 kw4 Sope11 n2 T S2 n2 n1 fd4 step4 n1 T S1 Synhronous Mhne4 n2 T S <Output ret e power Qeo (W)> n1 <Output t e power Sope14 delt (deg)> <Lod ngle K Gn3 Sope6 sour2 Fgure 8. Test Syste wth TS <Lod ngle delt (deg)> Sope14 K Sope13 <Output t e power G n Sope4 ThreePhse Fult K es2 Sope8 Sope3 Infnte us2 es1 lod3 lod2 Synhronous Mhne1 fd1 Sope1 step1 <Output ret e power Qeo (W)> G n2 Sope9 <Lod ngle delt (deg)> Sope12 onn3 STTOM1 Sope11 <Output t e power <Lod ngle delt (deg)> onn2 onn1 Sope7 10 kw4 K es4 Sope6 Gn3 ThreePhse Fult1 ThreePhse reker1 10 kw3 Sope lod4 fd2 step2 es3 lod1 Synhronous Mhne3 Sope5 fd3 Synhronous Mhne2 <Output ret e power Qeo (W)> Infnte us1 step3 <Output t e power Sope10 <Output ret e power Qeo (W)> step4 Synhronous Mh ne4 Sope2 <Output ret e power Qeo (W)> <Lod ngle delt (deg)> K Dsrete, Ts = 5e005 s. pow ergu Gn1 <Output t e power fd4 Fgure 9. Test Syste wth ll rghts Resered. Pge 70
6 S.Ttus* et l. / (IJITR) INTERNTIONL JOURNL OF INNOVTIVE TEHNOLOGY ND RESERH Volue No. 1, Issue No. 1, DeeerJnury 2013, <Lod ngle delt (deg)> Sope13 K<Output t e power Sope7 Gn <Output ret e power Qeo (W)> es1 lod3 Infnte us1 Sope4 K es2 Sope8 Sope3 ThreePhse Fult Sope12 lod2 Synhronous M hne1 Sope9 Infnte us2 fd1 Gn2 <Lod ngle l od1 ThreePhse Fult1 es4 Sope ThreePhse Trnsforer (Two Wndngs). lod4 ThreePhse Trnsforer (Two Wndngs)1 10 kw3 fd2 step2 Sope5 es3 Synhronous Mhne3 fd3 Synhronous M hne2 T <Output ret e power Qeo (W)> step3 <Output t e power <Output ret e power Qeo (W)> Sope10 Susyste onn4 onn3 onn2 onn5 onn4 onn2 onn1 Seres RL rnh1 Sope15 Susyste1 onn5 onn3 Sope11 <Out put t e power delt (deg)> <Lod ngle K 10 kw4 Gn3 Sope6 onn1 <Output ret e power Qeo (W)> Synhronous M h ne4 Sope2 <Output t e power delt (deg)> delt (deg)> <Lod ngle K Dsrete, Ts = 5e005 s. pow ergu Gn1 Sope1 step1 Sope14 step4 fd4 Fgure 10. Test Syste wth UPF Fgure 11. Suln Result for Generr Voltge (Vg) Fgure 12. Suln Result for Generr urrent ll rghts Resered. Pge 71
7 S.Ttus* et l. / (IJITR) INTERNTIONL JOURNL OF INNOVTIVE TEHNOLOGY ND RESERH Volue No. 1, Issue No. 1, DeeerJnury 2013, Fgure 13. Suln Result for Generr Lod ngle (δ) Fgure 15. Suln Result for urrent ner Infnte us (I) Generr Lod ngle (δ) n degree efore onnetng the FTS dees n test syste the lod ngle (δ) of generr s red up degree nd tkes round 7.4 seonds settle down stle regon fter the fult reoery. ut due the nterfng of FTS dee the settlng te s redued 4.2, 4.4 nd 4.2 seonds for TS, STTOM nd UPF respetely s shown n fg 13 nd tle 3. Fgure 14. Suln Result for Voltge ner Infnte us (V) TLE 3. GENERTOR LOD NGLE (δ) IN DEGREE Te n seonds Wthout FTS dee TS STTOM UPF Fro Fg 14 t s osered tht the settlng te for the oltge ner nfnte us (V) s 5.4 seonds when the FTS dees re not onneted. fter onnetng the FTS dees settlng te s redued s 0.4, nd 0.2 seonds for stle ondn. Slrly the urrent ner nfnte us (I) oes stle wthn 0.4, nd 0.2 seonds for TS, STTOM nd UPF respetely fter the fult reoery. ut wthout those dees t tkes 3.4 seonds reh stlty s shown n fg 15. The settlng te of Vg, Ig, δ, V, I for TS, STOM nd UPF re studed nd shown n tle 4. It ll rghts Resered. Pge 72
8 S.Ttus* et l. / (IJITR) INTERNTIONL JOURNL OF INNOVTIVE TEHNOLOGY ND RESERH Volue No. 1, Issue No. 1, DeeerJnury 2013, found tht the syste stlty s heed n short nterl whle nterfng UPF. [8] Enrque h, ludo R. Fuerte Esquel, Hugo rz Perez, esr ngeles ho, FTS Modellng nd Suln n Power Networks, John Wley & sons LTD, TLE 5. OMPRISON OF SETTLING TIME [9] R. Mohn Mthur, Rj K. Vr, Thyrsr sed FTS ontrollers for Eletrl Trnssson Systes, IEEE press seres on Power Engneerng, John Wley & Sons LTD, [10] S. Shnkr, S. lj, S. rul, Suln nd oprson of Vrous FTS dees n power syste, Internnl Journl of Engneerng Sene nd Tehnology, olue 2 (4), 2010, [11] lrez Sef, Ssn Ghol, n Shnpour, Power Flow Studt nd oprson of FTS: Seres (SSS), Shunt (STTOM) nd shunt seres (UPF), The Pf Journl of Sene nd Tehnology olue 11. No. 1. My 2010 (sprng). [12] rthtsode Yoe, N. Mthulnnthn, oprson of Shunt pr, SV nd STTOM n Stt Voltge Stlty Mrgn Enhneent, Internnl Journl of Eletrl Engneerng Edun, 41/2. [13] J. rt,. Seedn, S. S. Mortz, Dpng Power Syste Oslln Iproeent y FTS Dees: oprson etween SSS nd STTOM, Worl dy of Sene, Engneerng nd Tehnology [14]. Kze,. drzdeh, Modellng nd Suln of SV nd TS Study ther Lts on Mxu Lodlty Pont, Eletrl Power nd Energy Syste 26 (2004) , Elseer LTD. [15] P. Venkt Kshore, Dr. S. R Reddy, Voltge Sg Mtgn n Eght us Syste usng D STTOM for Power Qulty Iproeent, Internnl Journl of Engneerng Sene nd Tehnology, olue 2 (4), 2010, [16] Syed Mojt Shrn oroujen, Rez Het, Hdeh Delfkr, Elhe ehzdpour, Voltge Support nd Stlty Enhneent usng STTOM, ern Journl of Sentf Reserh, Euro Journl Pulshng, [17] N. Dzdre, G. nderson, Power Flow Reguln y use of UPF s Injen Model, IEEE Power Teh 99 onferene, [] S. Muthu Krshnn, Dr.. Nrl Kur oprson of Suln nd Experentl Results of UPF used for Power Qulty Iproeent, Internnl Journl of oputer nd Eletrl Engneerng, olue 2, No. 3, June Settlng te n seonds Preters Generr oltge (Vg) Generr urrent(ig) Generr lod ngle(δ) Voltge ner nfnte us(v) urrent ner nfnte us(i) Wthout FTS dees TS STTOM UPF V. ONLUSION In ths pper the power syste stlty enhneent of test network wth FTS dees TS, STTOM nd UPF s presented nd dsussed under three phse short rut fult. It s ler tht the syste regns ts stlty under ny one of the FTS dee s noled. lso the settlng te reh the stlty of the syste wth UPF for dfferent preters (Generr Voltge 1.4 ses, Generr urrent 2.3 ses, Generr Lod ngle 4.2 ses, Voltge ner Infnte us 0.2 ses nd urrent ner Infnte us 0.1 ses) s oprtely uh etter thn STTOM s well s TS. REFERENES [1] Dr. M. Rjr, N. Rek, D. Murl, oprson of FTS dees for power syste stlty enhneent, Internnl Journl of oputer pplns ( ), olue 8 No. 4, Oer [2] P. Kundur, J. Pser, V. jjrpu, G. nderson,. ose,. nzres, N. Htzrgyrou, D. Hll,. Stnko,. Tylor, T. V. uste, V. Vttl, Defenn nd lssfn of Power Syste Stlty, IEEE Trnsn on Power Syste, 2004, 19(2) [3] Hd Sdt, Power syste nlyss, TT MGrw Hll edn, [4] K. R. Pdyr, Power Syste Dyn Stlty nd ontrol, seond edn 2002,. S. puln, Hyderd [5] S. K. Srst, dned Power Eletrons sed Fts ontrollers nd Oerew, sn Power Eletrons Journl, olue 4, No. 3 Deeer [6] hntu Rz Mkkr, Llle Dewn, Trnsent stlty enhneent usng roust FTS ontrollers ref ur, ndn Journl on Eletrl & Eletrons Engneerng olue 1, No. 7, Deeer [7] t Grg, Snjy Kur grwl, Voltge ontrol nd Dyn Perforne of Power Trnssson Syste usng STTOM nd ts oprson wth SV, Internnl Journl of dnes n Engneerng nd Tehnology, Jnury ll rghts Resered. Pge 73
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