74AVCH16T General description. 2. Features and benefits

Size: px
Start display at page:

Download "74AVCH16T General description. 2. Features and benefits"

Transcription

1 16-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 5 1 March 2012 Product data sheet 1. General description The is a 16-bit transceiver with bidirectional level voltage translation and 3-state outputs.the device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual supplies (V CC() and V CC(B) ) for voltage translation and four 8-bit input-output ports (nn, nbn) each with its own output enable (noe) and send/receive (ndir) input for direction control. V CC() and V CC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. HIGH on ndir selects transmission from nn to nbn while a LOW on ndir selects transmission from nbn to nn. HIGH on noe causes the outputs to assume a high-impedance OFF-state The device is fully specified for partial power-down applications using I OFF. The I OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V CC() or V CC(B) are at GND level, both and B outputs are in the high-impedance OFF-state. The bus-hold circuitry on the powered-up side always stays active. The has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features and benefits Wide supply voltage range: V CC() : 0.8 V to 3.6 V V CC(B) : 0.8 V to 3.6 V Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-114F Class 3B exceeds 8000 V MM JESD exceeds 200 V CDM JESD22-C101D exceeds 1000 V Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation)

2 3. Ordering information 200 Mbit/s ( 1.1 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 2.5 V translation) 200 Mbit/s ( 1.1 V to 1.8 V translation) 150 Mbit/s ( 1.1 V to 1.5 V translation) 100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 m per JESD 78 Class II Inputs accept voltages up to 3.6 V I OFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to+85 C and 40 C to+125 C Table 1. Type number Ordering information [1] lso known as TVSOP48. Package Temperature range Name Description Version DGG 40 C to+125 C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm DGV 40 C to+125 C TSSOP48 [1] plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm EV 40 C to+125 C VFBG56 plastic very thin fine-pitch ball grid array package; 56 balls; body mm BX 40 C to+125 C HXQFN60 plastic compatible thermal enhanced extremely thin quad flat package; no leads; 60 terminals; body mm SOT362-1 SOT480-1 SOT702-1 SOT Functional diagram 1DIR 2DIR 1OE 2OE B1 2B1 V CC() V CC(B) V CC() V CC(B) to other seven channels to other seven channels 001aak426 Fig 1. Logic diagram Product data sheet Rev. 5 1 March of 29

3 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 V CC() V CC(B) 1OE 1DIR B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 V CC() V CC(B) 2OE 2DIR aak425 Fig 2. Logic symbol Product data sheet Rev. 5 1 March of 29

4 5. Pinning information 5.1 Pinning 1DIR 1B1 1B2 GND 1B3 1B4 V CC(B) 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 V CC(B) 2B5 2B6 GND 2B7 2B8 2DIR OE GND V CC() GND GND V CC() GND ball 1 index area B C D E F G H J K 25 2OE 001aak aak430 Transparent top view Fig 3. Pin configuration SOT362-1 and SOT480-1 (TSSOP48) Fig 4. Pin configuration SOT702-1 (VFBG56) Product data sheet Rev. 5 1 March of 29

5 terminal 1 index area D D4 1 D5 B20 B19 B18 D B1 B B2 B B3 B B4 B B5 B B6 B B7 B11 9 GND (1) D6 B8 B9 B10 D7 17 D D3 Transparent top view 001aak432 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SOT (HXQFN60) Product data sheet Rev. 5 1 March of 29

6 5.2 Pin description Table 2. Pin description Symbol Pin Description SOT362-1 and SOT702-1 SOT SOT DIR, 2DIR 1, 24 1, K1 30, 13 direction control 1B1 to 1B8 2, 3, 5, 6, 8, 9, 11, 12 B2, B1, C2, C1, D2, D1, E2, E1 B20, 31, D5, D1, 2, B2, B3, 5 data input or output 2B1 to 2B8 13, 14, 16, 17, 19, 20, 22, 23 GND [1] 4, 10, 15, 21, 28, 34, 39, 45 [1] ll GND pins must be connected to ground (0 V). F1, F2, G1, G2, H1, H2, J1, J2 B3, D3, G3, J3, J4, G4, D4, B4 6, B5, B6, 9, D2, D6, 12, B8 32, 3, 8, 11, 16, 19, 24, 27 data input or output ground (0 V) V CC(B) 7, 18 C3, H3 1, 10 supply voltage B (nbn inputs are referenced to V CC(B) ) 1OE, 2OE 48, 25 6, K6 29, 14 output enable input (active LOW) 11 to 18 47, 46, 44, 43, 41, 40, 38, to 28 36, 35, 33, 32, 30, 29, 27, 26 B5, B6, C5, C6, D5, D6, E5, E6 F6, F5, G6, G5, H6, H5, J6, J5 B18, 28, D8, D4, 25, B16, B15, 22 21, B13, B12, 18, D3, D7, 15, B10 data input or output data input or output V CC() 31, 42 C4, H4 17, 26 supply voltage (nn, noe and ndir inputs are referenced to V CC() ) n.c. - 2, 3, 4, 5, K2, K3, K4, K5 4, 7, 20, 23, B1, B4, B7, B9, B11, B14, B17, B19 not connected 6. Functional description Table 3. Function table [1] Supply voltage Input Input/output [3] V CC(), V CC(B) noe [2] ndir [2] nn [2] nbn [2] 0.8 V to 3.6 V L L nn = nbn input 0.8 V to 3.6 V L H input nbn = nn 0.8 V to 3.6 V H X Z Z GND [3] X X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don t care; Z = high-impedance OFF-state. [2] The nn, ndir and noe input circuit is referenced to V CC() ; The nbn input circuit is referenced to V CC(B). [3] If at least one of V CC() or V CC(B) is at GND level, the device goes into suspend mode. Product data sheet Rev. 5 1 March of 29

7 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC() supply voltage V V CC(B) supply voltage B V I IK input clamping current V I <0V 50 - m V I input voltage [1] V I OK output clamping current V O <0V 50 - m V O output voltage ctive mode [1][2][3] 0.5 V CCO +0.5 V Suspend or 3-state mode [1] V I O output current V O =0VtoV CC [2] - 50 m I CC supply current I CC() or I CC(B) m I GND ground current m T stg storage temperature C P tot total power dissipation T amb = 40 C to +125 C; TSSOP48 package [4] mw VFBG56 package [5] mw HXQFN60 package [5] mw [1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] V CCO is the supply voltage associated with the output port. [3] V CCO V should not exceed 4.6 V. [4] bove 60 C the value of P tot derates linearly with 5.5 mw/k. [5] bove 70 C the value of P tot derates linearly with 1.8 mw/k. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit V CC() supply voltage V V CC(B) supply voltage B V V I input voltage V V O output voltage ctive mode [1] 0 V CCO V Suspend or 3-state mode V T amb ambient temperature C t/ V input transition rise and fall rate V CCI = 0.8 V to 3.6 V [2] - 5 ns/v [1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the input port. Product data sheet Rev. 5 1 March of 29

8 9. Static characteristics Table 6. Typical static characteristics at T amb = 25 C [1][2] t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V OH HIGH-level output voltage V I = V IH or V IL V OL LOW-level output voltage V I = V IH or V IL I I input leakage current ndir, noe input; V I = 0 V or 3.6 V; V CC() =V CC(B) = 0.8 V to 3.6 V [1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the data input port. [3] The bus hold circuit can sink at least the minimum low sustaining current at V IL max. I BHL should be measured after lowering V I to GND and then raising it to V IL max. [4] The bus hold circuit can source at least the minimum high sustaining current at V IH min. I BHH should be measured after raising V I to V CC and then lowering it to V IH min. [5] n external driver must source at least I BHLO to switch this node from LOW to HIGH. [6] n external driver must sink at least I BHHO to switch this node from HIGH to LOW. [7] For I/O ports, the parameter I OZ includes the input leakage current. I O = 1.5 m; V CC() =V CC(B) = 0.8 V V I O = 1.5 m; V CC() =V CC(B) = 0.8 V V I BHL bus hold LOW current or B port; V I =0.42V;V CC() =V CC(B) = 1.2 V [3] I BHH bus hold HIGH current or B port; V I =0.78V;V CC() =V CC(B) =1.2V [4] I BHLO bus hold LOW overdrive or B port; V CC() = V CC(B) = 1.2 V [5] current I BHHO bus hold HIGH overdrive or B port; V CC() = V CC(B) = 1.2 V [6] current I OZ OFF-state output current or B port; V O =0 Vor V CCO ; [7] V CC() =V CC(B) =3.6V suspend mode port; V O =0VorV CCO ; [7] V CC() = 3.6 V; V CC(B) =0V suspend mode B port; V O =0VorV CCO ; [7] V CC() =0 V; V CC(B) =3.6V I OFF power-off leakage current port; V I or V O = 0 V to 3.6 V; V CC() =0V;V CC(B) = 0.8 V to 3.6 V B port; V I or V O = 0 V to 3.6 V; V CC(B) =0V;V CC() = 0.8 V to 3.6 V C I input capacitance ndir, noe input; V I = 0 V or 3.3 V; pf V CC() =V CC(B) =3.3V C I/O input/output capacitance and B port; V O = 3.3 V or 0 V; V CC() =V CC(B) =3.3V pf Product data sheet Rev. 5 1 March of 29

9 Table 7. Static characteristics [1][2] t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Max Min Max V IH HIGH-level data input input voltage V CCI = 0.8 V 0.70V CCI V CCI - V V CCI = 1.1 V to 1.95 V 0.65V CCI V CCI - V V CCI = 2.3 V to 2.7 V V V CCI = 3.0 V to 3.6 V V ndir, noe input V CC() = 0.8 V 0.70V CC() V CC() - V V CC() = 1.1 V to 1.95 V 0.65V CC() V CC() - V V CC() = 2.3 V to 2.7 V V V CC() = 3.0 V to 3.6 V V V IL LOW-level data input input voltage V CCI = 0.8 V V CCI V CCI V V CCI = 1.1 V to 1.95 V V CCI V CCI V V CCI = 2.3 V to 2.7 V V V CCI = 3.0 V to 3.6 V V ndir, noe input V CC() = 0.8 V V CC() V CC() V V CC() = 1.1 V to 1.95 V V CC() V CC() V V CC() = 2.3 V to 2.7 V V V CC() = 3.0 V to 3.6 V V V OH HIGH-level V I = V IH or V IL output I O = 100 ; voltage V CC() =V CC(B) = 0.8 V to 3.6 V V CCO V CCO V I O = 3 m; V CC() =V CC(B) = 1.1 V V I O = 6 m; V CC() =V CC(B) = 1.4 V V I O = 8 m; V V CC() =V CC(B) =1.65V I O = 9 m; V CC() =V CC(B) = 2.3 V V I O = 12 m; V CC() =V CC(B) =3.0V V V OL I I LOW-level output voltage input leakage current V I = V IH or V IL I O = 100 ; V V CC() =V CC(B) = 0.8 V to 3.6 V I O = 3 m; V CC() =V CC(B) = 1.1 V V I O = 6 m; V CC() =V CC(B) = 1.4 V V I O = 8 m; V CC() =V CC(B) = 1.65 V V I O = 9 m; V CC() =V CC(B) = 2.3 V V I O = 12 m; V CC() =V CC(B) =3.0V V ndir, noe input; V I = 0 V or 3.6 V; V CC() =V CC(B) = 0.8 V to 3.6 V Product data sheet Rev. 5 1 March of 29

10 Table 7. Static characteristics continued [1][2] t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Max Min Max I BHL bus hold or B port [3] LOW current V I = 0.49 V; V CC() =V CC(B) =1.4V V I = 0.58 V; V CC() =V CC(B) =1.65V V I = 0.70 V; V CC() =V CC(B) =2.3V V I = 0.80 V; V CC() =V CC(B) = 3.0 V I BHH bus hold or B port [4] HIGH current V I = 0.91 V; V CC() =V CC(B) =1.4V V I = 1.07 V; V CC() =V CC(B) =1.65V V I = 1.60 V; V CC() =V CC(B) =2.3V V I = 2.00 V; V CC() =V CC(B) =3.0V I BHLO bus hold or B port [5] LOW V CC() = V CC(B) = 1.6 V overdrive current V CC() = V CC(B) = 1.95 V V CC() = V CC(B) = 2.7 V V CC() = V CC(B) = 3.6 V I BHHO bus hold or B port [6] HIGH V CC() = V CC(B) = 1.6 V overdrive current V CC() = V CC(B) = 1.95 V V CC() = V CC(B) = 2.7 V V CC() = V CC(B) = 3.6 V I OZ OFF-state or B port; V O =0 Vor V CCO ; [7] output current V CC() =V CC(B) =3.6V suspend mode port; [7] V O =0VorV CCO ; V CC() =3.6 V; V CC(B) =0V suspend mode B port; [7] V O =0VorV CCO ; V CC() =0 V; V CC(B) =3.6V I OFF power-off port; V I or V O = 0 V to 3.6 V; leakage current V CC() =0V; V CC(B) = 0.8 V to 3.6 V B port; V I or V O = 0 V to 3.6 V; V CC(B) =0V; V CC() = 0.8 V to 3.6 V Product data sheet Rev. 5 1 March of 29

11 Table 7. Static characteristics continued [1][2] t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Max Min Max I CC supply port; V I = 0 V or V CCI ; I O = 0 current V CC() = 0.8 V to 3.6 V; V CC(B) = 0.8 V to 3.6 V V CC() = 1.1 V to 3.6 V; V CC(B) = 1.1 V to 3.6 V V CC() = 3.6 V; V CC(B) = 0 V V CC() = 0 V; V CC(B) = 3.6 V B port; V I = 0 V or V CCI ; I O = 0 V CC() = 0.8 V to 3.6 V; V CC(B) = 0.8 V to 3.6 V V CC() = 1.1 V to 3.6 V; V CC(B) = 1.1 V to 3.6 V V CC() = 3.6 V; V CC(B) = 0 V V CC() = 0 V; V CC(B) = 3.6 V plus B port (I CC() + I CC(B) ); I O =0; V I =0 Vor V CCI ; V CC() = 0.8 V to 3.6 V; V CC(B) = 0.8 V to 3.6 V plus B port (I CC() + I CC(B) ); I O =0; V I =0 Vor V CCI ; V CC() = 1.1 V to 3.6 V; V CC(B) = 1.1 V to 3.6 V [1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the data input port. [3] The bus hold circuit can sink at least the minimum low sustaining current at V IL max. I BHL should be measured after lowering V I to GND and then raising it to V IL max. [4] The bus hold circuit can source at least the minimum high sustaining current at V IH min. I BHH should be measured after raising V I to V CC and then lowering it to V IH min. [5] n external driver must source at least I BHLO to switch this node from LOW to HIGH. [6] n external driver must sink at least I BHHO to switch this node from HIGH to LOW. [7] For I/O ports, the parameter I OZ includes the input leakage current. Table 8. Typical total supply current (I CC() + I CC(B) ) V CC() V CC(B) Unit 0 V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0 V V V V V V V Product data sheet Rev. 5 1 March of 29

12 10. Dynamic characteristics Table 9. Typical power dissipation capacitance at V CC() = V CC(B) and T amb = 25 C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V CC() = V CC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V C PD power dissipation capacitance [1] C PD is used to determine the dynamic power dissipation (P D in W). P D =C PD V CC 2 f i N+ (C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = load capacitance in pf; V CC = supply voltage in V; port: (direction nn to nbn); output enabled port: (direction nn to nbn); output disabled port: (direction nbn to nn); output enabled port: (direction nbn to nn); output disabled B port: (direction nn to nbn); output enabled B port: (direction nn to nbn); output disabled B port: (direction nbn to nn); output enabled B port: (direction nbn to nn); output disabled N = number of inputs switching; (C L V 2 CC f o ) = sum of the outputs. [2] f i = 10 MHz; V I =GNDtoV CC ; t r = t f = 1 ns; C L = 0 pf; R L = pf pf pf pf pf pf pf pf Product data sheet Rev. 5 1 March of 29

13 Table 10. Typical dynamic characteristics at V CC() = 0.8 V and T amb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter Conditions V CC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V t pd propagation delay nn to nbn ns nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns [1] t pd is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. Table 11. Typical dynamic characteristics at V CC(B) = 0.8 V and T amb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter Conditions V CC() Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V t pd propagation delay nn to nbn ns nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns [1] t pd is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. Product data sheet Rev. 5 1 March of 29

14 Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7. Symbol Parameter Conditions V CC(B) Unit 1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V Min Max Min Max Min Max Min Max Min Max V CC() = 1.1 V to 1.3 V t pd propagation nn to nbn ns delay nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns V CC() = 1.4 V to 1.6 V t pd propagation nn to nbn ns delay nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns V CC() = 1.65 V to 1.95 V t pd propagation nn to nbn ns delay nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns V CC() = 2.3V to 2.7V t pd propagation nn to nbn ns delay nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns V CC() = 3.0V to 3.6V t pd propagation nn to nbn ns delay nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns [1] t pd is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. Product data sheet Rev. 5 1 March of 29

15 Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter Conditions V CC(B) Unit 1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V Min Max Min Max Min Max Min Max Min Max V CC() = 1.1 V to 1.3 V t pd propagation nn to nbn ns delay nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns V CC() = 1.4 V to 1.6 V t pd propagation nn to nbn ns delay nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns V CC() = 1.65 V to 1.95 V t pd propagation nn to nbn ns delay nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns V CC() = 2.3V to 2.7V t pd propagation nn to nbn ns delay nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns V CC() = 3.0V to 3.6V t pd propagation nn to nbn ns delay nbn to nn ns t dis disable time noe to nn ns noe to nbn ns t en enable time noe to nn ns noe to nbn ns [1] t pd is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. Product data sheet Rev. 5 1 March of 29

16 11. Waveforms V I nn, nbn input V M GND t PHL t PLH V OH nbn, nn output V M V OL 001aak285 Fig 6. Measurement points are given in Table 14. V OL and V OH are typical output voltage levels that occur with the output load. The data input (nn, nbn) to output (nbn, nn) propagation delay times V I noe input V M GND t PLZ t PZL V CCO output LOW-to-OFF OFF-to-LOW V OL V X V M t PHZ t PZH V OH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled V Y outputs disabled V M outputs enabled 001aak286 Fig 7. Measurement points are given in Table 14. V OL and V OH are typical output voltage levels that occur with the output load. Enable and disable times Table 14. Measurement points Supply voltage Input [1] Output [2] V CC(), V CC(B) V M V M V X V Y 0.8 V to 1.6 V 0.5V CCI 0.5V CCO V OL +0.1V V OH 0.1 V 1.65 V to 2.7 V 0.5V CCI 0.5V CCO V OL +0.15V V OH 0.15 V 3.0 V to 3.6 V 0.5V CCI 0.5V CCO V OL +0.3V V OH 0.3 V [1] V CCI is the supply voltage associated with the data input port. [2] V CCO is the supply voltage associated with the output port. Product data sheet Rev. 5 1 March of 29

17 V I negative pulse 0 V 90 % V M 10 % t W V M t f t r t r t f V I positive pulse 0 V 10 % 90 % V M t W V M V EXT V CC G V I DUT V O RL RT CL RL 001aae331 Fig 8. Test data is given in Table 15. R L = Load resistance. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance. V EXT = External voltage for measuring switching times. Test circuit for measuring switching times Table 15. Test data Supply voltage Input Load V EXT V CC(), V CC(B) V [1] I t/ V [2] C L R L t PLH, t PHL t PZH, t PHZ t PZL, t [3] PLZ 0.8 V to 1.6 V V CCI 1.0ns/V 15pF 2k open GND 2V CCO 1.65 V to 2.7 V V CCI 1.0ns/V 15pF 2k open GND 2V CCO 3.0 V to 3.6 V V CCI 1.0ns/V 15pF 2k open GND 2V CCO [1] V CCI is the supply voltage associated with the data input port. [2] dv/dt 1.0 V/ns [3] V CCO is the supply voltage associated with the output port. Product data sheet Rev. 5 1 March of 29

18 12. Typical propagation delay characteristics t pd (ns) aai476 (1) t pd (ns) aai477 (1) (2) (3) (4) (5) (6) 12 8 (2) (3) (4) (5) (6) C L (pf) C L (pf) a. Propagation delay (nn to nbn); V CC() = 0.8 V b. Propagation delay (nn to nbn); V CC(B) = 0.8 V (1) V CC(B) = 0.8 V. (1) V CC() = 0.8 V. (2) V CC(B) = 1.2 V. (2) V CC() = 1.2 V. (3) V CC(B) = 1.5 V. (3) V CC() = 1.5 V. (4) V CC(B) = 1.8 V. (4) V CC() = 1.8 V. (5) V CC(B) = 2.5 V. (5) V CC() = 2.5 V. (6) V CC(B) = 3.3 V. (6) V CC() = 3.3 V. Fig 9. Typical propagation delay versus load capacitance; T amb = 25 C Product data sheet Rev. 5 1 March of 29

19 7 001aai478 (1) 7 001aai491 t PLH (ns) t PHL (ns) (1) 5 (2) 5 (3) (2) 3 (4) (5) 3 (3) (4) (5) C L (pf) a. LOW to HIGH propagation delay (nn to nbn); V CC() = 1.2 V C L (pf) b. HIGH to LOW propagation delay (nn to nbn); V CC() = 1.2 V 7 001aai aai480 t PLH (ns) (1) t PHL (ns) 5 (2) 5 (1) (3) (2) 3 (4) (5) 3 (3) (4) (5) C L (pf) C L (pf) Fig 10. c. LOW to HIGH propagation delay (nn to nbn); V CC() = 1.5 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Typical propagation delay versus load capacitance; T amb = 25 C d. HIGH to LOW propagation delay (nn to nbn); V CC() = 1.5 V Product data sheet Rev. 5 1 March of 29

20 7 001aai aai482 t PLH (ns) (1) t PHL (ns) 5 (2) 5 (1) (3) (2) 3 (4) (5) 3 (3) (4) (5) C L (pf) a. LOW to HIGH propagation delay (nn to nbn); V CC() = 1.8 V C L (pf) b. HIGH to LOW propagation delay (nn to nbn); V CC() = 1.8 V 7 001aai aai486 t PLH (ns) (1) t PHL (ns) 5 5 (1) (2) (3) (2) 3 (4) (5) 3 (3) (4) (5) C L (pf) C L (pf) Fig 11. c. LOW to HIGH propagation delay (nn to nbn); V CC() = 2.5 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Typical propagation delay versus load capacitance; T amb = 25 C d. HIGH to LOW propagation delay (nn to nbn); V CC() = 2.5 V Product data sheet Rev. 5 1 March of 29

21 7 001aai aai484 t PLH (ns) (1) t PHL (ns) 5 5 (1) (2) 3 (3) (4) (5) 3 (2) (3) (4) (5) C L (pf) C L (pf) Fig 12. a. LOW to HIGH propagation delay (nn to nbn); V CC() = 3.3 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Typical propagation delay versus load capacitance; T amb = 25 C b. HIGH to LOW propagation delay (nn to nbn); V CC() = 3.3 V Product data sheet Rev. 5 1 March of 29

22 13. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E X y c H E v M Z Q 2 1 ( ) 3 pin 1 index 1 24 detail X L p L θ e bp w M mm scale DIMENSIONS (mm are the original dimensions). UNIT b p c D (1) E (2) e H E L L p Q v w y Z max mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT362-1 MO Fig 13. Package outline SOT362-1 (TSSOP48) Product data sheet Rev. 5 1 March of 29

23 TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm SOT480-1 D E X c y H E v M Z Q 2 1 ( ) 3 pin 1 index θ L p L detail X 1 24 e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H E L L p Q v w y Z max. (1) mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT480-1 MO-153 EUROPEN PROJECTION ISSUE DTE Fig 14. Package outline SOT480-1 (TSSOP48) Product data sheet Rev. 5 1 March of 29

24 VFBG56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm SOT702-1 D B ball 1 index area E 2 1 detail X e e 1 1/2 e b v M w M C C B y 1 C C y K J H G e F E e 2 D 1/2 e C X B ball 1 index area DIMENSIONS (mm are the original dimensions) UNIT 1 2 b D E e e 1 e 2 v w y y max mm mm scale OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT702-1 MO Fig 15. Package outline SOT702-1 (VFBG56) Product data sheet Rev. 5 1 March of 29

25 HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads; 60 terminals; body 4 x 6 x 0.5 mm SOT D B terminal 1 index area E 2 1 detail X e 2 e 1 b er v w C C B v w C B e C L 1 D2 D6 11 1/2 e 16 B8 B10 et D3 D7 y 1 C C y L er et 10 B7 B11 17 e E h e 3 e 4 1/2 e B1 B17 1 terminal 1 index area D5 D1 32 B20 B18 D h D8 et D4 er X et K er 0 5 mm Dimensions Unit 1 2 b D D h E E h e e 1 e 2 e 3 e 4 er et K L L 1 v w y y 1 mm max nom min sot1134-2_po Outline version References IEC JEDEC JEIT European projection Issue date SOT Fig 16. Package outline SOT (HXQFN60) Product data sheet Rev. 5 1 March of 29

26 14. bbreviations Table 16. cronym CDM DUT ESD HBM MM bbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes v Product data sheet - v.4 Modifications: For type number BX the SOT code has changed to SOT v Product data sheet - v.3 Modifications: Legal pages updated. v Product data sheet - v.2 v Product data sheet - v.1 v Product data sheet - - Product data sheet Rev. 5 1 March of 29

27 16. Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Product data sheet Rev. 5 1 March of 29

28 Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia s specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia s standard warranty and Nexperia s product specifications. Translations non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Product data sheet Rev. 5 1 March of 29

29 18. Contents 1 General description Features and benefits Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Typical propagation delay characteristics Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Date of release: 01 March 2012

74AVC32T General description. 2. Features and benefits

74AVC32T General description. 2. Features and benefits 32-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 1 16 January 2013 Product data sheet 1. General description The is a 32-bit transceiver with bidirectional

More information

74AVC20T245-Q General description. 2. Features and benefits

74AVC20T245-Q General description. 2. Features and benefits 20-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 1 7 April 2016 Product data sheet 1. General description The is a 20 bit, dual supply transceiver that enables

More information

74AVC20T General description. 2. Features and benefits

74AVC20T General description. 2. Features and benefits 20-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 7 8 March 2012 Product data sheet 1. General description The is a 20-bit, dual supply transceiver that enables

More information

4-bit dual supply translating transceiver with configurable voltage translation; 3-state

4-bit dual supply translating transceiver with configurable voltage translation; 3-state 4-bit dual supply translating transceiver with configurable voltage translation; -state Rev. 5 7 December 205 Product data sheet. General description The is an 4-bit, dual supply transceiver that enables

More information

8-bit dual supply translating transceiver with configurable voltage translation; 3-state

8-bit dual supply translating transceiver with configurable voltage translation; 3-state 8-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 5 27 December 202 Product data sheet. General description The is an 8-bit, dual supply transceiver that enables

More information

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1. Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance

More information

2-input EXCLUSIVE-OR gate

2-input EXCLUSIVE-OR gate Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output

More information

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device. 74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function

More information

74AVC4T774PW. 4-bit dual supply translating transceiver; 3-state

74AVC4T774PW. 4-bit dual supply translating transceiver; 3-state Rev. 1 25 September 2017 Product data sheet 1 General description 2 Features and benefits The is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight 1-bit input-output

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output

More information

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers. Rev. 1 2 November 2015 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. The provides two buffers. 2. Features and benefits 3. Ordering information Wide supply voltage

More information

The 74AXP1G04 is a single inverting buffer.

The 74AXP1G04 is a single inverting buffer. Rev. 1 25 August 2014 Product data sheet 1. General description The is a single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This

More information

Octal bus transceiver; 3-state

Octal bus transceiver; 3-state Rev. 2 3 November 2016 Product data sheet 1. General description The is an 8-bit transceiver with 3-state outputs. The device features an output enable (OE) and send/receive (DIR) for direction control.

More information

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer. Rev. 1 18 November 2013 Product data sheet 1. General description The provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

More information

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW

More information

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function. Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output

More information

The 74LV08 provides a quad 2-input AND function.

The 74LV08 provides a quad 2-input AND function. Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.

More information

74LVC1G125-Q100. Bus buffer/line driver; 3-state

74LVC1G125-Q100. Bus buffer/line driver; 3-state Rev. 2 8 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).

More information

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state Rev. 7 pril 203 Product data sheet. General description The consists of four non-inverting buffers/line drivers with 3-state outputs (ny) that are controlled by the output enable input (noe). HIGH at noe

More information

The 74AUP2G34 provides two low-power, low-voltage buffers.

The 74AUP2G34 provides two low-power, low-voltage buffers. Rev. 6 17 September 2015 Product data sheet 1. General description The provides two low-power, low-voltage buffers. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise

More information

Hex inverter with open-drain outputs

Hex inverter with open-drain outputs Rev. 6 0 November 20 Product data sheet. General description The provides six inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low wired-or

More information

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic

More information

Bus buffer/line driver; 3-state

Bus buffer/line driver; 3-state Rev. 12 2 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).

More information

Octal bus transceiver; 3-state

Octal bus transceiver; 3-state Rev. 02 7 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive

More information

74HC30-Q100; 74HCT30-Q100

74HC30-Q100; 74HCT30-Q100 Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

Dual supply buffer/line driver; 3-state

Dual supply buffer/line driver; 3-state Rev. 1 21 December 2015 Product data sheet 1. General description The is a dual supply non-inverting buffer/line driver with 3-state output. It features one input (A), an output (Y), an output enable input

More information

4-bit dual-supply buffer/level translator; 3-state

4-bit dual-supply buffer/level translator; 3-state Rev. 1 18 December 017 Product data sheet 1 General description Features and benefits The is a -bit, dual-supply level translating buffer with -state outputs. It features four data inputs (An and B), four

More information

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate. Rev. 6 31 July 2012 Product data sheet 1. General description The provides a single 3-input EXCLUSIVE-OR gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

More information

74LVC07A-Q100. Hex buffer with open-drain outputs

74LVC07A-Q100. Hex buffer with open-drain outputs Rev. October 202 Product data sheet. General description The provides six non-inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low wired-or

More information

4-bit dual supply translating transceiver; 3-state

4-bit dual supply translating transceiver; 3-state Rev. 25 September 207 Product data sheet General description 2 Features and benefits The is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight -bit input-output

More information

The 74LVC10A provides three 3-input NAND functions.

The 74LVC10A provides three 3-input NAND functions. Triple 3-input NND gate Rev. 5 7 November 20 Product data sheet. General description The provides three 3-input NND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows

More information

74LVC8T245; 74LVCH8T245

74LVC8T245; 74LVCH8T245 Rev. 3 December 11 Product data sheet 1. General description The are -bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output

More information

Low-power configurable multiple function gate

Low-power configurable multiple function gate Rev. 2 16 September 2015 Product data sheet 1. General description The is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions

More information

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state Rev. 6 10 July 2012 Product data sheet 1. General description The is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. Incorporates

More information

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop. Rev. 2 12 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH

More information

Single dual-supply translating 2-input OR with strobe

Single dual-supply translating 2-input OR with strobe Rev. 1 10 October 2018 Product data sheet 1. General description The is a single dual-supply translating 2-input OR with strobe inputs. It features two data input pins (A, B), two strobe input pins (STRA,

More information

Octal buffer/line driver; 3-state

Octal buffer/line driver; 3-state Rev. 4 1 March 2016 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC244 and 74HCT244. The is an octal non-inverting buffer/line

More information

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops

More information

Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state Rev. 4 25 November 2011 Product data sheet 1. General description The is an octal non-inverting buffer/line driver with 5 V tolerant inputs

More information

74AVCH General description. 2. Features and benefits. 16-bit transceiver with direction pin; 3.6 V tolerant; 3-state

74AVCH General description. 2. Features and benefits. 16-bit transceiver with direction pin; 3.6 V tolerant; 3-state Rev. 3 8 January 2013 Product data sheet 1. General description The is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features

More information

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer Rev. 1 23 April 2018 Product data sheet 1 General description 2 Features and benefits The is a suitable for use in clock distribution. It has a data input (A), four data outputs (Yn) and an output enable

More information

Single supply translating buffer/line driver; 3-state

Single supply translating buffer/line driver; 3-state Rev. 1 22 November 2017 Product data sheet 1 General description 2 Features and benefits 3 pplications The is a single, level translating buffer/line driver with 3-state output. The low threshold inputs

More information

Low-power configurable multiple function gate

Low-power configurable multiple function gate Rev. 8 23 September 2015 Product data sheet 1. General description The provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the

More information

74HC2G08-Q100; 74HCT2G08-Q100

74HC2G08-Q100; 74HCT2G08-Q100 Rev. 1 11 November 2013 Product data sheet 1. General description The is a dual 2-input ND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to s in

More information

74LVC8T245-Q100; 74LVCH8T245-Q100

74LVC8T245-Q100; 74LVCH8T245-Q100 7LVCT5-Q1; 7LVCHT5-Q1 Rev. 1 1 March 13 Product data sheet 1. General description The 7LVCT5-Q1; 7LVCHT5-Q1 are -bit dual supply translating transceivers with 3-state outputs that enable bidirectional

More information

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting Rev. 5 2 February 2016 Product data sheet 1. General description The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn causes the outputs

More information

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting Rev. 3 9 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable

More information

74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.

74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate. Rev. 1 20 March 2013 Product data sheet 1. General description The is a triple 3-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators

More information

2-input single supply translating NAND gate

2-input single supply translating NAND gate Rev. 1 22 November 2017 Product data sheet 1 General description 2 Features and benefits 3 pplications The is a single, level translating 2-input NND gate. The low threshold inputs support 1.8 V input

More information

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop. Rev. 12 5 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH

More information

Low-power triple buffer with open-drain output

Low-power triple buffer with open-drain output Rev. 2 5 October 2016 Product data sheet 1. General description The is a triple non-inverting buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain

More information

74ALVCH V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

74ALVCH V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Rev. 5 9 July 2012 Product data sheet 1. General description The is 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.

More information

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state Rev. 2 16 March 2015 Product data sheet 1. General description The is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.

More information

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter.

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter. Rev. 1 22 August 2012 Product data sheet 1. General description The is a single buffer and single inverter. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

More information

74HC1G32-Q100; 74HCT1G32-Q100

74HC1G32-Q100; 74HCT1G32-Q100 Rev. 1 8 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G32-Q100 and 74HCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input

More information

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current

More information

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description The is a 1-of-2 non-inverting demultiplexer with a 3-state output. The

More information

Low-power dual Schmitt trigger inverter

Low-power dual Schmitt trigger inverter Rev. 1 9 October 2014 Product data sheet 1. General description The is a dual inverter with Schmitt-trigger inputs. It transforms slowly changing input signals into sharply defined, jitter-free output

More information

Low-power buffer/line driver; 3-state

Low-power buffer/line driver; 3-state Rev. 6 15 ugust 2012 Product data sheet 1. General description The provides a single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).

More information

74HC541; 74HCT541. Octal buffer/line driver; 3-state

74HC541; 74HCT541. Octal buffer/line driver; 3-state Rev. 4 3 March 2016 Product data sheet 1. General description 2. Features and benefits The is an octal non-inverting buffer/line driver with 3-state outputs. The device features two output enables (OE1

More information

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state Rev. 5 17 November 2011 Product data sheet 1. General description The is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications.

More information

74LVC541A-Q100. Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

74LVC541A-Q100. Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state Rev. 2 4 March 2013 Product data sheet 1. General description The is an octal non-inverting buffer/line driver with 5 V tolerant inputs

More information

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. Rev. 3 16 August 2013 Product data sheet 1. General description The is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.

More information

7-stage binary ripple counter

7-stage binary ripple counter Rev. 9 28 April 2016 Product data sheet 1. General description The is a with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).

More information

74LVT244B; 74LVTH244B

74LVT244B; 74LVTH244B Rev. 4 14 June 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number 74LVT244BD 74LVTH244BD 74LVT244BDB 74LVTH244BDB 74LVT244BPW

More information

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This

More information

74HC2G125; 74HCT2G125

74HC2G125; 74HCT2G125 Rev. 5 17 March 2014 Product data sheet 1. General description 2. Features and benefits The 74HC2G125; 74HC2G125 are dual buffer/line drivers with 3-state outputs controlled by the output enable inputs

More information

74HC1G02-Q100; 74HCT1G02-Q100

74HC1G02-Q100; 74HCT1G02-Q100 Rev. 1 7 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G02-Q100 and 74HCT1G02-Q100 are high speed Si-gate CMOS devices. They provide a 2-input

More information

74LVC16244A; 74LVCH16244A

74LVC16244A; 74LVCH16244A Rev. 14 15 June 2017 Product data sheet 1 General description 2 Features and benefits The are 16-bit non-inverting buffer/line drivers with 3-state bus compatible outputs. The device can be used as four

More information

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02. Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC

More information

Low-power buffer with voltage-level translator

Low-power buffer with voltage-level translator Rev. 1 28 November 2017 Product data sheet 1 General description 2 Features and benefits The provides the single buffer function. This device ensures a very low static and dynamic power consumption across

More information

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state Rev. 6 1 February 2016 Product data sheet 1. General description The is a dual 4-bit multiplexer, each with four binary inputs (ni0 to ni3), an output enable input (noe) and shared select inputs (S0 and

More information

4-bit magnitude comparator

4-bit magnitude comparator Rev. 6 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a that compares two 4-bit words, A and B, and determines whether A is greater than

More information

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate Rev. 5 14 March 2018 Product data sheet 1 General description 2 Features 3 Ordering information Table 1. Ordering information Type number 74HC1G08GW 74HCT1G08GW 74HC1G08GV 74HCT1G08GV The is a single.

More information

Low-power 2-input NAND gate. The 74AUP1G00 provides the single 2-input NAND function.

Low-power 2-input NAND gate. The 74AUP1G00 provides the single 2-input NAND function. Rev. 6 27 June 2012 Product data sheet 1. General description The provides the single 2-input NND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

More information

74AHC2G241; 74AHCT2G241

74AHC2G241; 74AHCT2G241 Rev. 3 13 May 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device. The is a dual non-inverting buffer/line driver with

More information

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86. Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.

More information

4-bit dual-supply buffer/level translator; 3-state

4-bit dual-supply buffer/level translator; 3-state Rev. July 018 Product data sheet 1. General description. Features and benefits The is a -bit, dual-supply level translating buffer with -state outputs. It features four data inputs (An and B), four data

More information

74AVC1T General description. 2 Features and benefits. 1-to-4 fan-out buffer

74AVC1T General description. 2 Features and benefits. 1-to-4 fan-out buffer Rev. 1 3 April 1 Product data sheet 1 General description Features and benefits The is a translating suitable for use in clock distribution. It has dual supplies (V CC(A) and V CC(B) ) for voltage translation.

More information

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output

More information

74HC153-Q100; 74HCT153-Q100

74HC153-Q100; 74HCT153-Q100 Rev. 3 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each

More information

74HC365; 74HCT365. Hex buffer/line driver; 3-state

74HC365; 74HCT365. Hex buffer/line driver; 3-state Rev. 4 27 January 2016 Product data sheet 1. General description 2. Features and benefits The is a hex buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn

More information

74ALVC04. 1 General description. 2 Features and benefits. 3 Ordering information. Hex inverter

74ALVC04. 1 General description. 2 Features and benefits. 3 Ordering information. Hex inverter Rev. 3 5 October 207 Product data sheet General description 2 Features and benefits 3 Ordering information Table. Ordering information Type number Package The is a high-performance, low-power, low-voltage,

More information

The 74ABT125 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT125 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. 74BT25 Rev. 6 3 November 20 Product data sheet. General description The 74BT25 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The

More information

Low-power dual supply translating buffer

Low-power dual supply translating buffer Rev. 5 4 September 2013 Product data sheet 1. General description The provides a single buffer with two separate supply voltages. Input is designed to track V CC(). Output Y is designed to track V CC(Y).

More information

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function. Rev. 04 2 May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified

More information

74AHC541-Q100; 74AHCT541-Q100

74AHC541-Q100; 74AHCT541-Q100 74HC541-Q100; 74HCT541-Q100 Rev. 1 6 June 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. The are octal non-inverting buffer/line drivers with 3-state bus compatible

More information

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers. Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0

More information

Low-power 2-input AND gate with open-drain

Low-power 2-input AND gate with open-drain Rev. 5 29 September 2017 Product data sheet 1 General description 2 Features and benefits The provides the single 2-input ND gate with an open-drain output. The output of the device is an open-drain and

More information

74HC32-Q100; 74HCT32-Q100

74HC32-Q100; 74HCT32-Q100 Rev. 1 1 ugust 2012 Product data sheet 1. General description The is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages

More information

74AHC1G125; 74AHCT1G125

74AHC1G125; 74AHCT1G125 Rev. 10 23 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G125 and 74HCT1G125 are high-speed Si-gate CMOS devices. They provide one non-inverting

More information

74LVC126A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74LVC126A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state Rev. 9 2 ugust 20 Product data sheet. General description 2. Features and benefits 3. Ordering information Table. Ordering information Type number Package The consists of four non-inverting buffers/line

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 14 15 December 2016 Product data sheet 1. General description The is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE

More information

74AHC2G126; 74AHCT2G126

74AHC2G126; 74AHCT2G126 Rev. 04 27 pril 2009 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC2G126 and 74HCT2G126 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line

More information

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device. Rev. 05 20 December 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The has octal non-inverting buffer/line drivers with 3-state

More information

74AHC1G126; 74AHCT1G126

74AHC1G126; 74AHCT1G126 Rev. 8 23 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G126 and 74HCT1G126 are high-speed Si-gate CMOS devices. They provide one non-inverting

More information