74AVC1T General description. 2 Features and benefits. 1-to-4 fan-out buffer

Size: px
Start display at page:

Download "74AVC1T General description. 2 Features and benefits. 1-to-4 fan-out buffer"

Transcription

1 Rev. 1 3 April 1 Product data sheet 1 General description Features and benefits The is a translating suitable for use in clock distribution. It has dual supplies (V CC(A) and V CC(B) ) for voltage translation. It also has a data input (A), four data outputs (Yn) and an output enable input (OE). V CC(A) and V CC(B) can be independently supplied at any voltage between. V and 3. V. It makes the device suitable for low voltage translation between any of the following voltages:. V, 1. V, 1.5 V, 1. V,.5 V and 3.3 V. The levels of A and OE are referenced to V CC(A), outputs Yn are referenced to V CC(B). This supply configuration ensures that the fanned out signals can be used in level shifting. A HIGH on OE causes all outputs to be pulled LOW via pull-down resistors, a LOW on OE disconnects the pull-down resistors and enables all outputs. Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. The I OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. Wide supply voltage range: V CC(A) :. V to 3. V V CC(B) :. V to 3. V Complies with JEDEC standards: JESD-1 (. V to 1.3 V) JESD-11 (.9 V to 1.5 V) JESD-7 (1. V to 1.95 V) JESD-5 (1. V to.7 V) JESD-B (.7 V to 3. V) ESD protection: HBM ANSI/ESDA/JEDEC JS-1 Class exceeds kv CDM JESD-C11 exceeds 1 V Maximum data rates: 3 Mbit/s ( 1. V to 3.3 V translation) Mbit/s ( 1.1 V to 3.3 V translation) Mbit/s ( 1.1 V to.5 V translation) Mbit/s ( 1.1 V to 1. V translation) 15 Mbit/s ( 1.1 V to 1.5 V translation) 1 Mbit/s ( 1.1 V to 1. V translation) Latch-up performance exceeds 1 ma per JESD 7 Class II Inputs accept voltages up to 3. V Specified from - C to +5 C and - C to +15 C

2 3 Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version DP - C to +15 C TSSOP1 plastic thin shrink small outline package; 1 leads; body width 3 mm GU33 - C to +15 C XQFN1 plastic extremely thin small outline package; no leads; 1 terminals; body 1. x 1.3 x.33 mm SOT55-1 SOT13-1 Marking Table. Marking codes Type number DP GU33 Marking code Bc Bc 5 Functional diagram A V CC(A) V CC(B) 9 Y Rpd Y3 Rpd OE 7 Y Rpd Y1 Rpd Pin numbers are shown for TSSOP1 package only. Figure 1. Logic symbol aaa-71 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. /

3 Pinning information.1 Pinning terminal 1 index area VCC(A) 1 VCC(B) 9 Y A 1 7 Y3 V CC(A) 1 1 V CC(B) GND Y A 9 Y GND 3 Y3 OE GND 7 5 Y Y1 3 OE GND 5 Y1 aaa-71 aaa-715 Figure. Pin configuration SOT55-1 (TSSOP1) Transparent top view Figure 3. Pin configuration SOT13-1 (XQFN1). Pin description Table 3. Pin description Symbol Pin Description SOT55-1 SOT13-1 V CC(A) 1 1 supply voltage A A 1 data input (referenced to V CC(A) ) GND [1] 3, 5, ground ( V) OE 3 output enable input (active LOW) (referenced to V CC(A) ) Y1, Y, Y3, Y, 7,, 9 5,, 7, data outputs (referenced to V CC(B) ) V CC(B) 1 9 supply voltage B [1] All GND pins must be connected to ground ( V). All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 3 /

4 7 Functional description Table. Function table [1] Inputs Output OE A Yn L L L L H H H X L [1] H = HIGH voltage level; L = LOW voltage level; X = don t care. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 13). Voltages are referenced to GND (ground = V). Symbol Parameter Conditions Min Max Unit V CC(A) supply voltage A V V CC(B) supply voltage B V V I V O input voltage output voltage OE = LOW OE = HIGH [1] [1] [] [1] V -.5 V CC(B) +.5 V V I IK input clamping current V I < V -5 - ma I OK output clamping current V O < V -5 - ma I O output current V O = V to V CC(B) - ±5 ma I CC supply current I CC(A) or I CC(B) - 1 ma I GND ground current -1 - ma T stg storage temperature C P tot total power dissipation T amb = - C to +15 C SOT55-1 package SOT13-1 package [3] [] - 5 mw - 5 mw [1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. [] V CC(B) +.5 V should not exceed. V. [3] For SOT55-1 package: above 1 C, the value of P tot derates linearly with.3 mw/k. [] For SOT13-1 package: above 1 C, the value of P tot derates linearly with 5. mw/k. All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. /

5 9 Recommended operating conditions Table. Recommended operating conditions Symbol Parameter Conditions Min Max Unit V CC(A) supply voltage A. 3. V V CC(B) supply voltage B. 3. V V I input voltage 3. V V O output voltage OE = LOW V CCB V OE = HIGH 3. V T amb ambient temperature C Δt/ΔV input transition rise and fall rate V CC(A) =. V to 3. V ns/v 1 Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = V). Symbol Parameter Conditions V OH V OL HIGH-level output voltage LOW-level output voltage V I = V IH or V IL T amb = 5 C Min Typ Max I O = -1.5 ma; V CC(B) =. V V V I = V IH or V IL I I input leakage current A, OE input; V I = V or 3. V; V CC(A) = V CC(B) =. V to 3. V I OFF power-off leakage current V I or V O = V to 3. V; V CC(A) or V CC(B) = V I O = 1.5 ma; V CC(B) =. V V Unit - ±.5 ±.5 μa - ±.1 ±1 μa R pd pull-down resistance kω C I input capacitance A, OE input; V I = V or 3.3 V; V CC(A) = 3.3 V pf C O output capacitance Yn; V O = 3.3 V or V; V CC(B) = 3.3 V pf Table. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = V). Symbol Parameter Conditions T amb = - C to +5 C T amb = - C to +15 C Min Max Min Max Unit V IH HIGH-level input voltage A, OE input V CC(A) =. V.7V CC(A) -.7V CC(A) - V V CC(A) = 1.1 V to 1.95 V.5V CC(A) -.5V CC(A) - V V CC(A) =.3 V to.7 V V V CC(A) = 3. V to 3. V - - V All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 5 /

6 Symbol Parameter Conditions T amb = - C to +5 C T amb = - C to +15 C Min Max Min Max Unit V IL LOW-level input voltage A, OE input V CC(A) =. V -.3V CC(A) -.3V CC(A) V V CC(A) = 1.1 V to 1.95 V -.35V CC(A) -.35V CC(A) V V CC(A) =.3 V to.7 V V V CC(A) = 3. V to 3. V V V OH HIGH-level output voltage V I = V IH or V IL I O = -1 μa; V CC(B) =. V to 3. V V CC(B) V CC(B) V I O = -3 ma; V CC(B) = 1.1 V V I O = - ma; V CC(B) = 1. V V I O = - ma; V CC(B) = 1.5 V V I O = -9 ma; V CC(B) =.3 V V I O = -1 ma; V CC(B) = 3. V V V OL LOW-level output voltage V I = V IH or V IL I O = 1 μa; V CC(B) =. V to 3. V V I O = 3 ma; V CC(B) = 1.1 V V I O = ma; V CC(B) = 1. V V I O = ma; V CC(B) = 1.5 V V I O = 9 ma; V CC(B) =.3 V V I O = 1 ma; V CC(B) = 3. V V I I input leakage current A, OE input; V I = V or 3. V; V CC(A) = V CC(B) =. V to 3. V - ±1 - ±5 μa I OFF power-off leakage current V I or V O = V to 3. V; V CC(B) = V; V CC(A) =. V to 3. V - ±5 - ±3 μa I CC(A) supply current A V I = V or V CC(A) ; I O = A; V CC(A) =. V to 3. V; V CC(B) =. V to 3. V I CC(B) supply current B V I = V or V CC(A) ; I O = A; V CC(A) =. V to 3. V; V CC(B) =. V to 3. V μa μa All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. /

7 11 Dynamic characteristics Table 9. Typical dynamic characteristics at V CC(A) =. V and T amb = 5 C [1] Voltages are referenced to GND (ground = V); for test circuit, see Figure ; for waveforms, see Figure and Figure 5. Symbol Parameter Conditions V CC(B). V 1. V 1.5 V 1. V.5 V 3.3 V Unit propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns [1] is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. Table 1. Typical dynamic characteristics at V CC(B) =. V and T amb = 5 C [1] Voltages are referenced to GND (ground = V); for test circuit, see Figure ; for waveforms, see Figure and Figure 5. Symbol Parameter Conditions V CC(A). V 1. V 1.5 V 1. V.5 V 3.3 V Unit propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns [1] is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 7 /

8 Table 11. Dynamic characteristics for temperature range - C to +5 C [1] Voltages are referenced to GND (ground = V); for test circuit, see Figure ; for waveforms, see Figure and Figure 5. Symbol Parameter Conditions V CC(A) = 1.1 V to 1.3 V V CC(B) 1. V±.1 V 1.5 V±.1 V 1. V±.15 V.5 V±. V 3.3 V±.3 V Min Max Min Max Min Max Min Max Min Max Unit propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns V CC(A) = 1. V to 1. V propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns V CC(A) = 1.5 V to 1.95 V propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns V CC(A) =.3 V to.7 V propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns V CC(A) = 3. V to 3. V propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns [1] is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. /

9 Table 1. Dynamic characteristics for temperature range - C to +15 C [1] Voltages are referenced to GND (ground = V); for test circuit, see Figure ; for waveforms, see Figure and Figure 5. Symbol Parameter Conditions V CC(A) = 1.1 V to 1.3 V V CC(B) 1. V±.1 V 1.5 V±.1 V 1. V±.15 V.5 V±. V 3.3 V±.3 V Min Max Min Max Min Max Min Max Min Max Unit propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns V CC(A) = 1. V to 1. V propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns V CC(A) = 1.5 V to 1.95 V propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns V CC(A) =.3 V to.7 V propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns V CC(A) = 3. V to 3. V propagation delay A to Yn ns t dis disable time OE to Yn ns t en enable time OE to Yn ns [1] is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 9 /

10 Table 13. Dynamic characteristics for temperature range - C to +5 C and - C to +15 C Voltages are referenced to GND (ground = V); for test circuit, see Figure. Symbol Parameter Conditions T amb = - C to +5 C V CC(A) = V CC(B) 1. V±.1 V 1.5 V±.1 V 1. V±.15 V.5 V±. V 3.3 V±.3 V Max Max Max Max Max Unit t sk(o) output skew time between any output ns T amb = - C to +15 C t sk(o) output skew time between any output ns [1] [] Table 1. Typical power dissipation capacitance at T amb = 5 C V Symbol Parameter Conditions CC(A) = V CC(B) Unit C PD power dissipation capacitance. V 1. V 1.5 V 1. V.5 V 3.3 V Yn; outputs enabled pf Yn; outputs disabled pf [1] C PD is used to determine the dynamic power dissipation (P D in μw). P D = C PD V CC fi + Σ(C L V CC fo ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = load capacitance in pf; V CC = supply voltage in V; Σ(C L V CC fo ) = sum of the outputs. [] f i = 1 MHz; V I = GND to V CC(A) ; t r = t f = 1 ns; C L = pf; R L = Ω. All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 1 /

11 11.1 Waveforms and test circuit V I A input GND V M V M t PHL t PLH V OH Yn output V M V M Measurement points are given in Table 15. V OL and V OH are typical output voltage levels that occur with the output load. Figure. The data input (A) to output (Yn) propagation delay times V OL aaa-717 V I OE input V M GND t PLZ t PZL output LOW-to-OFF OFF-to-LOW V OH V OL V X V M t PHZ t PZH output HIGH-to-OFF OFF-to-HIGH V OH GND outputs enabled V Y outputs disabled V M outputs enabled Measurement points are given in Table 15. V OL and V OH are typical output voltage levels that occur with the output load. Figure 5. Enable and disable times aaa-19 Table 15. Measurement points Supply voltage Input Output V CC(A), V CC(B) V M V M V X V Y. V to 1. V.5V CC(A).5V CC(B) V OL +.1 V V OH -.1 V 1.5 V to.7 V.5V CC(A).5V CC(B) V OL +.15 V V OH -.15 V 3. V to 3. V.5V CC(A).5V CC(B) V OL +.3 V V OH -.3 V All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 11 /

12 t W V I negative pulse V 9 % V M 1 % V M t f t r t r t f V I positive pulse V 1 % V M 9 % t W V M V EXT V CC G V I DUT V O RL RT CL RL Test data is given in Table 1 R L = Load resistance. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance. V EXT = External voltage for measuring switching times. Figure. Test circuit for measuring switching times 1aae331 Table 1. Test data Supply voltage Input Load V EXT V CC(A), V CC(B) V I Δt/ΔV [1] C L R L t PLH, t PHL t PZH, t PHZ t PZL, t PLZ. V to 1. V V CC(A) 1. ns/v 15 pf kω open GND V CC(B) 1.5 V to.7 V V CC(A) 1. ns/v 15 pf kω open GND V CC(B) 3. V to 3. V V CC(A) 1. ns/v 15 pf kω open GND V CC(B) [1] dv/dt 1. V/ns All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 1 /

13 11. Typical propagation delay characteristics (ns) 3 aaa-939 (ns) 3 aaa () 1 1 () () () 1 () () a. Propagation delay (A to Yn); V CC(B) =. V V CC(A) =. V () V CC(A) = 1. V V CC(A) = 1.5 V () V CC(A) = 1. V V CC(A) =.5 V () V CC(A) = 3.3 V b. Propagation delay (A to Yn); V CC(A) =. V V CC(B) =. V () V CC(B) = 1. V V CC(B) = 1.5 V () V CC(B) = 1. V V CC(B) =.5 V () V CC(B) = 3.3 V Figure 7. Typical propagation delay versus load capacitance; T amb = 5 C All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 13 /

14 1 aaa aaa-191 t PLH (ns) () () t PHL (ns) () () a. LOW to HIGH propagation delay (A to Yn); V CC(A) = 1. V b. HIGH to LOW propagation delay (A to Yn); V CC(A) = 1. V V CC(B) = 1. V () V CC(B) = 1.5 V V CC(B) = 1. V () V CC(B) =.5 V V CC(B) = 3.3 V Figure. Typical propagation delay versus load capacitance; T amb = 5 C All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 1 /

15 1 aaa aaa-191 t PLH (ns) t PHL (ns) () () () () a. LOW to HIGH propagation delay (A to Yn); V CC(A) = 1.5 V b. HIGH to LOW propagation delay (A to Yn); V CC(A) = 1.5 V 1 aaa aaa-191 t PLH (ns) t PHL (ns) () () () () c. LOW to HIGH propagation delay (A to Yn); V CC(A) = 1. V V CC(B) = 1. V () V CC(B) = 1.5 V V CC(B) = 1. V () V CC(B) =.5 V V CC(B) = 3.3 V d. HIGH to LOW propagation delay (A to Yn); V CC(A) = 1. V Figure 9. Typical propagation delay versus load capacitance; T amb = 5 C All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 15 /

16 1 aaa aaa-191 t PLH (ns) t PHL (ns) () () () () a. LOW to HIGH propagation delay (A to Yn); V CC(A) =.5 V b. HIGH to LOW propagation delay (A to Yn); V CC(A) =.5 V 1 aaa aaa-19 t PLH (pf) t PHL (ns) () () () () c. LOW to HIGH propagation delay (A to Yn); V CC(A) = 3.3 V V CC(B) = 1. V () V CC(B) = 1.5 V V CC(B) = 1. V () V CC(B) =.5 V V CC(B) = 3.3 V d. HIGH to LOW propagation delay (A to Yn); V CC(A) = 3.3 V Figure 1. Typical propagation delay versus load capacitance; T amb = 5 C All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 1 /

17 1 Package outline TSSOP1: plastic thin shrink small outline package; 1 leads; body width 3 mm SOT55-1 D E A X c y H E v M A Z 1 A A1 (A 3 ) A pin 1 index L p θ 1 5 e b p w M L detail X.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT A max. 1 mm A A 3 b p c D E () e H E L L p v w y Z θ Notes 1. Plastic or metal protrusions of.15 mm maximum per side are not included.. Plastic or metal protrusions of.5 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT Figure 11. Package outline SOT55-1 (TSSOP1) All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 17 /

18 XQFN1: plastic extremely thin small outline package; no leads; 1 terminals; body 1. x 1.3 x.33 mm SOT13-1 D B A ball A1 index area E A A 1 A3 detail X e 1 b 3 5 Ø v Ø w C C A B y 1 C C y L 1 7 e ball A1 index area k 1 9 L 1 X L mm scale Dimensions (mm are the original dimensions) Unit A A 1 A3 b D E e e 1 k L L1 L v w y y 1 mm max nom min Outline version SOT References IEC JEDEC JEITA MO Note 1. Plastic or metal protrusions of.75 mm maximum per side are not included. Figure 1. Package outline SOT13-1 (XQFN1) European projection sot13-1_po Issue date All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 1 /

19 13 Abbreviations Table 17. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model 1 Revision history Table 1. Revision history Document ID Release date Data sheet status Change notice Supersedes v.1 13 Product data sheet - - All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 19 /

20 15 Legal information 15.1 Data sheet status Document status [1][] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 13) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. /

21 Non-automotive qualified products Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations A non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Nexperia B.V. 1. All rights reserved. 1 /

22 Contents 1 General description... 1 Features and benefits Ordering information... Marking... 5 Functional diagram... Pinning information Pinning...3. Pin description Functional description... Limiting values... 9 Recommended operating conditions Static characteristics Dynamic characteristics Waveforms and test circuit Typical propagation delay characteristics Package outline Abbreviations Revision history Legal information... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. Nexperia B.V. 1. All rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Date of release: 3 April 1 Document identifier:

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer Rev. 1 23 April 2018 Product data sheet 1 General description 2 Features and benefits The is a suitable for use in clock distribution. It has a data input (A), four data outputs (Yn) and an output enable

More information

Single dual-supply translating 2-input OR with strobe

Single dual-supply translating 2-input OR with strobe Rev. 1 10 October 2018 Product data sheet 1. General description The is a single dual-supply translating 2-input OR with strobe inputs. It features two data input pins (A, B), two strobe input pins (STRA,

More information

The 74AXP1G04 is a single inverting buffer.

The 74AXP1G04 is a single inverting buffer. Rev. 1 25 August 2014 Product data sheet 1. General description The is a single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This

More information

4-bit dual-supply buffer/level translator; 3-state

4-bit dual-supply buffer/level translator; 3-state Rev. 1 18 December 017 Product data sheet 1 General description Features and benefits The is a -bit, dual-supply level translating buffer with -state outputs. It features four data inputs (An and B), four

More information

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers. Rev. 1 2 November 2015 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. The provides two buffers. 2. Features and benefits 3. Ordering information Wide supply voltage

More information

The 74AUP2G34 provides two low-power, low-voltage buffers.

The 74AUP2G34 provides two low-power, low-voltage buffers. Rev. 6 17 September 2015 Product data sheet 1. General description The provides two low-power, low-voltage buffers. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise

More information

Octal bus transceiver; 3-state

Octal bus transceiver; 3-state Rev. 2 3 November 2016 Product data sheet 1. General description The is an 8-bit transceiver with 3-state outputs. The device features an output enable (OE) and send/receive (DIR) for direction control.

More information

74AVC4T774PW. 4-bit dual supply translating transceiver; 3-state

74AVC4T774PW. 4-bit dual supply translating transceiver; 3-state Rev. 1 25 September 2017 Product data sheet 1 General description 2 Features and benefits The is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight 1-bit input-output

More information

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

Low-power configurable multiple function gate

Low-power configurable multiple function gate Rev. 2 16 September 2015 Product data sheet 1. General description The is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions

More information

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter.

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter. Rev. 1 22 August 2012 Product data sheet 1. General description The is a single buffer and single inverter. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

More information

7-stage binary ripple counter

7-stage binary ripple counter Rev. 9 28 April 2016 Product data sheet 1. General description The is a with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).

More information

Low-power dual Schmitt trigger inverter

Low-power dual Schmitt trigger inverter Rev. 1 9 October 2014 Product data sheet 1. General description The is a dual inverter with Schmitt-trigger inputs. It transforms slowly changing input signals into sharply defined, jitter-free output

More information

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop. Rev. 2 12 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH

More information

The 74LV08 provides a quad 2-input AND function.

The 74LV08 provides a quad 2-input AND function. Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.

More information

4-bit dual-supply buffer/level translator; 3-state

4-bit dual-supply buffer/level translator; 3-state Rev. July 018 Product data sheet 1. General description. Features and benefits The is a -bit, dual-supply level translating buffer with -state outputs. It features four data inputs (An and B), four data

More information

Dual supply buffer/line driver; 3-state

Dual supply buffer/line driver; 3-state Rev. 1 21 December 2015 Product data sheet 1. General description The is a dual supply non-inverting buffer/line driver with 3-state output. It features one input (A), an output (Y), an output enable input

More information

Low-power triple buffer with open-drain output

Low-power triple buffer with open-drain output Rev. 2 5 October 2016 Product data sheet 1. General description The is a triple non-inverting buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain

More information

74LVC1G125-Q100. Bus buffer/line driver; 3-state

74LVC1G125-Q100. Bus buffer/line driver; 3-state Rev. 2 8 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).

More information

Low-power configurable multiple function gate

Low-power configurable multiple function gate Rev. 8 23 September 2015 Product data sheet 1. General description The provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the

More information

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop. Rev. 12 5 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH

More information

Bus buffer/line driver; 3-state

Bus buffer/line driver; 3-state Rev. 12 2 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).

More information

4-bit dual supply translating transceiver; 3-state

4-bit dual supply translating transceiver; 3-state Rev. 25 September 207 Product data sheet General description 2 Features and benefits The is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight -bit input-output

More information

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device. 74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function

More information

2-input single supply translating NAND gate

2-input single supply translating NAND gate Rev. 1 22 November 2017 Product data sheet 1 General description 2 Features and benefits 3 pplications The is a single, level translating 2-input NND gate. The low threshold inputs support 1.8 V input

More information

74AVC20T245-Q General description. 2. Features and benefits

74AVC20T245-Q General description. 2. Features and benefits 20-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 1 7 April 2016 Product data sheet 1. General description The is a 20 bit, dual supply transceiver that enables

More information

2-input EXCLUSIVE-OR gate

2-input EXCLUSIVE-OR gate Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output

More information

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1. Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance

More information

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer. Rev. 1 18 November 2013 Product data sheet 1. General description The provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

More information

Single supply translating buffer/line driver; 3-state

Single supply translating buffer/line driver; 3-state Rev. 1 22 November 2017 Product data sheet 1 General description 2 Features and benefits 3 pplications The is a single, level translating buffer/line driver with 3-state output. The low threshold inputs

More information

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting Rev. 5 2 February 2016 Product data sheet 1. General description The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn causes the outputs

More information

Octal buffer/line driver; 3-state

Octal buffer/line driver; 3-state Rev. 4 1 March 2016 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC244 and 74HCT244. The is an octal non-inverting buffer/line

More information

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description The is a 1-of-2 non-inverting demultiplexer with a 3-state output. The

More information

74AVC32T General description. 2. Features and benefits

74AVC32T General description. 2. Features and benefits 32-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 1 16 January 2013 Product data sheet 1. General description The is a 32-bit transceiver with bidirectional

More information

74HC541; 74HCT541. Octal buffer/line driver; 3-state

74HC541; 74HCT541. Octal buffer/line driver; 3-state Rev. 4 3 March 2016 Product data sheet 1. General description 2. Features and benefits The is an octal non-inverting buffer/line driver with 3-state outputs. The device features two output enables (OE1

More information

Low-power dual supply buffer/line driver; 3-state

Low-power dual supply buffer/line driver; 3-state Rev. 2.1 23 July 2018 Product data sheet 1 General description 2 Features and benefits The is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with outpuable circuitry.

More information

74HC153-Q100; 74HCT153-Q100

74HC153-Q100; 74HCT153-Q100 Rev. 3 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each

More information

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting Rev. 3 9 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable

More information

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state Rev. 2 16 March 2015 Product data sheet 1. General description The is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 14 15 December 2016 Product data sheet 1. General description The is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE

More information

4-bit magnitude comparator

4-bit magnitude comparator Rev. 6 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a that compares two 4-bit words, A and B, and determines whether A is greater than

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output

More information

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW

More information

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. Rev. 3 16 August 2013 Product data sheet 1. General description The is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.

More information

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state Rev. 6 1 February 2016 Product data sheet 1. General description The is a dual 4-bit multiplexer, each with four binary inputs (ni0 to ni3), an output enable input (noe) and shared select inputs (S0 and

More information

Low-power dual PCB configurable multiple function gate

Low-power dual PCB configurable multiple function gate Rev. 2 2 December 2015 Product data sheet 1. General description The is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the

More information

Low-power buffer with voltage-level translator

Low-power buffer with voltage-level translator Rev. 1 28 November 2017 Product data sheet 1 General description 2 Features and benefits The provides the single buffer function. This device ensures a very low static and dynamic power consumption across

More information

74HC365; 74HCT365. Hex buffer/line driver; 3-state

74HC365; 74HCT365. Hex buffer/line driver; 3-state Rev. 4 27 January 2016 Product data sheet 1. General description 2. Features and benefits The is a hex buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn

More information

74HC132-Q100; 74HCT132-Q100

74HC132-Q100; 74HCT132-Q100 Rev. 3 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate. Rev. 6 31 July 2012 Product data sheet 1. General description The provides a single 3-input EXCLUSIVE-OR gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

More information

Low-power Schmitt trigger inverter

Low-power Schmitt trigger inverter Rev. 1 28 August 2014 Product data sheet 1. General description The is a single inverter with Schmitt trigger input. It transforms slowly changing input signals into sharply defined, jitter-free output

More information

74LV03. 1 General description. 2 Features and benefits. 3 Ordering information. Quad 2-input NAND gate

74LV03. 1 General description. 2 Features and benefits. 3 Ordering information. Quad 2-input NAND gate Rev. 4 31 August 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number Package The is a low-voltage Si-gate CMOS device

More information

74HC107-Q100; 74HCT107-Q100

74HC107-Q100; 74HCT107-Q100 Rev. 2 26 January 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,

More information

74HC2G125; 74HCT2G125

74HC2G125; 74HCT2G125 Rev. 5 17 March 2014 Product data sheet 1. General description 2. Features and benefits The 74HC2G125; 74HC2G125 are dual buffer/line drivers with 3-state outputs controlled by the output enable inputs

More information

Dual supply configurable multiple function gate

Dual supply configurable multiple function gate Rev. 4 28 October 2016 Product data sheet 1. General description The is a dual supply configurable multiple function gate with Schmitt-trigger inputs. It features three inputs (A, B and C), an output (Y)

More information

74HC280; 74HCT bit odd/even parity generator/checker

74HC280; 74HCT bit odd/even parity generator/checker Rev. 3 15 September 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a 9-bit parity generator or checker. Both even and odd parity outputs are available.

More information

Triple inverting Schmitt trigger with 5 V tolerant input

Triple inverting Schmitt trigger with 5 V tolerant input Rev. 14 15 December 2016 Product data sheet 1. General description The provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply

More information

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate Rev. 3 5 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current

More information

74HC151-Q100; 74HCT151-Q100

74HC151-Q100; 74HCT151-Q100 Rev. 2 11 February 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output

More information

Low-power 2-input NAND gate. The 74AUP1G00 provides the single 2-input NAND function.

Low-power 2-input NAND gate. The 74AUP1G00 provides the single 2-input NAND function. Rev. 6 27 June 2012 Product data sheet 1. General description The provides the single 2-input NND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

More information

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger Rev. 4 12 May 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and

More information

74HC30-Q100; 74HCT30-Q100

74HC30-Q100; 74HCT30-Q100 Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

74LVC1G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger

74LVC1G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger Rev. 13 5 December 2016 Product data sheet 1. General description The is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs,

More information

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state Rev. 6 10 July 2012 Product data sheet 1. General description The is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. Incorporates

More information

74ALVCH V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

74ALVCH V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Rev. 5 9 July 2012 Product data sheet 1. General description The is 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.

More information

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops

More information

74HC126; 74HCT126. Quad buffer/line driver; 3-state

74HC126; 74HCT126. Quad buffer/line driver; 3-state Rev. 3 22 September 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad buffer/line driver with 3-state outputs controlled by the output enable

More information

74LVC2G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger

74LVC2G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger Rev. 11 15 December 2016 Product data sheet 1. General description The is a single positive-edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs,

More information

74ALVC04. 1 General description. 2 Features and benefits. 3 Ordering information. Hex inverter

74ALVC04. 1 General description. 2 Features and benefits. 3 Ordering information. Hex inverter Rev. 3 5 October 207 Product data sheet General description 2 Features and benefits 3 Ordering information Table. Ordering information Type number Package The is a high-performance, low-power, low-voltage,

More information

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function. Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They

More information

8-bit parallel-in/serial-out shift register

8-bit parallel-in/serial-out shift register Rev. 7 9 March 2016 Product data sheet 1. General description The is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When

More information

74AHC2G241; 74AHCT2G241

74AHC2G241; 74AHCT2G241 Rev. 3 13 May 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device. The is a dual non-inverting buffer/line driver with

More information

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate Rev. 5 14 March 2018 Product data sheet 1 General description 2 Features 3 Ordering information Table 1. Ordering information Type number 74HC1G08GW 74HCT1G08GW 74HC1G08GV 74HCT1G08GV The is a single.

More information

HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder

HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder Rev. 06 25 November 2009 Product data sheet 1. General description 2. Features 3. Applications The is a 4-bit, a 4-bit BCO to octal decoder with active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer.

More information

74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer

74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer Rev. 5 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each

More information

Low-power 2-input AND gate with open-drain

Low-power 2-input AND gate with open-drain Rev. 5 29 September 2017 Product data sheet 1 General description 2 Features and benefits The provides the single 2-input ND gate with an open-drain output. The output of the device is an open-drain and

More information

74AVC20T General description. 2. Features and benefits

74AVC20T General description. 2. Features and benefits 20-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 7 8 March 2012 Product data sheet 1. General description The is a 20-bit, dual supply transceiver that enables

More information

74HC109-Q100; 74HCT109-Q100

74HC109-Q100; 74HCT109-Q100 Rev. 1 28 September 2016 Product data sheet 1. General description The is a dual positive edge triggered JK flip-flop featuring individual nj and nk inputs. It has clock (ncp) inputs, set (nsd) and reset

More information

74HC1G125; 74HCT1G125

74HC1G125; 74HCT1G125 Rev. 6 6 September 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number 74HC1G125GW 74HCT1G125GW 74HC1G125GV 74HCT1G125GV

More information

74HC2G08-Q100; 74HCT2G08-Q100

74HC2G08-Q100; 74HCT2G08-Q100 Rev. 1 11 November 2013 Product data sheet 1. General description The is a dual 2-input ND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to s in

More information

74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger

74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger Rev. 4 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state Rev. 5 17 November 2011 Product data sheet 1. General description The is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications.

More information

74AUP1G04. 1 General description. 2 Features and benefits. Low-power inverter

74AUP1G04. 1 General description. 2 Features and benefits. Low-power inverter Rev. 9 8 June 2018 Product data sheet 1 General description 2 Features and benefits The provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input

More information

74HC1G32-Q100; 74HCT1G32-Q100

74HC1G32-Q100; 74HCT1G32-Q100 Rev. 1 8 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G32-Q100 and 74HCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input

More information

74AUP1G34. 1 General description. 2 Features and benefits. Low-power buffer

74AUP1G34. 1 General description. 2 Features and benefits. Low-power buffer 74UP1G34 Rev. 8 8 June 2018 Product data sheet 1 General description 2 Features and benefits The 74UP1G34 provides a low-power, low-voltage single buffer. Schmitt trigger action at all inputs makes the

More information

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current

More information

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers. Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0

More information

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state Rev. 7 pril 203 Product data sheet. General description The consists of four non-inverting buffers/line drivers with 3-state outputs (ny) that are controlled by the output enable input (noe). HIGH at noe

More information

Low-power buffer/line driver; 3-state

Low-power buffer/line driver; 3-state Rev. 6 15 ugust 2012 Product data sheet 1. General description The provides a single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).

More information

74LVC823A-Q General description. 2. Features and benefits

74LVC823A-Q General description. 2. Features and benefits 9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Rev. 1 15 September 2016 Product data sheet 1. General description The is a 9-bit D-type flip-flop with common clock

More information

The 74LVC1G02 provides the single 2-input NOR function.

The 74LVC1G02 provides the single 2-input NOR function. Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use

More information

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches with supplementary switches Rev. 03 16 December 2009 Product data sheet 1. General description 2. Features 3. Applications 4. Ordering information The is a dual 3-channel analog multiplexer/demultiplexer

More information

74HC1G02-Q100; 74HCT1G02-Q100

74HC1G02-Q100; 74HCT1G02-Q100 Rev. 1 7 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G02-Q100 and 74HCT1G02-Q100 are high speed Si-gate CMOS devices. They provide a 2-input

More information

Low-power inverter with open-drain output

Low-power inverter with open-drain output Rev. 8 12 February 2018 Product data sheet 1 General description 2 Features and benefits The provides the single inverting buffer with open-drain output. The output of the device is an open drain and can

More information

74HC2G14; 74HCT2G14. Dual inverting Schmitt trigger

74HC2G14; 74HCT2G14. Dual inverting Schmitt trigger Rev. 2 14 March 2014 Product data sheet 1. General description The is a dual inverter with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface

More information

74LVC126A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74LVC126A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state Rev. 9 2 ugust 20 Product data sheet. General description 2. Features and benefits 3. Ordering information Table. Ordering information Type number Package The consists of four non-inverting buffers/line

More information

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This

More information

74HC3G04; 74HCT3G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Triple inverter

74HC3G04; 74HCT3G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Triple inverter Rev. 5 26 November 2018 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package 74HC3G04DP 74HCT3G04DP 74HC3G04DC 74HCT3G04DC

More information