University of Tripoli / Tripoli - Libya. ** Centre for Solar Energy Research and Studies / Tripoli-Libya

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1 Analyss and Smulatn f ntrlavd Bst Cnvrtr fr Autmtv Applcatns Farag. S. Alargt **, Ahmd. S. Ashur * * Dpartmnt f Elctrcal and Elctrnc Engnrng Unvrsty f Trpl / Trpl - bya. ** Cntr fr Slar Enrgy Rsarch and Studs / Trpl-bya Abstract - Ths papr studs a dsgn and smulatn f mult-phas ntrlavd bst DC-DC cnvrtr. Th cntrl stratgy f th cnvrtr s basd n a vltag md-cntrlld Puls Wdth Mdulatn (PWM) wth a Prprtnal-ntgral- Drvatv (PD) cntrllr. Th prpsd cnvrtr has a 1KW pwr and 42 utput vltag t satsfy th rqurmnts f usag n 14/42 pwr systm usd n autmtv applcatns. Ths archtctur s cnsdrd t b tchncally a vabl slutn fr autmtv dual-vltag pwr systm fr passngr car n th nar furthr. Th cncptn, analyss and smulatn f a mult-phas ntrlavd DC-DC bst cnvrtr fr 42 pwr systms ar prsntd. On klwatt ntrlavd thr-phas bst cnvrtr dsgnd t prat n a Dscntnuus Cnductn Md (DCM). Th mpact f paramtr varatn n th prfrmanc capablts f th cnvrtr s dscrbd. Smulatn rsults ar prvdd t llustrat th advantags f th prpsd cnvrtr and cntrllr schm. All th advantags f ntrlavng, such as hghr ffcncy and rducd nput and utput rppl fr vltag/currnt, ar als Achvd n th prpsd bst cnvrtr. Th rsults shw that th systm s stabl and wll bhavd undr nput vltag varatns and th utput vltag rmans wthn th dsrd spcfd lmts prsntd n autmtv standards. ndx Trms DC-DC cnvrtrs; ntrlavd bst cnvrtr.. NTRODUCTON A swtchng cnvrtr s an lctrnc pwr systm whch transfrms an nput vltag lvl nt anthr fr a gvn lad by swtchng actn f smcnductr dvcs. A hgh pwr ffcnt dc-dc cnvrtr s strngly dsrd and has fund wdsprad applcatns. Exampls nclud arspac, sa and undrsa vhcls, lctrc vhcls (E), Hybrd Elctrc hcl (HE), prtabl lctrnc dvcs lk pagrs, and mcrprcssr vltag rgulatn [1]. n dual-vltag pwr systms, th dc-t-dc cnvrtr s rqurd t stp-up vltag prvdd frm th lw-vltag bus r back up part fr th xstng hgh-pwr dvcs n th applcatn that us ths pwr systm. A pwr systm cnsstng f ful cll, battry and pssbly thr nrgy strag cmpnnts usd n lctrc vhcls and statnary pwr systm applcatns, whch nrmally rqur a hghpwr bst cnvrtr fr nrgy managmnt that mplys an nrgy strag cmpnnt t assst th slw-rspndng ful cll. Multphas cnvrtr wth ntrlavd cntrl s ssntal fr th hgh-pwr bst cnvrtr n rdr t rduc th rppl currnt and t rduc th sz f passv cmpnnt. S far fw ltraturs rlatd t th cntrllr dsgn f th hgh-pwr ntrlavd bst cnvrtr can b fund [4]. Thr hav bn many paprs dscrbng th us f multphas buck cnvrtrs, spcally fr hgh-prfrmanc hgh-pwr applcatns [1,9,10]. Hwvr, all th advantags f ntrlavng, such as hghr ffcncy and rducd nput and utput rppl fr vltag/currnt, ar als ralzd n th bst tplgy. Mst f th cntrllrs usd n buck applcatns apply qually wll whn cnfgurd fr us n an ntrlavd bst applcatn. n [1] mult-phas buck cnvrtr cntrlld by PD s prsntd. Ths papr fllwng th sam apprach usd n buck cnvrtrs and appld t n bst cnvrtr, PD s cnfgurd usng Zglr Nchls tunng mthd, whr th ndvdual ffcts f P,, and D s tund n th clsdlp rspns t gv th rqurd charactrstcs. n sctns and rspctvly, prncpls f mdlng and dsgn stps t slct cmpnnts ar prsntd fr bst cnvrtr. ntrlavd multphas bst cnvrtr and cntrl dsgn ar ntrducd n sctn v, and v. Smulatn and rsults f wrk rprtd and cmputd n sctn v. A brf cnclusn s drawn n sctn v.. PRNCPES OF MODENG AND DESGN BOOST CONERTER Th crcut f th PWM bst dc dc cnvrtr s shwn n Fg. 1, ts utput vltag s always hghr than th nput vltag fr stady-stat pratn. t bsts th vltag t a hghr lvl. Th cnvrtr cnssts f an nductr, a pwr MOSFET, a dd D 1, a fltr capactr C, and a lad rsstr R. Th swtch S s turnd n and ff at th swtchng frquncy f s = 1/T wth th ON duty rat D = t n /T, whr t n s th tm ntrval whn th swtch S s ON [2]. Th Equvalnt crcut whn th swtch s ON and th dd s OFF and th rvrs cas ar shwn n fg. 1(b) and fg. 1(c), rspctvly. Th prncpl f pratn f th cnvrtr ar dpctd n Fg. 2, fr th tm ntrval 0 < t DT, th swtch s ON. Thrfr, th vltag acrss th dd s D = -, causng th dd t b rvrs basd. Th vltag acrss th nductr s =. As a rsult, th nductr currnt ncrass lnarly wth a slp f /. Th swtch currnt s qual t th nductr currnt. At t = DT, th swtch s turnd ff by th gat-t-surc vltag. Th nductr acts as a currnt surc and turns th dd n. Th vltag acrss th nductr s = < 0. Hnc, th nductr currnt 76

2 dcrass wth a slp f ( )/. Th dd currnt quals th nductr currnt. Durng ths tm ntrval, th nrgy s transfrrd frm th nductr t th fltr capactr C and th lad rsstanc R. At tm t = T, th swtch s turnd n agan, trmnatng th cycl [2,6,5]. d () t t (1) dt f th surc vltag rmans cnstant, th rat f rs f nductr currnt s pstv and rmans fxd, s lng as th nductr s nt saturatd. Thn quatn (1) can b xprssd as: Fg 1. PWM bst cnvrtr. (a) Crcut. (b) Equvalnt crcut whn th swtch s ON and th dd s OFF. (c) Equvalnt crcut whn th swtch s OFF and th dd s ON [2]. Fg 2. dalzd currnt and vltag wavfrms n th PWM bst cnvrtr wrk n CCM [6]. A mathmatcal mdl f th systm hlps us t ralz th cntrllr dsgn. Hnc, w wll drv th quatns cncrnng th DC/DC bst cnvrtr mdl frm basc laws. d () t (2) dt Whn th swtch s pn, th crcut that s applcabl s shwn n Fgur 3.a. Nw th vltag acrss th nductr s: v (3) Gvn that th utput vltag s largr than th surc vltag, th vltag acrss th nductr s ngatv and th rat f rs f nductr currnt, dscrbd by quatn (4) [2], s ngatv. Hnc f th swtch s hld OFF fr a tm ntrval qual t (1-D)T, th chang n nductr currnt can b cmputd as gvn n quatn (5) d () t (4) dt Δ t 1 D T (5) Th chang n nductr currnt rflctd by quatn (5) has a ngatv valu, snc >. Snc th nt chang n nductr currnt vr a cycl prd s zr whn th rspns (t) s prdc, th sum f changs n nductr currnt xprssd by (3) and (5) shuld b zr. That ylds (6) 1 D th valu f th nductanc ndd t nsur that th cnvrtr rmans n Dscntnuus Cnductn Md (DCM) f pratn.. th nductr currnt s zr durng part f th swtchng prd and bth smcnductr dvcs ar OFF durng sm part f ach cycl, nductr valu must b lss than crtcal, whch can b dtrmnd as fllw[2]. D 1 D T crtcal (7) 2 Whr, crtcal And Fg 3. Bst cnvrtr pratn stats [2]. Whn th swtch s clsd, th quvalnt crcut that s applcabl s shwn n Fg. 3.b.Th surc vltag s appld acrss th nductr and th rat f rs f nductr currnt s dpndnt n th surc vltag and nductanc. Th dffrntal quatn dscrbng ths cndtn s [2]: P (8) Whr, P s th utput pwr. Th pak nductr currnt can b calculatd as: DT pk (9) 77

3 Th avrag nductr currnt can b fund ut by quatng th pwr drawn frm th surc t th pwr dlvrd t th lad rsstr. Agan th rppl n utput vltag s gnrd and t s assumd justfably that th utput vltag rmans stady at ts avrag valu. P absrbd by lad rsstr s thn: 2 ( O ) P (10) R Th avrag valu f nductr currnt s als th avrag valu f surc currnt, thn: 2 ( O ) (11) R Smlarly, th utput capactanc slctn s als cnsdrd t mak sur that utput vltag rppl s wthn th dsrd bundary. t s prvn that th mnmum capactanc rqurd fr utput vltag rppl s gvn by [8], DT C mn (12) R rppl Hwvr, th standard dc-dc cnvrtr wth sngl structur s nt practcabl du t th hgh currnt (71A), and hgh pwr (1KW) rqurd fr autmtv applcatns. Thrfr, th pwr stag f th cnvrtr wuld hav t b bult n paralll fr practcal mplmntatn. A cmmn apprach n tchncal ltratur and ndustry practc s t us ntrlavd mult-phas tchnqu nstad f a sngl largr cnvrtr [1]. Ths apprach wll b dscussd n th nxt sctn.. COMPONENT SEECTON Fr lw vltag/hgh currnt pwr cnvrtr, th usag f MOSFETs swtchng dvcs wth lw n-rsstanc s rqurd fr mr ffcnt and practcal pwr cnvrsn. Th nductrs and capactrs play mprtant rls n th dsgn f th pwr cnvrtr. nductr s an nrgy strag lmnt whl th capactr s th man buffr fr absrbng th rppl currnt gnratd by th swtchng actn f th pwr stag. Th swtchng frquncy f th pwr lctrncs usd n autmtv ndustry rangs frm 82 khz t 200 khz wth 100 khz as a typcal valu usd fr mst pratn f dc/dc cnvrtrs [1]. Cmpnnts was calculatd frm quatns abv wth = 14, = 42, and P = 1000W, th calculatd and slctd cmpnnt summarzd n tabl (1). TABE 1 Calculatd And Slctd Cmpnnt Cmpnnt/ calculatd slctd quatn paramtrs R 1.764hm 1.764hm (10) 0.65µH.3 µh (7) n (8) C 3.779mF 3.9mF (12). MUTPHASE SWTCHNG OF DC-TO-DC CONERTER T ralz pwr cnvrsn by a smpl systm cnfguratn, a mult-clls bst cnvrtr tplgy dsgnd fr DCM f pratn s mplyd. Fg. 4 shws th dvlpd Smulnk dagram f thr-cll ntrlavd bst cnvrtr wth PD Cntrllr. Fg 4. Smulnk mplmntatn f th ntrlavd thrphas bst cnvrtr crcut wth PD cntrllr T dsgn ths cnvrtr, th fllwng autmtv spcfcatns fr dual-vltag autmtv lctrcal systms must b fulflld and ar tabulatd n tabl (2) [1,11]. TABE 2 Dsgn Spcfcatns Fr A Pwr Cnvrtr n A Dual-ltag Autmtv Elctrcal Systm Dscrptn Paramtr alu Opratn utput 30<42<50 vltag Opratn nput 11<14<16 vltag Pwr ratng P 1KW Opratn tmpratur T -40C<T<90C rang Output rppl vltag rppl 300m Output rppl currnt rppl 1A Th thr-cll ntrlavd bst cnvrtr s cnnctd n paralll t a cmmn utput capactr and sharng a cmmn lad wth th asscatd cntrl systm. n ths ntrlavd thr-cll dc/dc cnvrtr archtctur, th clls ar swtchd wth th sam duty rat, but wth a rlatv phas shft r tm ntrlavd f 120 ntrducd btwn ach cll n rdr t rduc th magntud f th rppl at th utput prt f th cnvrtr. Th vrall utput currnt s achvd by th summatn f th utput currnts f th clls. Wth th phas shft f 120, th utput f th cnvrtr s fund t b cntnuus. Du t th qual sharng f th lad currnt btwn clls, th vrwrk n th smcnductr swtchs s rducd and thrby rlablty s mprvd. Anthr advantag s th ablty t prat th cnvrtr whn a falur ccurs n n cll as wll as th pssblty t add nw clls t th cnvrtr wth mnmum ffrts [1]. Snc ths s a thr-phas ntrlavng cnvrtr, th pwr 78

4 stag nductanc f ach phas s thrfr qual t µh (nt that rqurd fr n stag cnvrtr s 0.3 µh, as shwn n tabl 1). Th utput capactr s anthr mprtant lmnt, whch may rduc th systm cst n mult-phas cnvrtr systm and s ndd t kp th utput vltag rppl rppl wthn th allwabl utput vltag rang. T mt ths cnstrants f th dsgn spcfcatn, a capactr valu f 3.9mFs suffcnt.. CONTRO DESGN Fdback s usd n cntrl systms t chang th dynamc bhavur f th systm, whthr mchancal, lctrcal, r blgcal, and t mantan thr stablty. Th cntrl stratgy f th prpsd cnvrtr s basd n a vltag-md-cntrlld Puls Wdth Mdulatn (PWM) wth a Prprtnal-ntgral-Drvatv (PD) whch taks ts cntrl sgnal frm th utput vltag f th swtchng cnvrtr. A Smulnk mdl fr th ntrnal structur f th PD usd t cntrl th cnvrtr s shwn n Fgur 5. Th dsrd utput gnratd sgnal f th PD cntrllr s fd t th Puls Wdth Mdulatn (PWM) unt, whr t s cmpard wth a cnstant frquncy sawtth vltag. Th frquncy f sawtth vltag s th swtchng frquncy f s f th cnvrtr whch s 100 khz. Th utput sgnal frm th PWM s th swtchng cntrl sgnal, whch rprsnts a squnc f pulss that drvs th smcnductr swtch, as shwn n Fgur 6. Fg 5. A PD cntrllr rprsntd by a Smulnk blck dagram Th am s t rgulat th utput vltag f th cnvrtr acrss th lad rsstanc R t match a prcs stabl rfrnc vltag rf. Ths s achvd by subtractng th dsrd rfrnc vltag rf frm th snsd utput ltag f th cnvrtr. Th vltag-rrr thus btand s passd thrugh a PD cntrllr t btan th dsrd sgnal. Th functn f th PD cntrllr s t tak th nput sgnal, cmput ts drvatv and ntgral, and thn cmput th utput as a cmbnatn f nput sgnal, drvatv and ntgral. Th ndvdual ffcts f P,, and D tunng n th clsd-lp rspns ar summarzd n tabl 3[1]. Tabl 3 ffct f ndpndnt P,, and D durng th tunng prcss Clsd p rspns ncrasng P ncrasng ncrasng D Rs tm Dcras Small dcras Small dcras Ovrsh t ncras ncras Dcras Sttlng tm Small ncras ncras Dcras Stady stat rrr Dcras arg dcras Mnr dcras Fg 6. mplmntatn f Puls Wdth Mdulatn n Smulnk Th prpsd cnvrtr ncsstats a phas-shft f 120 btwn th clls t gnrat th thr-swtchng cntrl sgnal whch ar usd t drv th thr actv MOSFET swtchng dvcs f th cnvrtr systm. Fgur 7 and 8 shw th mplmntatn f th thr-phas ntrlavng crcut n Smulnk and th thr phas cntrl sgnal wavfrms rspctvly. Fg 7. Thr phass f ntrlavng n Smulnk Fg 8. Thr phas cntrl sgnals n Smulnk 79

5 . SMUATON AND RESUTS Th cmplt mdl f th Smulnk mplmntatn f th ntrnal structur f th ntrlavd thr-phas bst cnvrtr systm s shwn n Fgur 9. Th cnvrtr systm s dvdd nt thr man parts; th thr-cll bst cnvrtr, th PD cntrllr ncludng th vltag md PWM and th phas shft crcut. Th mult-phas cnvrtr has bn smulatd t btan th ncssary wavfrms that dscrb cnvrtr systm pratn undr stady-stat and transnt cndtns, usng th dsgn paramtrs tabulatd n tabl 4. Fg 10. Output ltag Rppls Fg 9. Smulnk schmatc dagram llustratng th mplmntatn f ntrlavd tr-phas bst cnvrtr crcut wth a PD cntrllr Tabl 4. Th paramtrs f cnvrtr paramtr symb valu unt l nput vltag 14 Output vltag 42 Numbr f phass N 3 - nductr valu μh Capactr valu C 3.9 mf ad rsstanc R hm Swtchng frquncy f s 100 khz A. Rppl Cancllatn Th frst stp n th analyss f th mult-phas ntrlavd cnvrtr systm s t nvstgat th ffctvnss f rppl cancllatn rlatd t th varatn f currnt and vltag as a functn f th numbr f clls. As can b sn th cnvrtr achvs a vry gd currnt and vltag rppl cancllatn fr thr-clls and abv. Thugh, sx r ght clls prduc a bttr rppl cancllatn, hwvr th cst utwgh th gans n accuracy. t can b sn frm Fgurs 10 and 11, whch th rppl f utput vltag s 8.8m, and th rppl f th ttal utput currnt f th cnvrtr s 5mA, and thy ar bttr than th dsrd spcfd lmts. Fg 11. Output Currnt Rppls Fgur 12 shws th stady-stat wavfrms f th ndvdual cll currnts, th smulatd rsults shw that nductr currnt f ach cll rss t 70.86A durng ach swtchng prd and gs thrugh an ntrval n th dscntnuus cnductn md. Fg 12. Th ndvdual cll currnts wavfrm Fg 13 and 14 shw th ttal utput currnt and th utput vltag f th cnvrtr systm, th pratn f th pwr cnvrtr systm s stabl and accurat. Th cnvrtr s abl t rspnd and prduc th dsrd stabl utput vltag and dlvr th rqurd ttal utput currnt 80

6 t th lad wth vry lw rppl. As a rsult, n ngatv ffct n th lads cnnctd t th cnvrtr. Fg 13. Th utput vltag f th cnvrtr Fg15. Transnt rspns f th utput vltag t stp chang n lad t can b sn that th utput vltag vrsht t 44.5, and 42.6, whn th lad at th utput f th cnvrtr systm was rapdly changd frm 25% t 50%, frm 50% t 75% and frm 75% t full lad (1kW). Th rsults shw that th prfrmanc f th systm s stabl and wll bhavd undr lad varatns and th utput vltag rmans wthn th dsrd spcfd lmts prsntd arlr n tabl (2). C. Transnt Smulatn fr nput ltag aratn n ral cndtns, th altrnatr utput vltag rangs frm 11 t 16 durng nrmal pratn, wth nmnal vltag f 14. T study ths ln f varatn, a stp chang n th nput vltag frm 9 t 24 s appld t th mdl. Fgur 16 shws a transnt rspns f th utput vltag bhavur wavfrm du t suddn changs n th nput vltag f th pwr cnvrtr systm. Fg 14. Th ttal utput currnt f th cnvrtr B. Transnt Smulatn fr ad aratn Th ntrlavd dc/dc bst cnvrtrs ar usd as pwr surc t rsstv and dynamc lads n passngr car and ths lads culd b catgrzd nt [1]. Small mtrs ry small mtrs ghtng systm Ky-ff lads thr lads Th lctrcal lads dmand vars and dpnds upn th wathr and th drvng cndtns. A full lad cndtn s rarly prsnt fr a prlngd prd f tm and mst f th dvcs run at lght lads (stand-by-md) fr mst f th tm. T study th ffct f th lad varatn n th dynamc bhavur f th cnvrtr systm, th lad at th utput f th cnvrtr systm s suddnly changd frm 25% t 50% t 75% and t 100% and thn back frm 100% t 75% t 50% and 25% f th full lad at tm t = 0.05, 0.08, 0.11, 0.13, 0.16 and 0.19s, rspctvly. Th smulatd rsults ar shwn n Fgur 15. Fg 16. Output vltag and utput currnt du t nput vltag varatns t can b sn that th utput vltag vrshts t 42.69, and dcrass t , thn vrshts t fnally vltag vrshtng t whn th nput vltag f th cnvrtr systm s rapdly changd frm 14 t 16 t 24 t 9 t 11 and t 14, at tm t= 0.05s, 0.08s, 0.11s, 0.13s, 0.16s and 0.19s, rspctvly. t can b bsrvd that th dsgnd systm has a lw snstvty t th varatns f nput vltag. Ths varatns hav nly small nflunc n th utput vltag and lad currnt and stll rspct th spcfcatns f th autmtv standard. t can b cncludd that frm th rsults btand th prpsd cnvrtr can mantan th dsrd utput vltag ndpndntly f lad and supplyvltag varatns. Ths may lad t th lmnatn r rducng f prtctn cnnctd t th 42 bus n th pwr systm.. CONCUSON n ths papr, analyss, dsgn and smulatn f 14/42 ntrlavd thr-phas dc/dc bst cnvrtr systm wth n klwatt utput pwr s prsntd. Ths systm s a part f th dual vltag archtctur that wll b usd n futur passngr car pwr systm. Basd n th smulatn 81

7 rsults, th prfrmanc f th dc-t-dc bst cnvrtr systm prvds a numbr f faturs that d nt xst n tday's lctrcal systms. All th advantags f ntrlavng, such as hghr ffcncy and rducd nput and utput rppl fr vltag/currnt, ar als Achvd n th prpsd bst cnvrtr. Th rsults shw that th systm s stabl and wll bhavd undr nput vltag varatns and th utput vltag rmans wthn th dsrd spcfd lmts prsntd n autmtv standards. AUTHOR BOGRAPHY Ahmd Sad Ashur (M 2009) btand hs BSc frm th Unvrsty f Al-Fatah n 1975, hs MSc frm th Suthrn Calfrna Unvrsty (USC) n 1981, and hs PhD frm Unvrsty f Nttngham n H s a faculty mmbr at th Unvrsty f Trpl snc Hs ara f ntrst s dgtal sgnal prcssng algrthms, systms, applcatns, and cmmuncatns. H has mr than 19 publcatns n rputabl jurnals, and ntrnatnal cnfrncs. REFERENCES [1] A. Shrud, H. Kharaz, A. S. Ashur, A. Fars and M. Bnamar, A study f Mdlng and Smulatn fr ntrlavd Buck Cnvrtr, 1 st Pwr Elctrnc & Drv Systms & Tchnlgs Cnfrnc, Pag(s): 28 35, [2] Maran K. Kazmrczuk, Puls-wdth Mdulatd DC DC Pwr Cnvrtrs A Jhn Wly and Sns, td, Publcatn [3] drs Gadura, Ka Zngr, Tuv Sunt, Ptr allttu, Nw Mthdlgy fr Dsgn, Analyss, and aldatn f DC DC Cnvrtrs Basd n Advancd Cntrllrs Tlcmmuncatn Enrgy Cnfrnc, NTEEC '99. [4] Xngy Xu, zh Zhu, A DSP Basd Cntrllr fr Hgh- Pwr ntrlavd Bst Cnvrtrs APEC'03, vl. 1, pp , 9-13 Fbruary [5] On smcnductr, WTCHMODE Pwr Suppls Rfrnc Manual and Dsgn Gud [6]. Ramanarayanan, Curs Matral n Swtchd Md Pwr Cnvrsn Dpartmnt f Elctrcal Engnrng ndan nsttut f Scnc Bangalr Scnd Edtn [7] Janpng Xu, An analytcal tchnqu fr th analyss f swtchng DC-DC cnvrtrs Crcuts and Systms, 1991., EEE ntrnatnal Sympsum n vl.2 PP [8] S,Karthk Kumaran, KR Santha, DSP Cntrl f DC/DC Bst Cnvrtr fr Ful Cll basd Hybrd Elctrc hcl, EEE- ntrnatnal Cnfrnc On Advancs n E.ngnrng, Scnc And Managmnt (CAESM -2012). [9] Yabn Zhang, Pal Bagnl, Eml Franch. Thrtcal Dsgn f Cmpact Mult-phas ntrlavd Buck DC-DC Cnvrtr fr Autmtv Pwr Applcatns ntrnatnal Sympsum n Pwr Elctrncs, Elctrcal Drvs, Autmatn and Mtn (SPEEDAM), 2012, Pag(s): [10] Wnnan Gu, Pravn K. Jan, Analyss and Mdlng f ltag Md Cntrlld Phas Currnt Balancng Tchnqu fr Multphas ltag Rgulatr t Pwr Hgh Frquncy Dynamc ad Appld Pwr Elctrncs Cnfrnc and Expstn, APEC Twnty- Furth Annual EEE Pags: [11] Tmthy C. Nugbaur and Davd J. Prrault Cmputr add ptmzatn f DC/DC cnvrtrs fr autmtv applcatns, EEE Transactns n Pwr Elctrncs.Ol.18., NO.3, May, (2003). [12] Muhammad H. Rashd, Pwr Elctrncs Handbk Acadmc Prss Srs n Engnrng, Publcatn Farag S. Alargt was brn n Zltn, bya, n H rcvd th B.S. dgr n lctrcal and lctrnc ngnrng frm Almrgb Unvrsty, Alkhms, bya, n H s currntly wrkng tward th M.S. dgr n lctrcal ngnrng n Trpl Unvrsty, Trpl, bya. Snc 2012, h has bn a Rsarchr at Cntr fr Slar Enrgy Rsarch and Studs. Hs rsarch ntrsts nclud mdlng and cntrl f swtchng dc dc cnvrtrs and rnwabl nrgy tchnlgy. 82