PASAP: Power Aware Structured ASIC Placement

Transcription

1 PASAP: Powr Awr Strutur ASIC Plmnt Ashutosh Chkrorty ECE Dprtmnt Univrsity o Txs t Austin Austin, Txs, USA shutosh@r.utxs.u Dvi Z. Pn ECE Dprtmnt Univrsity o Txs t Austin Austin, Txs, USA pn@.utxs.u ABSTRACT Strutur ASICs provi n xiting mil groun twn FPGA n ASIC sign mthoologis. Compr to ASIC, strutur ASIC s signs rquir lowr non rurring nginring (NRE) osts n turn-roun-tim ut sur rom highr powr onsumption n lowr prormn. Powr rution or strutur ASICs uss xtnsiv lok n supply powr-own o unus iruitry n us o low powr vis. Howvr, u to th limit grnulrity o powr-own, physil sign (spilly plmnt) shoul prorm to mximiz th omponnts tht n powr own. In this ppr, w prsnt th irst plmnt lgorithm to spiilly trgt this prolm. Our tool, PASAP (Powr Awr Strutur ASIC Plmnt), minimizs th lok n lkg powr y mximizing th rtion o th strutur ASIC tht n powr own or isonnt rom lok tr. On st o lrg nhmrk signs, PASAP rus lok n lkg powr y 32% n 17% rsptivly ompr to prior strutur ASIC plmnt tool RgPl [1] inurring 17% pnlty in wirlngth n 30% longr runtim. Ctgoris n Sujt Dsriptors B.7.2 [Hrwr, Intgrt Ciruit]: Dsign Ais Gnrl Trms Algorithms, Dsign Kywors low powr, plmnt, rgulr ris, strutur ASICs 1. INTRODUCTION Skyrokting osts n inrsing vriility ssoit with n ASIC sign low n unptl powr n ly pnlty ssoit with FPGA sign low hv or smionutor ompnis to look or ltrntivs. On vil ltrntiv tht hs mrg ovr tim is th us o strutur ASICs. Strutur ASICs provi n xiting mil-groun twn high prormn o ASIC signs n short tim-to-mrkt FPGA Prmission to mk igitl or hr opis o ll or prt o this work or prsonl or lssroom us is grnt without provi tht opis r not m or istriut or proit or ommril vntg n tht opis r this noti n th ull ittion on th irst pg. To opy othrwis, to rpulish, to post on srvrs or to ristriut to lists, rquirs prior spii prmission n/or. ISLPED 10, August 18 20, 2010, Austin, Txs, USA. Copyright 2010 ACM /10/08...$ signs. Thy xploit th t tht not ll msk-lyrs provi qul vlu or th ustomrs n ths lyrs n pr-rit mortizing thir ost ovr multipl signs [2]. Strutur ASIC low is muh simplr thn tht or tritionl ASICs us mjority o p sumiron issus suh s signl intgrity, powr gri optimiztion, low skw lok tr istriution r lry tkn r o y th strutur ASIC vnors. Highr powr onsumption ompr to th ASIC pproh n prov to th Ahills hl o strutur ASIC mthoology. To ru th powr pnlty, thr hv n mny innovtions in thir rhittur inluing us o vi progrmming (inst o SRAMs whih rin lkg powr), low lkg tripl oxi vis, n powr-own o unus omponnts. From th EDA prsptiv, th powr svings n inrs i th sign tools n xploit ths powr optimiztion mthos. On suh stp is to nhn plmnt lgorithms to mximiz th unus omponnts so tht thy n powr own. Distriution o lls s i y plmnt trmins whih rs o th strutur ASICs must rmin powr on. Du to limit grnulrity o powr own vill, mny non untioning vis my or to rmin powr up u to nighoring untioning vis, ling to wst lkg powr. In ition, plmnt lso trmins th xtnt o th lok ntwork tht must swith t h lok yl. Typilly, lls longing to only on lok group n pl los to h othr, thror wrong istriution o lls n signiintly urn muh mor powr y rquiring lrgr lok ntwork to rmin tiv. In this ppr, w tkl powr wr plmnt on strutur ASIC pltorms or th irst tim n propos mthos to ru th lkg n lok powr. Th rst o this ppr is orgniz s ollows: W provi kgroun o strutur ASIC rhittur n plmnt in Stion 2. Stion 3 tils th lkg n lok powr mol us to vlut th plmnt solution. Powr wr strutur ASIC plr (PASAP) is prsnt in Stion 4. Th xprimntl stup is sri in Stion 5. Powr rution rsults r prsnt in Stion 6. Stion 7 onlus our ppr. 2. BACKGROUND 2.1 Strutur ASIC Arhittur Lik FPGAs, strutur ASICs onsist o rgulr 2-D rptition o si uiling lok ll til. Dpning on th siz o th sign to implmnt on strutur ASIC, th numr o rptition o th tils in th horizontl n vrtil irtion n moii. Th physil strutur hiv y rptition o th til rtin numr o tims, will rrr to s pltorm. Sin til is th si uiling lok o strutur ASIC, w sri its rhittur nxt. 395

2 Eh til is rtngulr rgion in whih th vis r prrit. Thr n mny irnt units rit in til suh s logi lls, lip lops, multiplxrs, rs t. In this work, w will primrily trgt th rhittur o til s rls y ling strutur ASIC ompny ASIC [3] s prt o thir worlwi plmnt ontst. Thr r our irnt typs o lls rit in h til: logi lls, lip lops units, rgistr ils n RAMs. W rr to ths lls s LOGC, DFF, REG, n RAM rsptivly in th rst o th ppr. Th rltiv siz o ths lls r 1x1, 1x1, 8x32, n 16x64 thus thir r is in th rtio 1:1:256:1024 rsptivly. Expt LOGC, ll othr ll typs r squntil in ntur. Th lotions whr ths lls r pr-rit in th til r s shown in Figur 1. LOGC n DFF lls r rit in olumns o hight 64 h. Thr r 36 n 24 olumns (not ll shown in Figur 1) o LOGC n DFF lls rsptivly in h til. At th ntr o th til, on RAM is rit n hl o th olumns o LOGC ndff h ppr on oth si o th RAM ll. On th right n o th til, 4 REG r rit in 2x2 rry ormtion. In summry, h til hs 2304 LOGC, 1536 DFF, 4 REG n 1 RAM lls. Clok routing onstrints itt tht not mor thn w loks n istriut in til (though th pltorm n hv mny mor uniqu loks). Thror, th squntil lls insi h til shoul not rquir mor thn givn numr o uniqu loks. Til LCELL BRAM DFF REG Intr-til sp Figur 1: Strutur ASIC pltorm. 2.2 Strutur ASIC Plmnt Plmnt on strutur ASIC tks s input ) n RTL xprss in trms o LOGC, DFF, REG, n RAM lls, ) th rhittur o th strutur ASIC pltorm, ) Gomtry inormtion out th til, n ) Clok onstrints t th pltorm n t th til lvl; n mps h ll to pr-rit lotion on th pltorm suh tht sit omptiility s wll s lok onstrints r stisi. Th ojtiv o th plmnt n to minimiz wirlngth or ly o th iruit whil mting ths onstrints. Prvious Work: Rnt plmnt ontst sponsor y ASIC [3] ostr rsrh in th il o plmnt or strutur ASICs. Hr w sri th grn priz winning ntry RgPl [1]. Du to its vilility (opn sour) n high qulity, w us RgPl s our plmnt rmwork n slin to ompr ginst. RgPl irst trnsorms th strutur ASIC plmnt prolm into simplr row-s plmnt prolm y rsizing th lrgr lls (REG n RAM to unit siz n rmoving th physil sp rsrv or ths lls rom th pltorm. Also, th lok onstrints r ignor t this stg. Existing high qulity row-s plr (suh s CAPO [4], mpl6 [5] t) is us to gnrt n initil plmnt with xllnt wirlngth. Th plmnt rsults r thn xpn to r-insrt physil sp rmov or REG n RAM lls whil onurrntly prorming ut minimiztion u to rinsrt sp or ths lls. An intgr linr progrmming (ILP) s lok ssignmnt n ntwork low s lok lgliztion is prorm to stisy th lok onstrints. Finlly wirlngth rution is prorm to uno ny mg u to lgliztion. 3. LEAKAGE/CLOCK POWER MODEL Lkg Powr Mol: Th lkg powr o strutur ASIC pltorm is roughly proportionl to th numr o vis in it. Evn i no ll (in th RTL) is mpp on to vi on th pltorm, th vi will still onsum lkg powr unlss isonnt rom th powr supply. Existing strutur ASICs lry llow powr own (i.. isonnt rom powr gri) o unus vis on th pltorm using singl-vi powr progrmming. W ssum tht powr-own n prorm t two lvls o grnulrity: ) An unus til n ompltly powr own ruing its lkg (n ynmi) powr to zro, n ) Within til, n unus olumn n powr own i no untioning lls r pl in it, ruing its powr to zro. Th lkg powr svings hiv y powr own o omplt til is quivlnt to tht hiv y iniviul powr own o h olumn in th til iniviully. I th lkg powr o on olumn is P ol, thn th lkg powr mol o th strutur ASIC pltorm is simply th sum o lkg powr o ll th olumns tht 0 r not powr 1 own. P lk = P ol X B X E A (1) t tils ols(t) whr ols(t) nots th olumns in til t n E is inry vril whos vlu is 1 i th olumn is powr on n 0 othrwis. From Eqn 1, it is lr tht w shoul try to minimiz th numr o olumns powr up to ru lkg powr. Clok Powr Mol: Unlik lkg powr, lok powr is lrgly proportionl to th lok swith pitn. Du to stringnt slw n skw onstrints on th lok signl, lok is istriut ross th pltorm using hirrhy o high riv powr hungry urs. To ru lok powr, th im shoul to ru lok ntwork s swith pitn. To unrstn th lok powr mol, w must irst unrstn lok istriution rhittur. W ssum simplisti lok istriution ntwork s pit in Figur 2 sri using 2x2 tils to ru luttr. Figur 2- pits th pltorm lvl lok istriution whrs Figur 2- pits th til lvl lok istriution. Th rhittur w ssum is s on th rnt works on lok istriution on FPGAs [6] [7]. Hr, w sri th lok istriution rhittur o singl lok whih is uplit to istriut multipl loks. In Figur 2-, lvl 1 ur B1 insrts th lok signl t th ntr o th hip tht rivs horizontl spin. Eh lvl 2 ur B2 istriuts th lok signl to on vrtil spin. Similrly, lvl 3 urs rivs th lok signl into h til. Insi til, s shown in Figur 2-, Lvl 4 urs B4 riv th DFF olumns (only 1 shown) s wll s REG n RAM lls. Owing to th lrgr numr o squntil lmnts in RAM n REG lls, multipl B4 urs r rquir to riv thm (only 396

3 B2 B2 B1 B2 B2 B4 DFF DFF DFF B4 RAM ) ) REG Figur 2: Clok istriution: ) Pltorm ) Til lvl 1 shown). W ssum tht h B4 ur n riv only s mny squntil lmnts s r in DFF olumn. To istriut multipl loks, th B1 n B2 lok urs n rplit or h lok signl. Du to routing onstrints, typilly only sust o pltorm lvl loks n rout into h til. Eh n B4 lok urs is rplit s mny tims s th siz o sust o loks tht n rout in h til. W ssum tht powr-own o lok signl n prorm t thr lvls o grnulrity: ) An unus vrtil spin s lok n isonnt i ll o th tils rivn y this spin r unus. ) An unus til n isonnt i ll lls in it r unus, n ) within th til, th lok riving h DFF olumn, REG, RAM ll n isonnt. For pltorm with WxH tils (inst o 2x2 in Figur 2), lt C G loks t pltorm lvl n C T loks t til lvl support. Furthr, lt th numr o quivlnt (tr sling or lrgr sizs o REG n RAM) numr o DFF olumns S h ontining N squntil lmnts. Unr ths ssumptions, Tl 1, shows th onstitunts o th lok ntwork. Columns 2 ontins th numr o ur n whrs olumn 3 shows th pitiv lo on h o ths urs. Th lst olumn shows th totl swith pitn sn y th orrsponing lvl o lok urs whn th input pitn o n ntity X is not y L X. B4 Tl 1: Clok Tr Distriution Chrtristis Bur Numr Eh Totl Typ Instn Lo Lo B1 C G 2 W L B2 2 W C G L B2 B2 C G 2 W 0.5 H L 2 W H C G L C T W H S L B4 W H S C T L B4 B4 C T W H S N L DF F W H S N C T L DF F Using th lok ntwork rhittur n Tl 1, th totl lok powr n writtn s!! C X G 2WX 0.5H X P lk = L B1 + E ijl B2 + (E ije jk L ) + i=0 X t tils C T X m=0 j=0 k=0!! SX (E mnl B4 + E mnl DF F) n=0 whr ll E xy r ooln vrils. E ij is 1 i lok i rivs spin j, E jk is 1 i spin j rivs til k on tht spin, E mn is 1 i lok m in th til rivs th olumn n. Th irst trm in Eqution 2 is th totl swith pitn o C G glol loks n th son trm is th totl swith pitn within til, summ ovr ll th tils. Sltiv powr own o unus omponnts (spin, til, olumn) moult th vlus o ths inry vril thus hnging th lok powr. (2) 4. LOW POWER PLACEMENT W now introu th prolm ing tkl in this work. Givn strutur ASIC pltorm n sign, prorm ll plmnt to minimiz th lok n lkg powr onsumption y mximizing th omponnts tht n powr own. Powr rution shoul not gr th wirlngth y mor thn givn ugt. 4.1 Ovrll Flow Figur 3, shows our omplt low. Th rtngulr loks rprsnt our nw ontriutions whrs th ovl loks rprsnt th stps in RgPl [1], n xisting opn sour plr or strutur ASICs. Atr sriing th ovrll low in this stion, h rtngulr lok will xplin in mor tils in nxt w sustions. RTL Spin & Til Rution Pltorm Glol Plmnt Clok Lgliztion Column Minimiztion Column Assignmnt Wirlngth Rution OUT Figur 3: Our plmnt low. Blu rtngls r our nw ontriutions. Gry ovls r rom [1]. Givn th input ntlist n th pltorm, w minimiz th vrtil spins n tils tht must rmin powr up y gnrting nw onstrints or glol plr. This stp works unr givn wirlngth inrs ugt. Glol plmnt is thn xut on th sign ollow y lok lgliztion. In th nxt stp, w minimiz th numr o olumns tht must sty powr on y voiing snrios whr th numr o lls in til is slightly mor thn intgrl multipl o numr o lls tht n ommot in olumn, thry rquiring nothr olumn. Finlly, w lustr n ssign th lls into s w olumns s possil whil minimizing wirlngth hng. 4.2 Spin n Til Rution To mrk vrtil spin s unus, w must nsur tht ll th tils rivn y th spin r mrk s unus. To mrk til s unus, w must mk sur tht no ll is pl in it. I th sign to pl is muh smllr thn th physil pltorm, nturlly thr woul mny suh tils. Howvr, our im is to mximiz suh unus tils y intiying thos whih woul hv vry low numr o lls in thm n viting ths lls without muh wirlngth pnlty. Algorithm 1 pits our ovrll spins n til rution strtgy. W prorm rough plmnt to gnrt ors nsity mp nsuring tht th ut-lin uring prtitioning oini with th til ounris (Lin 1). Th wirlngth inrs ugt is st to k% o th originl wirlngth (Lin 2). For h horizontl trunk in th pltorm, w go ovr ll th vrtil spins onnt to it. Ths spins r sort in nonrsing orr o th numr o lls in ll th tils rivn y th orrsponing vrtil spin (Lin 4-5). Thn, th sort st o spins is itrt ovr whil trying to vit th lls in it using prour EvitSpin. Th shm or ruing th numr o tils is lso similr (Lin 8-10) whrin th prour EvitTil is xut or h til in sort orr. W now sri Algorithm 2 n Algorithm 3 whih implmnt prour EvitSpin n EvitTil rsptivly. 397

4 Algorithm 1 Vrtil Spin n Til Minimiztion 1: Prorm Rough Plmnt 2: BUDGET = k % o wirlngth o sign {Minimiz spin utiliztion in nxt lok} 3: or ll Horizontl Spin hs o 4: CONN = All vrtil spins onnt to hs 5: Sort CONN y numr o lls in it 6: or ll Vrtil Spin vs onnt to CONN o 7: EvitSpin(vs, BUDGET) {Minimiz til utiliztion in nxt lok} 8: T = All tils in pltorm 9: Sort TILES y numr o lls in it 10: or ll Til t in TILES o 11: EvitTil(vs, BUDGET) Algorithm 2 EvitSpin(Spin S, BUDGET) 1: SL(SR) = Spin on lt(right) o S 2: REST = Tils in SL SR 3: or ll Til t in S o 4: NGHBR = All tils in REST <= 1 til wy rom t 5: Buil low twn t n NGHBR 6: A Constrint or WL Inrs < BUDGET 7: i Flow Possil thn 8: Mov lls rom tils in S to SL or SR Algorithm 2 whih tris to vit givn spin works s ollows. For trgt urrnt spin ing vit, th list o ll tils in th spins to th lt n right o it is otin (Lins 1-2). Nxt w writ ntwork low ormultion whr ll th lls rom h til longing to th urrnt spin r mov out o th spin. For h til in th spin, th possil lotion o intrst r ll th til jnt to it xpt itsl (Lin 3-5). W limit th lls to mov to only jnt tils to ru wirlngth pnlty. Th ojtiv o th ntwork low is to minimiz th stimt wirlngth inrs u to th movmnt. An itionl onstrint is to oun th mximum ptl wirlngth inrs (Lin 6). I th ntwork low is possil, th spin S n vit n its lls r mov out. Algorithm 3 EvitTil (til T, BUDGET) 1: Gt xavg = vrg X oorint o lls in T 2: Gt yavg = vrg Y oorint o lls in T 3: Comput Up/Dn/L/RtConn or T 4: NGHBR = All nighors o tils T 5: or ll tils n in NGHBR o 6: i n is n mpty til, ontinu; 7: movx = n s ntr X oorint - xavg 8: movy = n s ntr Y oorint - yavg 9: WLINCR = movx (LConn - RtConn) 10: WLINCR += movy (DnConn - UpConn) 11: A low rom T to n with ost WLINCR 12: A Constrint or WL Inrs < BUDGET 13: i Flow Possil thn 14: Evit T n mov lls Algorithm 2 n only vit on whol spin t tim. Howvr, thr n mny snrios whr w (ut not ll) tils o spin hv smll numr o lls in it n n vit. For this, Algorithm 3 works on h til in th sign. For h til, w in th vrg x n y oorint (XAvg n YAvg) o th lls in it (Lin 1-2). W lso omput our numrs (Rt- Conn, UpConn, LConn, DnConn) whih rprsnt th numr o nts inint on ny ll in th til whos ouning ox is stritly to th right, ov, on lt, or low this til (Lin 3). Th intuition is tht i ll th lls o this til r mov to nothr til, th inrs in wirlngth y this mov n pproximt y omintion o ths numrs. Nxt, w itrt ovr ll ight physilly ontiguous tils roun th trgt til (Lin 5) whih r th possil stintions whil omputing th stimt wirlngth inrs (Lin 7-10). A ntwork low prolm is uilt n i thr is lgl solution to it, th til T n vit (Lin 13-14). Atr th trmintion o Algorithm 1, w otin th lrgst st o omplt spins n tils whih n vit unr givn wirlngth inrs ugt. Bs on this inormtion, w trnsorm th plmnt prolm y ing ix lokgs ovring th unus tils. This trnsorm plmnt prolm oms th input to RgPl glol plr. 4.3 Column Minimiztion Atr th glol plmnt n lok lgliztion hs n prorm, omintionl (i.. LOGC) n squntil lls longing to multipl loks oul istriut in h til. To xploit this lxiility, w pply Algorithm 4 to rtngulr pphol M tils wi n N tils high. On th numr o powr up olumns in th pphol is ru, th pphol is mov to th nxt jnt position n Algorithm 4 is rrun. I th whol pltorm onsists tils tht is W wi n H high, Algorithm 4 is xut W-M H-N tims. Now w sri th Algorithm 4 Column Count Rution 1: T = All tils in urrnt pphol 2: N = Mximum lls in olumn 3: C = All loks in T NIL { NIL Clok onnts to omintionl ll i.. LOGCs} {Lt n i = lls o lok in til i} 4: or ll Clok C o 5: MOVES = φ 6: USED = P i T il(ni/n) 7: REQD = il( P i T ni)/n 8: i USED == REQD thn 9: ontinu; {Column ount lry optimiz} 10: or ll Til t T o 11: t.extr = n t - N loor(n t/n) 12: Sort T in non inrsing orr o Extr(t) 13: or ll Til t sort T o 14: OTHER(t) = T - {t}. Sort w.r.t. istn rom t. 15: or ll Til o sort OTHER o 16: trns = min(t.extr, N-o.Extr) 17: MOVES = MOVES {trns rom t to o} 18: i t.extr == 0 thn 19: rk 20: Implmnt ll MOVES stor stps involv in on invotion: W ummy lok ll NIL whih onnts to ll omintionl lls (i.. LOGC lls) (Lin 3). Th optimiztion is prorm or on lok typ t tim (Lin 4). Th mximum numr o lls tht n ommot in olumn is givn s N (Lin 2). W prun th ss or whih th numr o olumns oupi is lry optiml (Lin 6-9). For h til in th pphol, w omput th minimum ount o lls (Extr) tht, whn rmov, lv n intgrl multipl o N lls (Lin 10-11). All th tils in th pphol r sort oring to non-rsing Extr ount 398

5 (Lin 12). For h til, vry til xpt itsl is prosptiv til in whih th Extr lls n mov (Lin 14). To ru th impt on wirlngth inrs, w sort th prosptiv tils oring to istn rom th urrnt til (Lin 15) n try pushing th Extr lls o urrnt til into thm s long s this mov os not rt nw olumns in th prosptiv til (Lin 17-18). On ll th movs to ru th olumn ount or lok r ror, w tully implmnt thm y moving th lls mong th tils. Whn moving ll rom til A to til B, its nw lotion in til B is hosn s th point losst to th originl lotion in til A. 4.4 Column Assignmnt Atr th trmintion o Algorithm 4, th ision rgring lustring o ths lls into olumns n how th olumns or th irnt loks r rltivly pl, still ns to m. For this, w us Algorithm 5 whih runs on on til t tim n pks th lls into iniviul olumns. Algorithm 5 irst Algorithm 5 WL Awr Column Assignmnt 1: COLS = Columns in th til 2: N = Cpity o h olumn 3: BINS = φ 4: C = All loks in til NIL { NIL Clok onnts to omintionl ll i.. LOGCs} 5: or ll Clok C o 6: CLSTR = φ 7: L = lls o lok rom lt to right 8: or ll Cll i L o 9: CLSTR = CLSTR i 10: i siz o CLSTR == N thn 11: BINS = BINS CLSTR 12: CLSTR = φ 13: Assign BINS to COLS [ssignmnt prolm]. Cost o ssignmnt = inint wirlngth. 14: Swp lls twn olumns o sm lok to ru WL prorms gry lustring o lls o sm lok typ into ins o siz N (=pity o h olumn) strting th swp rom th lt g o th til (Lin 9-12). All th lls longing to on in orm on lustr n pl in on olumn. I th numr o ins us or pking is n th numr o olumns vill in th til is n, mpping th ins to n olumns n st s n Assignmnt Prolm n solv iintly using Munkrs lgorithm (Lin 13). Finlly, to rpir wirlngth grtion u to su-optiml lustring o lls into olumns, lls r swpp twn olumns o sm lok typ i it rus wirlngth. ) Input ) Clustring ) Colm Assign. ) WL Rution Figur 4: Column ssignmnt: ) Input. ) Clls lustr s on originl lotion. ) Columns ssign to h lustr. ) Atr WL rution y swpping Figur 4 shows n xmpl o olumn pking in tion. For this xmpl, h olumn n hv only 2 lls. Clls rivn y th sm lok typ hv th sm shp. Th lls r ivi in thr ins s shown in Figur 4-. Ths ins r ssign to iniviul olumns s shown in Figur 4-. Finlly, ll swpping my l to swpping o lls n to ru wirlngth. 5. EXPERIMENTAL SETUP W implmnt our low powr plmnt low PASAP in th C++ lngug insi th opn sour strutur ASIC plmnt tool RgPl [1]. All xprimnts wr run on 16 or, 1.6 GHz, Linux worksttion. W us GLPK [8] s th intgr linr progrmming (ILP) n ntwork low solvr n ustom implmnttion o Munkrs [9] lgorithm or ssignmnt prolm. Th wirlngth inrs ugt in Algorithm 1 ws st t 15%. Pltorm: Two irnt pltorms wr gnrt y rpliting th til sri in Stion 2.2. Th tils o ths pltorms r in Tl 2. Columns 2 n 3 show th numr o tims th til is rplit in horizontl n vrtil irtion rsptivly. Rst o th olumns init th mximum numr o LOGC, DFF, REG, RAM tht n ommot in th pltorm. Tl 2: Pltorm Chrtristis Plt Rp Rp Mx Mx Mx Mx Mx Nm X Y LOGC DFF REG RAM CLK A M 675k B M 811k Dsigns: Th nhmrks us wr originl rls y ASIC or th plmnt ontst. Tl 3 shows th rkup o th sign in trms o onstitunt lls. Th totl numr o lls rngs twn 125K to ovr 1 million. Column 6 shows th numr o glol lok signls us. Tl 3: Bnhmrk Chrtristis Nm LOGC DFF REG RAM CLK si1 832,824 87, si2 812,200 45, si3 961,063 52, si4 102,038 23, si5 913,853 84, RESULTS Tl 4 sris our xprimntl rsults ompring th plmnt gnrt y RgPl to PASAP plmnt. Th nhmrk nm in th irst olumn lso shows th pltorm on whih th nhmrk ws pl. For xmpl si4b intiis tht it is th nhmrk si4 pl on pltorm B. Th mtris ing ompr or th two plmnt r : ) unus spins, ) unus tils, ) unus olumns, ) wirlngth n ) totl CPU runtim. For h o ths mtris, thr su-olumns r shown in Tl 4. Ths su-olumns pit th vlu otin using RgPl (RP in tl), vlu otin using PASAP (PA in tl) n th irn twn ths two solutions rsptivly. Th iy opasap to inrs th numr o unus spins, tils n olumns is vint rom Tl 4. Du to th irnt nhmrk sizs n utiliztion rtio, th numrs vry wily mong th irnt iruits. Thror, in our isussion, w will primrily ous on th improvmnt/pnlty summ ovr ll th nhmrks. First o ll, w not tht ovr ll th nhmrks, nrly 58% xtr lok spins n turn o using 399

6 Tl 4: Inrs in numr o spin, til n olumn tht n powr own or vrious nhmrks. Bnh # Unus Spins # Unus Tils # Unus Columns Wirlngth (x10 6 ) CPU Runtim (s) Nm RP PA % RP PA % RP PA % RP PA % RP PA % si1a in si1b si2a 0 3 in si2b si3b si4a si4b si5b 0 4 in Totl: our mtho. Turning o spin irtly orrspons to lowr lok pitn. Bnhmrks si1a n si3b hs suh high utiliztion rtio tht oth RgPl n PASAP nnot in vn on unus spin. Similrly, th numr o unus tils n inrs y roun 29% thus giving signiint nhnmnt in th powr sving ility. As or th numr o unus olumns, thir numr improv y pproximtly 42% using PASAP s ompr to RgPl. Th vry low improvmnt in th numr o olumn us or nhmrk si4a n si4b is u to its vry smll siz whih implis vn y using RgPl, most o th olumns r unus. Th ov improvmnt in inrsing th ount o unus spin, tils n olumn oms t ost s sn in th wirlngth n runtim pnlty. Th wirlngth o th signs inrs y pproximtly 17%. Du to th runtim ssoit with rough plmnt gnrtion n ggrssiv spin/til/olumn rution, PASAP tks pproximtly 30% mor runtim tht RgPl. Though runtim grtion is not insigniint, w liv it is ir tr-o or th kin o powr svings possil with PASAP. To ompr th powr rution, th hng in plmnt mtris rom Tl 4 must onvrt to lok n lkg powr. Using th rltion riv in Eqn 1, th lkg powr sving hiv y prorming plmnt using PASAP s ompr to RgPl is plott in Figur 5. Eh olumn in Figur 5 orrspons to on nhmrk with th xption o lst olumn whih shows th vrg svings. PASAP rus th lkg powr in th rng o 7% to 40% with n vrg vlu o 17%. L k g R u tio n ( in % ) B n h m r k ( si * ) Figur 5: Lkg powr svings or plmnt gnrt y PASAP ompr to RgPl. Nxt w ompr th lok powr rution u to PASAP. By ggrssiv rution in th numr o spins, tils n olumns in whih th lok signl ns to istriut, PASAP n signiintly minimiz th lok swith pitn. Bs on th lok powr xprssion riv in Eqn 2, w plott th lok powr rution hiv y PASAP or irnt nhmrks in Figur 6. PASAP rus th lok powr o irnt nhmrk iruits in th rng o 20% to 60% with n vrg vlu o 32%. Th lok powr ws omput ssuming th rqunis o ll th lok signl in th strutur ASIC is th sm. C lo k P o w r R u tio n ( in % ) B n h m r k ( si * ) Figur 6: Clok powr svings or plmnt gnrt y PASAP ompr to RgPl. 7. CONCLUSIONS In this ppr, w propos powr wr strutur ASIC plmnt (PASAP) low. For givn strutur ASIC rhittur, PASAP minimizs th lkg powr n lok powr issiption y mximizing th vis tht n powr own n ruing th lok ntwork s swith pitn rsptivly. W propos lgorithms to minimiz th numr o lok spins, tils (th uiling lok o strutur ASIC pltorm) n olumns tht n to powr on, without signiintly impting th wirlngth o th sign. Exprimntl rsults on lrg tstss show tht PASAP n ru th lkg n lok powr onsumption y s muh s 40% n 60% rsptivly with 17% pnlty in wirlngth n 30% longr plr runtim. 8. REFERENCES [1] A. Chkrorty t l., Rgpl: A high qulity opn-sour plmnt rmwork or strutur sis, in Dsign Automtion Conrn, pp , ACM, [2] H. Shmit t l., Plmnt Chllngs or Strutur ASICs, in Intrntionl Symposium on Physil sign, pp , ACM, [3] ASIC Corport Wsit. [4] J. A. Roy t l., Cpo: Roust n Sll Opn-sour min-ut Floorplr, in Intrntionl Symposium on Physil sign, pp , ACM, [5] T. F. Chn t l., mpl6: Enhn Multilvl Mix-siz Plmnt, in Intrntionl Symposium on Physil sign, pp , ACM, [6] Q. Wng t l., Clok powr rution or virtx-5 pgs, in Proing o th Intrntionl Symposium on Fil Progrmml Gt Arrys, (Nw York, NY, USA), pp , ACM, [7] L. Wng t l., Fpg ynmi powr minimiztion through plmnt n routing onstrints, EURASIP J. Em Syst., vol. 2006, no. 1, pp. 7 7, [8] GNU Linr Progrmming Kit. [9] H. W. Kuhn, Th Hungrin Mtho or th Assignmnt Prolm, Nvl Rsrh Logistis Qurtrly, vol. 2, pp ,