A Low Noise and Reliable CMOS I/O Buffer for Mixed Low Voltage Applications
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1 Proings of th 6th WSEAS Intrntionl Confrn on Miroltronis, Nnoltronis, Optoltronis, Istnul, Turky, My 27-29, A Low Nois n Rlil CMOS I/O Buffr for Mix Low Voltg Applitions HWANG-CHERNG CHOW n YOU-GANG CHEN Dprtmnt n Grut Institut of Eltronis Enginring, Chng Gung Univrsity 259 Wn-Hw 1 st Ro, Kwi-Shn, To-Yun 333 TAIWAN, REPUBLIC OF CHINA hhow@milhttp:// Astrt: - In this ppr th sign of high voltg tolrnt n rlil CMOS I/O uffr is propos without using thik-oxi vis. In this prsnt sign for mix low voltg intrf pplitions, it uss simplr strutur n thrfor th iruit hs goo gt-oxi rliility. In ition, it is fr of lkg urrnt. No itionl p for ul powr supplis is rquir in th propos iruit. Th pull-up oprtion inluing oth th ris-tim n powr-ly prout is ru out 2%. Th simpl strutur ls to 5% r sving s ompr to th xisting prior rt. Ky-Wors: - I/O uffr, Mix low voltg, Intrf, Singl p, DC lkg 1 Introution With th vnmnt of th pross thnology, th vi imnsion sls own n th stnr powr supply voltg lso rus to lowr lvl. Howvr, for systm sign, it is hr to onvrt ll high voltg (for xmpl 5V, 3.3V or 2.5V) omponnts into low voltg (1.8V) intgrt iruits u to th ost onsirtion. Bus of ths fts, thr r usully iffrnt supply voltgs us so tht th trnsmission of signls twn high n low voltg iruits hs som prolms. This uss th sir for th mix low voltg intrf pplitions. 2 Prior Art As shown in Fig. 1, it is onvntionl CMOS input/output (I/O) uffr. Whn th signl is, it is n output uffr n whn th signl is 1, it is n input uffr (in tri-stt mo). Whn th uffr oprts s n input uffr n th signl in is H, mny ig prolms ris. For xmpl, th first, rliility prolms in gtoxi of strong PMOS n NMOS r suffr u to th high ltri fil rsulting from high voltg iffrn of th gt-rin n gtsour trminls. Bus trnsistors r gnrlly frit with thin gt-oxi, thy nnot tolrt th high voltg iffrn n th oxi n only tolrt 2%~3% highr thn th nominl supply voltg [1]. Thrfor, thin gt-oxi will rk own u to ovrstrss [1]. Th son prolm is tht th voltg in nos n shoul n V to turn th strong PMOS n NMOS off n thrfor thr is no stti powr onsumption. Howvr, unr th high voltg input signl onition, th prsiti io of PMOS to wll will onut urrnt u to forwr is. Th othr lkg pth is from p to vi th pull-up PMOS hnnl sin th high voltg uss th V DG (voltg iffrn twn rin n gt of PMOS) is lrgr thn its thrshol voltg Vtp. Ths two-lkg pths will l to xtr powr onsumption n wrong oprtions. Fig. 1 A onvntionl 1.8V I/O uffr rivn y 2.5V input signl Thr r som prior rt iruits propos to solv ths prolms [2]-[8]. Th us of thik- oxi vi n th stk NMOS n ovrom th gtoxi ovrstrss prolms [2]. An th son powr supply (H ) onnt to th pullup PMOS N-wll n solv th lkg urrnt =1.8V H=2.5V v H
2 Proings of th 6th WSEAS Intrntionl Confrn on Miroltronis, Nnoltronis, Optoltronis, Istnul, Turky, My 27-29, prolms [3]. Howvr, ths solutions lso hv fw rwks. Th first on is tht th us of thikoxi vis ns ul-oxi pross. Th son rwk is tht th son powr ns n itionl oning p. Thrfor, prior rt iruit tht n limint th prolms sri ov is propos [4], s shown in Fig. 2. In this iruit, it uss thniqu ll floting N-wll. Although it ovroms th prolms ut th us of mny itionl trnsistors mks th iruit omplit. As shown in Fig. 3, in this prior rt iruit [5], it uss only 4 itionl trnsistors to rliz th funtion. It rus th omplxity of th iruit sign ut th trnsistor ns thik-oxi vi n th sris strutur of th two lrg PMOS trnsistors ns mor r to hiv th iruit lyout n grs th ris-tim. is th min iruit. Th propos iruit uss th thniqu of floting N-wll. Th iruit oprtion is sri in th following. Pr-rivr iruit M M M M M M f MP8 Fig. 4 Th propos mix-voltg input/output uffr MN5 P7 Whn =, it is for output uffr us. As shown in Fig. 5, whn th input signl is 1, th no is ishrg to V n th no is lso ishrg to V. Thrfor th voltg is pull up to y n is turn off. Bus th no voltg is ishrg to V, th voltg n pull up to y vi. Fig. 2 Th prior rt 1 mix-voltg input/output uffr pu B As shown in Fig. 6, whn th input signl is, th no is initilly pull up to - Vtn(mn3) n th no is pull up to. Thrfor, is turn on n th no voltg is ishrg to V. So th no voltg n pull up to to turn ompltly off. Bus th no voltg is, th voltg n pull up to y. M M M M Fig. 3 Th prior rt 2 mix-voltg input/output uffr M M 3 Propos Ciruit Th propos CMOS I/O uffr is shown in Fig. 4. Th lft prt is pr-rivr iruit n th othr prt Fig. 5 Th propos iruit for output uffr us. (= 1 )
3 Proings of th 6th WSEAS Intrntionl Confrn on Miroltronis, Nnoltronis, Optoltronis, Istnul, Turky, My 27-29, M M Thrfor, th oul gur ring strutur shoul ppli to voi th lth-up prolm. M M M M M M H M Fig. 6 Th propos iruit for output uffr us.(= ) M M M H M M () M M M M Fig. 7 Th propos iruit for input uffr us (= 1 ) Whn = 1, it is for input uffr us, s shown in Fig. 7. It mns tht oth n r in off stt. As shown in Fig. 8(), whn th input high signl vi th is H, th no voltg n pull up to H y n th no voltg is pull to -Vtn(). Thrfor, is turn off n is turn on to pull th no voltg to H to kp off. Th voltg is pull to H y us th gt voltg of is. As for th s tht th input high signl vi th is (V), th tils r shown in Fig. 8(). Thrfor, thr r no lkg urrnt pths n no gt-oxi ovrstrss onition in th vis in th propos iruit for ll input onitions. Bus th propos iruit uss th thniqu of floting N-wll, th lth-up prolm my ris. M M M M M M () Fig. 8 input uffr () =H () =V 4 Rsults n Disussions Th simultion rsults r prform s on TSMC.18μm CMOS pross y Hspi. In Fig. 9, it is th omprison of ris-tim twn th propos iruit n prior rt 2 iruit [5] (Fig. 4) unr 5MHz with 15pF lo in output uffr mo. It is ovious tht th pull-up sp in th
4 Proings of th 6th WSEAS Intrntionl Confrn on Miroltronis, Nnoltronis, Optoltronis, Istnul, Turky, My 27-29, propos iruit is fstr thn tht of th prior rt 2 iruit. to H. This onition my us lth-up. As for th omplt mix-voltg I/O simultions, th rsults r givn in Fig. 12. Fig. 9 Th omprison of ris-tim twn th propos iruit n prior rt 2 iruit In Fig. 1, it is th omprison of th voltg mong th propos iruit, prior rt iruit [4] n prior rt iruit [5] oprting s n output uffr t 5 MHz with 15pF lo. From th wvform, th voltg in prior rt iruit [5] is lowr. It my us th prsiti io forwr is n rsults in lth-up. Fig. 11 Th omprison of th voltg mong th propos iruit, prior rt iruit [4] n prior rt iruit [7] s n input uffr t 1 MHz in 3.3V Fig. 12 Complt mix-voltg I/O simultion rsults Fig. 1 Th omprison of th voltg mong th propos iruit, prior rt iruit [4] n prior rt iruit [5] s n output uffr t 5MHz In Fig. 11, it is th omprison of th voltg mong th propos iruit, prior rt iruit [4] n prior rt iruit [7] oprting s n input uffr t 1 MHz in 3.3V. From th wvform, whn th input signl is H, th voltg n hng to H with th voltg. Thrfor, it n gt goo gt-oxi rliility n hs no lkg pth. Howvr, th voltg of th prior rt iruit kps floting n nnot hng As shown in Tl 1, it is th prformn omprison mong th prior rt 1 [4], prior rt 2 [5], n propos iruits. In this tl, whr Trp n Tfp: ris-tim n fll-tim in, rsptivly; Tr n Tf: rising n flling propgtion ly twn input signl () n output signl (), rsptivly; PDP-r n PDP-f: powr-ly (Tr or Tf) prout; itionl trnsistors: vis xpt th lrg n. Th trnsistor ount of itionl vis in th propos iruit is 8 s ompr to 11 in prior rt 1. Thrfor, th iruit omplxity is fftivly ru 27% whil it lso
5 Proings of th 6th WSEAS Intrntionl Confrn on Miroltronis, Nnoltronis, Optoltronis, Istnul, Turky, My 27-29, monstrts out 1% pull-up sp nhnmnt. As ompr to prior rt 2, th pull-up sp inluing oth th ris-tim n PDP is out 2% improvmnt whil th r is ru to only hlf. Thrfor, th propos iruit hs highr sp prformn, ttr lth-up immunity, lowr iruit omplxity, n vry smllr r. 5 Conlusion In this ppr, th sign of high voltg tolrnt n rlil CMOS I/O uffr hs n propos without using thik-oxi vis. In this prsnt sign for mix low voltg intrf pplitions, it uss simplr strutur n thrfor th iruit hs goo gt-oxi rliility. In ition, it is fr of lkg urrnt. No itionl p for ul powr supplis is rquir in th propos iruit. Th pull-up oprtion inluing oth th ris-tim n powr-ly prout is ru out 2%. Th simpl strutur ls to 5% r sving s ompr to th xisting prior rt. Thrfor, th propos I/O uffr is vry suitl for mix low voltg intrf pplitions. Rfrns: [1] A. -J. Annm, G.J.G.M. Gln, n P.C. Jong, 5.5-V I/O in 2.5-V.25-μm CMOS thnology, IEEE Journl of Soli-Stt Ciruits, Vol. 36, 21, pp [2] K. Bult, Anlog ron ommunition iruits in pur igitl p su-niron CMOS, in Dig. Th. Pprs Int. Soli-Stt Ciruits Conf., 1999, pp [3] M. Assr t l., CMOS low powr mix voltg iirtionl I/O uffr, US Ptnt #5,3,835, April [4] M. Plgrom n E. Dijkmns, A 3/5 V Comptil I/O Buffr, IEEE J. Soli-Stt Ciruits, Vol. 3, 1995, pp [5] H. -C. Chow, Biirtionl uffr for mix voltg pplitions, Proings of th 1999 IEEE Intrntionl Symposium on Ciruits n Systms, Vol. 1, 1999, pp [6] D. -Y. Chn, Dsign of mix 3.3 V n 5 V PCI I/O uffr, 2n Intrntionl Confrn on ASIC, 1996, pp [7] M. -D. Kr n C. -S. Tsi, Dsign of 2.5 V/5 V mix-voltg CMOS I/O uffr with only thin oxi vi n ynmi N-wll is iruit, Proings of th 23 Intrntionl Symposium on Ciruits n Systms, Vol. 5, 22, pp [8] G. P. Singh n A. B. Slm, High-Voltg- Tolrnt I/O Buffrs with Low-Voltg CMOS Pross, IEEE J. Soli-Stt Ciruits, Vol. 34, 1999, pp *Th softwr support from th Chip Implmnttion Cntr of Tiwn is knowlg. Tl 1 Prformn omprison 5MHz/15pf prior rt 1 prior rt [6] prior rt 2 prior rt [7] propos Powr(mW) improvmnt -.59% 5.7% -.29% 8.6% Trp(ns) improvmnt 7.% 1.27% 19.5% 12.6% --- Tfp(ns) improvmnt % 6.1% -.33% 7.7% --- Tr(ns) improvmnt 6.8% 8.25% 17.6% 23.2% --- Tf(ns) PDP-r(W*s) 5.98E E E E E-11 improvmnt 1.5% 13.35% 12.6% 26.2% --- PDP-f(W*s) 4.412E E E E E-11 improvmnt -.45% 6.1% 1.9% 8.6% --- Aitionl trnsistors improvmnt 27.2% -25% -5% 27.2% --- Ar(um) improvmnt 1.6% % 1.3% ---
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