EEO 401 Digital Signal Processing Pro. Mark Fowler Note Set #14 Practical A-to-D Converters and D-to-A Converters Reading Assignment: Sect. 6.3 o Proakis & Manolakis 1/19
The irst step was to see that this is possible: Can we recover the signal rom its ideal samples???!!! x(t) C-T Signal ADC x[n] D-T Signal Clock DAC xˆ ( t) C-T Signal Now that we have the basic theory or ideal sampling How do real ADCs and DACs work?? What are the important aspects to take into account? Quantization issues in the ADCs Sample-and-Hold issues in the DACs /19
Practical Analog-to-Digital Converter Quantizer Stream o binary words x(t) b bit Binary Words x q [n] t ADC t 3/19
Ideal Quantization Operation An ADC s number o bits sets the number o levels Let b = # o bits used to represent a level There will be b quantization levels Each level = (integer) where = ADC resolution or step size Sampled analog value converted to closest quantization level 4 3 3 x q = round(x/ ) x q [n] t Ideal ADC Specs Full-Scale Voltage: V max Number o bits: b Resolution: = V max / b Dynamic Range (DR) Signal-to-Noise Ratio (SNR) 4/19
Dynamic Range o Ideal ADC DR = (Power o Max Signal) / (Power o Min Signal) Max Signal = Sinewave with Amplitude o Full Scale Min Signal = Smallest Sinewave That Can Change LSB = / P max max V = = b ( ) = b 8 P min min = V = ( ) = 8 DR Pmax b 8 = 10log10 = 10log10 = 6.0b P min 8 (db) Signal Just Below Min Signal / / t 6 db o DR per Bit b DR 8 48 db 10 60 db 1 7 db 14 84 db 16 96 db 5/19
Ideal Quantization Adds Noise Quantized Signal = Original + Noise x [ k] = x[ k] e [ k] q + q x q [k] error / 4 3 / e q [k] = x q [k] x[k] 3 t / t 6/19
Ideal Quantization Noise Model Need a Statistical Model Prob. Density Function (PDF) Power Spectral Density (PSD) / Auto-Correlation Function (ACF) Assume that no error value is more likely than others PDF = Uniormly Distributed: U[ /, /] Histogram o Error - / error / Assume that error then does not aect error now Error is uncorrelated aka white noise PSD is lat ( white ) S q ( ) = N o 7/19
Ideal Quantization Noise PSD PSD w/o Quantization Signal = 3 Sines DFT (db) DFT (db) 0-10 -0-30 -40-5 -4-3 - -1 0 1 3 4 5 Frequency (khz) 0-10 -0-30 -40-5 -4-3 - -1 0 1 3 4 5 Frequency (khz) PSD w/ 5 Bit Quantization 8/19
Ideal ADC SNR Signal-to-Noise Ratio (SNR) SNR ADC = (Signal Power) / (Quant Noise Power) Uniorm Quantization Noise: U[ /, /] So Noise Power is. / { q } P = E e [ k] = e (1 / ) de = q / ADC Specs usually give SNR or Full-Scale Sinewave P max max V = = b ( ) = b 8 [ ] b 8 b P SNR 3 4 max ADC, max = = = P q 1 SNR ADC, max ( db) = 6.0b + 1.76 9/19 1
Ideal ADC SNR & Peak Factor SNR ADC,max is only or Full-Scale and Sinusoid For other cases: SNR ADC ( db) = 6.0b + C where C 1. 76 db where C depends on Signal Level and Signal s Peak Factor (PF) Peak Factor = (Signal Peak Value) / (Signal RMS) Low PF Signal High PF Signal t t 10/19
Impact o PF on Ideal ADC SNR SNR ADC (db) 90 80 70 60 50 40 30 0 Note: For Full-Scale Signals Only 14 bits 1 bits 10 bits 8 bits 6 bits 10-1 -18-15 -1-9 -6-3 Peak Factor (db) Max. Peak Factor Max. Result 11/19
Non-Ideal ADC Error Sources Nonlinearities Nonlinear Relationship Between Input/Output Levels 1 Output Value 0.5 0-0.5 Aperture Jitter Variations in Sample Times (aren t sampling on a regular time grid) Missing Output Code -1-1 -0.5 0 0.5 1 Input Value A Binary Code that Never Shows Up Regardless o Input Value These Errors Cause: Spurs in the Frequency Domain Increase in the SNR ADC 1/19
Eect o Non-Ideal Error Sources Signal Spikes 0 DFT (db) -5-10 -15-0 -5-30 -35 Spurs Noise Floor SFDR -40-5 -4-3 - -1 0 1 3 4 5 Frequency (khz) 13/19
Speciications or Practical ADCs These are common deinitions BUT check the data sheet! Signal-to-Noise Ratio (SNR) Ratio o Fundamental Sinusoid Power to Total Noise Power Power o Spurs is Excluded Signal-to-Noise-and-Distortion Ratio (SINAD) Ratio o Fundamental Sinusoid Power to Total Noise and Distortion Power Power o Spurs is Included Eective Number o Bits (ENOB) # o Bits or an Ideal ADC whose Theoretical SNR ADC = SINAD o Device ENOB = SINAD 1.76 6.0 Spurious-Free Dynamic Range (SFDR) Ratio o Fundamental Sinusoid Power to Largest Spur s Power 14/19
Practical Digital-to-Analog Converter x [n] = x (nt) Ideal Digital-to-Analog Converter Impulse Gen Clock at t = nt (DAC) ~ x ( t ) CT LPF xˆ ( t) Binary words o Samples Binary-to-Voltage Converter Sample & Hold CT LPF xˆ ( t) Clock at t = nt 15/19
Modeling the DAC s Sample & Hold Eect x [n] = x (nt) Ideal Digital-to-Analog Converter Impulse Gen Clock at t = nt (DAC) ~ x ( t ) CT LPF xˆ ( t) Sample & Hold Digital-to-Analog Converter x [n] = x (nt) Impulse Gen Clock at t = nt Sample & Hold CT LPF xˆ ( t) h S& H () t 1, 0 t T = 0, otherwise 16/19
x(t) Sample at t = nt ADC Hold Recall Ideal DAC Analysis DAC x[n] = x(nt) Impulse Gen CT LPF ~ x ( t ) xˆ ( t ) B A A/T X( ) B ~ 1 X ( ) = X ( + kf s ) T k= F s F s T H( ) F s F s A Xˆ ( ) Xˆ ( ) = X ( ) i Fs B 17/19
x(t) Sample at t = nt ADC Hold DAC w/ S&H Analysis x[n] Impulse Gen Sample & Hold DAC CT LPF xˆ ( t) F s F s *Attenuates Desired Signal * Passes Aliasing H S&H ( ) F s F s F s F s Can design to equalize S&H eect H( ) F s F s Xˆ ( ) 18/19
x(t) Sample at t = nt ADC Hold DAC w/ S&H Analysis Oversampling DAC x[n] Impulse Gen Sample & Hold CT LPF xˆ ( t) F s F s F s F s H S&H ( ) F s F s *Less Attenuation o Desired Signal * Aliasing arther out easier or LPF to remove H( ) Xˆ ( ) 19/19