Nanometer Transistors and Their Models Jan M. Rabaey
Chapter Outline Nanometer transistor behavior and models Sub-threshold currents and leakage Variability Device and technology innovations
Nanometer Transistors and Their Models Emerging devices in the sub-100 nm regime post challenges to low-power design Leakage Variability Reliability Yet also offer some opportunities Increased mobility Improved control (?) State-of-the-art low-power design should build on and exploit these properties Requires clear understanding and good models
The Sub-100 nm Transistor Velocity-saturated Linear dependence between I D and V GS Threshold voltage V TH strongly impacted by channel length L and V DS Reduced threshold control through body biasing Leaky Sub-threshold leakage Gate leakage Decreasing I on over I off ratio
I D versus V DS for 65 nm bulk NMOS transistor 1 10 4 I D (A) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 V GS = 1.0 V GS = 0.8 V GS = 0.6 V GS = 0.4 I D is a linear function of V GS 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 V DS (V) Early saturation Decreased output resistance
Drain Current Under Velocity Saturation I DSat = v Sat WC ox (V GS V TH ) 2 V GS V TH + E C L Good model, could be used in hand or MATLAB analysis = W L μ C eff ox V V V ) 2 I DSat DSat ( GS TH with V DSat = ( V V ) E L V GS TH C GS VTH + EC L [Ref: Taur-Ning, 98]
Models for Sub-100 nm CMOS Transistors Further simplification: The unified model useful for hand analysis Assumes V DSat constant [Ref: Rabaey, DigIC 03]
Models for Sub-100 nm CMOS Transistors unified model simulation 700 1.2V 600 500 linear 1.0V I DS [μa] 400 300 vel. saturation 0.8V 200 0.6V saturation 100 0.4V 0 0 0.2 V DSat 0.4 0.6 0.8 1 1.2 V DS [V]
Alpha Power Law Model Alternate approach, useful for hand analysis of propagation delay I DS W = μ C 2 L ox V GS V Parameter α is between 1 and 2. In 65 180 nm CMOS technology α ~ 1.2 1.3 α TH This is not a physical model Simply empirical: Can fit (in minimum mean squares sense) to a variety of α s, V TH Need to find one with minimum square error fitted V TH can be different from physical [Ref: Sakurai, JSSC 90]
Output Resistance Drain current keeps increasing beyond the saturation point Slope in I V characteristics caused by: Channel-length modulation (CLM) Drain-induced barrier lowering (DIBL). The simulations show approximately linear dependence of I DS on V DS in saturation (modeled by λ factor) (kω) [Ref: BSIM 3v3 Manual]
Thresholds and Sub-Threshold Current 8.0E 04 6.0E 04 Drain current vs. gate source voltage V DS = 1.2 V I DS [A] 4.0E 04 2.0E 04 0.0E+00 0 0.2 0.4 0.6 0.8 1 1.2 V THZ V GS [V]
Forward and Reverse Body Bias Threshold value can be adjusted through the fourth terminal, the transistor body. 0.5 Forward bias restricted by SB and DB junctions 0.45 V TH (V) 0.4 0.35 0.3 Reverse bias Forward bias 0.25 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 V BS (V)
Evolution of Threshold Control Body-biasing effect diminishes with technology scaling below 100 nm. No designer control at all in FD SOI technology 0.15 130 nm 0.1 210 mv ΔV TH (V) 0.05 0 90 nm 65 nm 95 mv 55 mv 0.05 0.1 0.5 0 0.5 V BB (V)
Impact of Channel Length on Threshold Voltages With halo implants Long-channel threshold V TH L min (for small values of V DS ) L V TH [V] Partial depletion of channel due to source and drain junctions larger in short-channel devices Channel Length [m] Simulated V TH of 90 nm technology
Impact of Channel Length on Threshold Voltages 1 0.9 Normalized leakage current 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 50 100 150 200 250 300 350 400 Length (nm) 50% increase in channel length decreases leakage current by almost a factor of 20 for 90 nm technology
Drain-Induced Barrier Lowering (DIBL) In a short-channel device, source drain distance is comparable to the depletion region widths, and the drain voltage can modulate the threshold V TH = V TH0 λ d V DS V TH Short channel V DS = 0.2V V DS = 1.2V Long channel Channel 0 (S) L (D)
MOS Transistor Leakage Components G Gate leakage S D Junction leakage D S leakage B(W)
Sub-threshold Leakage The transistor in weak inversion 3 V DS = 1.2V 4 G log I DS [log A] 5 6 7 S C i C d Sub D 8 Sub-threshold slope S = kt/q ln10 (1+C d /C i ) 9 0 0.2 0.4 0.6 0.8 1 1.2 V GS [V] Drain leakage current varies exponentially with V GS Sub-threshold swing S is ~ 70 100 mv/decade
Impact of Reduced Threshold Voltages on Leakage four orders of magnitude 300 mv Leakage: sub-threshold current for V GS = 0
Sub-threshold Current Sub-threshold behavior can be modeled physically 2 VGS VTH VDS V = GS VTH W kt nkt q = kt q nkt q I DS 2nμCox e 1 e I Se 1 e L q VDS kt q 2 W kt where n is the slope factor ( 1, typically around 1.5) and I S = 2nμCox L q Very often expressed in base 10 VGS VTH S I DS = I S 10 1 10 nvds S 1 for V DS > 100 mv kt where S = n ( ) ln(10), the sub-threshold swing, ranging between 60 mv and 100 mv q
Sub-threshold Current - Revisited Drain-Induced Barrier Lowering (DIBL) Threshold reduces approximately linearly with V DS V TH = V TH 0 λ V Body-Biasing Effect Threshold reduces approximately linearly with V BS V = V γ V Leading to: TH TH 0 d d DS BS γ nvds = S VGS VTH 0 + λdvds + dvbs S I DS IS10 1 10 Leakage is an exponential function of drain and bulk voltages
Sub-threshold Current as a Function of V DS I D (A) 4.5 10 9 4 3.5 3 2.5 2 1.5 1 0.5 λ d = 0.18 S = 100 mv/dec DIBL Two effects: diffusion current (like in bipolar transistor) exponential increase with V DS (DIBL) 3 10x in current technologies 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 V DS (V) I D versus V DS for minimum size 65 nm NMOS transistor (V GS = 0)
Gate-Induced Drain Leakage (GIDL) Excess drain current is observed, when gate voltage is moved below V TH, and moves to negative values (for NMOS) More pronounced for larger values of V DS (or GIDL ~ V DG ) High electrical field between G and D causes tunneling and generation of electron hole pairs Causes current to flow between drain and bulk Involves many effects such as band-toband direct tunneling and trap-assisted tunneling [Ref: J. Chen, TED 01] IEEE 2001
Combining All Drain-Leakage Effects 10 4 10 6 V DS = 2.5 V I D (A) 10 8 GIDL V DS = 1.0 V V DS = 0.1 V 10 10 90 nm NMOS 10 12 0.4 0.2 0 0.2 0.4 0.6 0.8 1 1.2 V GS (V)
Gate Leakage Introduction of high-k dielectrics Gate 1.2 nm SiO 2 Silicon substrate Scaling leads to gate-oxide thickness of a couple of molecules Causes gates to leak! MOS digital design has always been based on the assumption of infinite input resistance! Hence: Fundamental impact on design strategy! [Ref: K. Mistry, IEDM 07]
Gate-Leakage Mechanisms 1E 07 I 1E 08 ox /E 2 1E 09 A*cm 2 /MV 2 1E 10 1E 11 1E 12 1E 13 1E 14 1E 15 IEEE 2000 60 80 Å FN tunneling <50 Å Direct-oxide tunneling 0.1 0.15 0.2 1/E (MV/cm) 1 0.25 Direct-oxide tunneling dominates for lower T ox [Ref: Chandrakasan-Bowhill, Ch3, 00]
10 9 T ox Direct-Oxide Tunneling Currents J G (A/cm 2 ) 10 6 10 3 10 0 10 3 10 6 10 9 V DD trend 0 0.3 0.6 0.9 1.2 1.5 1.8 0.6 nm 0.8 nm 1.0 nm 1.2 nm 1.5 nm 1.9 nm J G : exponential function of oxide thickness and applied voltage Vox 1 (1 ) ΦB α Vox / Tox J G e 3/2 V DD Also - Gate tunneling a strong function of temperature - Larger impact for NMOS than PMOS [Courtesy: S. Song, 01]
High-k Gate Dielectric T ox SiO 2 T g High-k Material Electrode Electrode Si substrate Si substrate Equivalent Oxide Thickness = EOT = T ox = T g * (3.9/ε g ), where 3.9 is relative permittivity of SiO 2 and ε g is relative permittivity of high-k material Currently SiO 2 /Ni; Candidate materials: HfO 2 ( ε eff ~15 30); HfSiO x ( ε eff ~12 16) Often combined with metal gate Reduced Gate Leakage for Similar Drive Current
High-k Dielectrics Gate 1.2 nm SiO 2 Gate electrode 3.0nm High-k Silicon substrate Silicon substrate High-k vs SiO 2 Benefits Gate capacitance Gate dielectric leakage 60% greater Faster transistors >100% reduction Lower power Buys a few generations of technology scaling [Courtesy: Intel]
Gate Leakage Current Density Limit Versus Simulated Gate Leakage [Ref: ITRS 2005]
Temperature Sensitivity Increasing temperature Reduces mobility Reduces V TH I on decreases with temperature I off increases with temperature I on /I off 10 104 I DS 9 8 90 nm NMOS 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 Temp( C) increasing temperature V Gs
Variability Scaled device dimensions leading to increased impact of variations Device physics Manufacturing Temporal and environmental Impacts performance, power (mostly leakage) and manufacturing yield More pronounced in low-power design due to reduced supply/threshold voltage ratios
Variability Impacts Leakage 1.4 Normalized Frequency 1.3 1.2 1.1 1.0 30% 5X 130 nm 0.9 1 2 3 4 5 Normalized Leakage (I( I sb ) Threshold variations have exponential impact on leakage [Ref: P. Gelsinger, DAC 04]
Variability Sources Physical Changes in characteristics of devices and wires. Caused by IC manufacturing process, device physics & wear-out (electro-migration). Time scale: 10 9 s (years). Environmental Changes in operational conditions (modes), V DD, temperature, local coupling. Caused by the specifics of the design implementation. Time scale: 10 6 to 10 9 s (clock tick).
Variability Sources and Their Time Scales
Process Variations 3σ/mean 40% 30% 20% 10% 0% L eff w, h, ρ T ox, V TH 250 180 130 90 65 Technology Node (nm) Percentage of total variation accounted for by within-die variation(device and interconnect) [Courtesy: S. Nassif, IBM] L (nm) 250 180 130 90 65 45 V TH (mv) 450 400 330 300 280 200 σ(v TH ) (mv) 21 23 27 28 30 32 σ(v TH )/V TH 4.7% 5.8% 8.2% 9.3% 10.7% 16%
Threshold Variations Most Important for Power Mean Number of Dopant Atoms 10000 1000 100 10 1000 500 250 130 65 32 Technology Node (nm) Decrease of random dopants in channel increases impact of variations on threshold voltage [Courtesy: S. Borkar, Intel]
Device and Technology Innovations Power challenges introduced by nanometer MOS transistors can be partially addressed by new device structures and better materials Higher mobility Reduced leakage Better control However Most of these techniques provide only a one (or two) technology generation boost Need to be accompanied by circuit and system level methodologies
Device and Technology Innovations Strained silicon Silicon-on-Insulator Dual-gated devices Very high mobility devices MEMS transistors DG-SOI GP-SOI FinFET
Strained Silicon Improved ON-Current (10 25%) translates into: 84 97% leakage current reduction or 15% active power reduction [Ref: P. Gelsinger, DAC 04]
Strained Silicon Improves Transistor Performance and/or Reduces Leakage Transistor Leakage Current (na/μm) 1000 100 10 Std Strain Std Strain PMOS NMOS 1 0.2 0.4 0.6 0.8 1.0 +25% I ON +10% I ON 0.04 I OFF Transistor Drive Current (ma/μm) [Ref: S. Chou, ISSCC 05] 0.20 I OFF 1.2 1.4 1.6
Beyond Straining Hetero-junction devices allow for even larger carrier mobility Mobility (cm/s) 100000 10000 1000 Electrons (intrinsic) Si + strain ε Si Ge, GaAs InAs InSb 100 5.2 5.4 5.6 5.8 6 6.2 6.4 6.6 Lattice Constant (Å) Example: Si-Ge-Si heterostructure channel [Courtesy: G. Fitzgerald (MIT), K. Saraswat (Stanford)]
Silicon-on-Insulator (SOI) Thin silicon layer S G FD Thin Oxide Substrate D [Courtesy: IBM] Reduced capacitance (source and drain to bulk) results in lower dynamic power Faster sub-threshold roll-off (close to 60 mv/decade) Random threshold fluctuations eliminated in fullydepleted SOI Reduced impact of soft-errors But More expensive Secondary effects
Example: Double-Gated Fully Depleted SOI thin BOX (< 10nm) VT control dopant (10 18 /cm 3 ) G (Ni silicide) thin SOI (< 20 nm) STI D well sub S STI well sub well contact STI Buried gate provides accurate threshold control over wide range Threshold voltage V TH (V) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.1 1.0 High dose Low dose w/o IEEE 2004 VDD = 1.0 V t SOI = 20 nm t BOX = 10 nm 0.5 0.0 0.5 Well-bias voltage V well (V) 1.0 90 nm bulk 65 nm bulk 45 nm bulk 32 nm bulk 65 nm FD-SOI 45 nm FD-SOI 32 nm FD-SOI [Ref: M. Yamaoka, VLSI 04, R. Tsuchiya, IEDM 04] 0 σ int σext σ int σext σ (V T) σ (VT) 1 2 Standard deviation (a.u.)
FinFETs An Entirely New Device Architecture IEEE 1999 UC Berkeley, 1999 Suppressed short-channel effects Higher on-current for reduced leakage Undoped channel No random dopant fluctuations [Ref: X. Huang, IEDM 99] S = 69 mv/decade
BackGated FinFET Source Gate length = L G Gate Fin Width = Drain T Si Fin Height H FIN = W /2 Source Switching Gate Gate length = Gate1 Drain L G Gate2 Vth Control Fin Height H FIN =W FIN Double-gated (DG) MOSFET Back-gated (BG) MOSFET Independent front and back gates One switching gate and V TH control gate Increased threshold control
New Transistors: FinFETs Intel tri-gate Berkeley PMOS FinFET Manufacturability still an issue may even cause more variations Source Gate Drain [Courtesy: T.J. King, UCB; Intel]
Some Futuristic Devices FETs with sub-threshold swing < kt/q (I-MOS) Impact Ionization 1.0E 03 V S = 1V I-MOS Region ON Poly V D = 0V P + I-MOS Buried-Oxide [Courtesy: J. Plummer, Stanford] N + 1.0E 05 MOS 1.0E 07 5 mv/dec. L I = 25 nm L G = 25 nm 1.0E 09 OFF T ox = 1 nm T si = 25 nm 1.0E 11 0 0.2 0.4 0.6 Zero off-current transistor Uses MEMS technology to physically change gate control. Allows for zero-leakage sleep transistors and advanced memories [Ref: Abele05, Kam05] IEEE 2005
Summary Plenty of opportunity for scaling in the nanometer age Deep-submicron behavior of MOS transistors has substantial impact on design Power dissipation mostly influenced by increased leakage (SD and gate) and increasing impact of process variations Novel devices and materials will ensure scaling to a few nanometers
References Books and Book Chapters A. Chandrakasan, W. Bowhill, and F. Fox (eds.), Design of High-Performance Microprocessor Circuits, IEEE Press 2001. J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed, Prentice Hall 2003. Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998. Articles N. Abele, R. Fritschi, K. Boucart, F. Casset, P. Ancey, and A.M. Ionescu, Suspended-Gate MOSFET: Bringing New MEMS Functionality into Solid-State MOS Transistor, Proc. Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, pp.479 481, Dec. 2005 BSIM3V3 User Manual, http://www.eecs.berkeley.edu/pubs/techrpts/1998/3486.html J.H. Chen et al., An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET, IEEE Trans. On Electron Devices, 48(7), pp. 1400 1405, July 2001. S. Chou, Innovation and Integration in the Nanoelectronics Era, Digest ISSCC 2005, pp. 36 38, February 2005. P. Gelsinger, Giga-scale Integration for Tera-Ops Performance, 41st DAC Keynote, DAC, 2004, (www.dac.com) X. Huang et al., "Sub 50-nm FinFET: PMOS, International Electron Devices Meeting Technical Digest, p. 67. Dec. 5 8, 1999. International Technology Roadmap for Semiconductors, http://www.itrs.net/ H. Kam et al., A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics, IEDM Tech. Digest, pp. 463 466, Dec. 2005. K. Mistry et al., A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-free Packaging, Proceedings, IEDM, p. 247, Washington, Dec. 2007. Predictive Technology Model (PTM), http://www.eas.asu.edu/~ptm/ T. Sakurai and R. Newton. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas., IEEE Journal of Solid-State Circuits, 25(2), 1990. R. Tsuchiya et al., Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control, Proceedings IEDM 2004, pp. 631 634, Dec. 2004. M. Yamaoka et al., Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology, Digest of Technical Papers VLSI Symposium, pp. 288 291, June 2004. W. Zhao, Y. Cao, New generation of predictive technology model for sub-45nm early design exploration, IEEE Transactions on Electron Devices, 53(11), pp. 2816 2823, November 2006