IGITAL ESIGN COEN 32 Prof. r. A. J. Al-Khalili Time Allowed 3: hrs. April, 998 2 pages Answer All uestions No materials are allowed uestion a) esign a half subtractor b) esign a full subtractor c) Using Boolean Algebra implement a full subtractor with half subtrctors and an OR gate. d) If the exclusive OR gate has a delay of ns and an AN or OR gate has a delay of 5 ns what is the delay of this circuit? uestion 2 a) A logic circuit implements the following function F(A,B,C,) = A C + AC It is found that the circuit input combination A=C= can never exist. Find a simpler expression for F using don t care conditions. b) raw the logic diagram of a 2 to 4 decoder with only NOR gates. Include an enable input and show your circuit clearly with all inputs and outputs marked. c) Minimize the following Boolean expression F(A,B,C,) = AB + AC + BC uestion 3 a) Suppose two two bit numbers, A = aa and B = bb. Are to be compared. The comparator will have three outputs: A>B, A=B, and A<B. Assume that B & A are unsigned positionally coded integers. esign this circuit. b) Use a MUX to implement the B=A output. uestion 4 a) etermine the transition table and the transition equation of a -Latch. b) Explain what are the disadvantages of a transparent latch. c) Explain the operation of a Master-Slave Flip Flop. d) What is the s catching problem? uestion 5 Analyze the sequential circuit given below x A A B B A B Page of
a) erive the State Table, and the State iagram b) What sequences the circuit counts through as the clock ticks after power is applied? When the system is turned on, B A =. Consider output as B A. c) Starting from B A = draw timing diagram for the circuit for 4 clock pulses. You may assume ) positive edge triggered flip flop. 2) Flip Flops have a delay of ns. 3) system clock is MHz. uestion 6 esign a counter that counts through the following sequence,4,6,7,3,,, etc and keeps repeating the sequence. Page 2 of
Solutions uestion a) X Y h B h h = X Y BBh = X Y X Y h B h b) X Y B in B out XY B in = X Y B in + X Yb in + XYB in + XY B in = X Y B in B in XY B out = X Y +X YB in + X YB in = X Y + B in (X Y) c) = X Y B in = h B in B out = X Y + B in (X Y) = B h + B in h X Y h B in B out d) 2 x XOR d = 2 or XOR d + Inv d + AN d + OR d = + 5 + 5 = 2 (If Inv d = ) If Inv has delay great than zero, then elay = 2 ns + Inv delay. Page 3 of
uestion 2 a) F(A,B,C,) =A C + AC and A = C = is don t care C AB F = C+A X X X X b) A AB A B B AB A B E d) F = AB + AC +BC = AB(C +C ) + AC + BC = ABC + ABC + AC + BC = AC + BC Page 4 of
uestion 3 a) Input a a b b 2 3 4 5 6 7 8 9 2 3 4 5 Output A=B A<B A>B F = m (,5,,5) F2 = m (,2,3,6,7,) F3 = m (4,8,9,2,3,4) aa bb F = (A=B) = a a b b + a ab b + aabb + aa bb aa bb aa bb F2 = (A<B) = a b + a bb+a a b a a b b F2 = (A>B) = ab + ab b + aab = ab + ab (b + a) F F3 F2 Page 5 of
b) b a a b b b a a b a ab a ab aa b aa b A=B b aab aab a a b uestion 4 a) When clock is high Input Present State Next State + + = b) Page 6 of
c) The disadvantage of a transparent latch is that it has no control on input such as a clock, so when input changes, with some delay the output follows. This behavior makes it impossible to be used in a state machine or when input/output transitions require some control Master Slave d) Master turns on Slave turns off Master turns off Slave turns on In order to insure that one transition per clock cycle occurs and the precise time of transition is determined, the master-slave FF is used. ata may arrive when clock is high even with multiple transition on, the O/P does not change. When the clock is changed on the edge of clock change data is transferred to the slave which appears at the o/p after a Δt delay. Because of this data has to be set up at the input and only one transition per clock is insured. The M-S FF described is a negative edge triggered ata ue to finite clock edges and switching delay of devices a appearing at end of clock high (Glitch), is captured by clock during its transition. This is transferred to the slave when the clock goes low then corrupting the o/p. uestion 4 a) A = x A B = A B The State Table Present State A B Next State x = x= + A + B + A B + x = x= A B A B Page 7 of
The state iagram x = x = x = x = x = x = x = x = Reorganize x = x = x = x = x = x = x = x = b) x =, A B 2 2 x =, A B 3 2 A divider by two counters A divider by 4 counters c) μs 2 μs 3 μs 4 μs x = A B ns ns ns ns x = A ns ns ns ns B ns ns Page 8 of
uestion 6 Present State y2 y y Next State y2 + y + y + x = 4 X X X X X X x = x = 3 7 x = x = 6 x = Using binary state assignment Can not be further minimized Using a dlip flop, we may y y α X I I ϕ X I α ϕ ϕ β X ϕ β Ι X y2 + y + y y ϕ X α ϕ X β I I X X y + 2 = y2 + = y y y X X X X = y + = y2 = y + = y Page 9 of
Since this arrangement is minimal then there is no need to try another implementation. y2 y 2 y Page of