OMINTIONL IRUITS pplications Parity Generation and heking Even Parity P e P e P P P P P P5 P P6 ( ) = m(,, ) =, Odd Parity P o P e Three-bit Parity Generator ( ) = m(,,5, ) P P P P P P5 P P6 = 6 Three-bit Parity Generator P e P o ata P e Parity it P e for even parity ata P o Parity it P o for odd parity
OMINTIONL IRUITS pplications Parity Generation and heking 5 6 8-bit Parity Generator P e P o 5 6 P e 8-bit Even Parity hecker P e when P e = P e Transmitter - Receiver Parity Generator 8 Parity it even Parity hecker = Parity OK, activate receiver = Parity not OK, activate "alarm"
ecoders binary code of n bits is capable of representing up to n distinct elements of coded information. decoder is a combinational circuit that converts binary information from n input lines to maximum of n unique output lines. n - to - m line decoder n m = = = = = = = 5 = - to - 8 -line decoder pplications OMINTIONL IRUITS
OMINTIONL IRUITS pplications ecoders E = E Low level active E = E = E = E - to - -line decoder with ENLE input E
OMINTIONL IRUITS pplications ecoders E = E Low level active E = E = E = E - to - -line decoder with ENLE input and inverted outputs E 5
OMINTIONL IRUITS pplications ecoders Expanding ecoders E X8 decoder E to High level active X8 decoder E 8 to 5 6
OMINTIONL IRUITS pplications ombinational Logic Implementation with ecoder Implementation of a full adder i S o Truth Table of the full adder i X8 decoder 5 6 S
OMINTIONL IRUITS pplications ombinational Logic Implementation with ecoder SNLS8 G G G & G 5 6 Y Y Y Y Y Y5 Y6 Y 8 (ctive Low) Outputs : Y,..., Y 6 Inputs :,, and Enable Inputs G, G and G If G + G =, then Y i = High (i =,..., ) If G =, then Y i = High (i =,..., ) -line to 8-line decoder/demultiplexer G G G & G 5 6 Y Y Y F F (,, ) = + + (,, ) = 8
OMINTIONL IRUITS pplications ombinational Logic Implementation with ecoder 8 MSI decoder module (Medium Scale Integrated) The truth table of the 8 [] 9
OMINTIONL IRUITS pplications ombinational Logic Implementation with ecoder '5 MSI decoder module (Medium Scale Integrated) -line to 6-line decoder/demultiplexer The truth table of the 5 []
OMINTIONL IRUITS pplications ombinational Logic Implementation with ecoder ddress ecoding []
OMINTIONL IRUITS pplications ombinational Logic Implementation with ecoder onversion of encoded data to a format suitable for driving a numeric display (-segment display). f a g b e d c 5 6 8 9 Type has reversed diodes (common cathodes) esimal Point P 9 f e 8 a d g b c P 5 6 Type ssumption : LE is ON if F i =, where i = a, b, c, d, e, f, g LE is OFF if F i = -bit code. Variables are,,, ( is LS and is MS) n example of the seven-segment display HSP-56 Green
OMINTIONL IRUITS pplications ombinational Logic Implementation with ecoder F F F F F F F a b c d e f g (,,, ) = (,,,5,6,,8,9) = (,,,,,,8,9) = (,,,,5,6,,8,9) = (,,,5,6,8,9) = (,,6,8) = (,,5,6,8,9) = (,,,5,6,8,9) a b c d e f g 5 6 8 9 x x x x x x x x x x x x Truth table of the -segment decoder with active high outputs. -segment display driver (ctive high output) LS ctive low outputs Open-collector outputs Sink urrent = m Output Max. voltage = 5V LS9 ctive high outputs Open-collector outputs Sink urrent = 8m Output Max. voltage = 5.5V lanking input I LS9 a b c d e f g
OMINTIONL IRUITS pplications ombinational Logic Implementation with ecoder -segment display driver F e Segment e : (,,, ) = (,,6, 8) X X X X X X (,,, ) = + = ( ) F e + LS9 has blanking input i i Fe (,,, ) = ( + ) i = ( + ) i If lanking input is LOW, then F i = LOW
OMINTIONL IRUITS pplications Encoder n encoder is a combinational circuit which has s (or fewer) inputs and s output lines. In general : When encoder module has n inputs, then the number of output s must satisfy the expression : n inputs Encoder s outputs s n 5
OMINTIONL IRUITS pplications Encoder Octal-to inary encoder Only one input is allowed to be at same time. = I = I = I + I + I + I 5 + I + I + I 5 6 6 + I + I + I oolean functions for octal-to-binary encoder I I V Output is if I is or all inputs are. mbiguity We can add one extra output V, which is only if at least one input is. V = if all inputs are. V = I + + I + I + I + I + I5 + I6 I Implemented with three four-input OR-gates Note! We have different input combinations. Only seven input combinations are defined. Minimum logic implementation leads to the assumption that only one input I i in each time is allowed to be. 6
OMINTIONL IRUITS pplications Encoder Priority Encoder ctive high inputs V x x x x x x x x Truth Table of a -input Priority Encoder
OMINTIONL IRUITS pplications P P P P P P5 P P6 P P P 5 P P 8 P9 P P V = + + + P P P P X P P5 P P6 P P P 5 P P 8 P9 P P = + P P P P P X P5 P P6 P P P 5 P 8 P P P9 P = + Encoder Priority Encoder V 8
OMINTIONL IRUITS pplications Encoder MSI Priority Encoder module : [] 9
OMINTIONL IRUITS pplications Multiplexer (data selector) []
OMINTIONL IRUITS pplications Multiplexer (data selector) n input and n selection lines whose bit combinations determine which input is selected. Y i Y S Quadruple -to--line multiplexer = S + S where i =,,, i i Simple expansion to have a6-to- muxer -to- Multiplexer Y I I Y S Two- to -one - line multiplexer Y = S I + S I S Y Multiplexer with three-state gate I I S Y Logic diagram
OMINTIONL IRUITS pplications Multiplexer (data selector) We must ensure that only one three-state buffer has acces to the output while all other buffers are maintained in a high-impedance state. Y E S S Y x x z The truth table of the -to--line muxer with enable input Select Enable S S E X decoder -to--line muxer with Enable input
OMINTIONL IRUITS pplications Multiplexer (data selector) Implementing a three-input function with a 8x multiplexer EN 5 6 MUX Y W F F (,, ) = (,, ) (,, ) = (,,,5, 6) SNLS5
OMINTIONL IRUITS pplications Multiplexer (data selector) P i 5 6 8 9 5 6 5 Implementing a four-input function with a 8x multiplexer S S S F F = F = F = F = F = F = F = F = Truth table of the oolean function F (,,, ) (,,,,,,, ) F = = 5 S S S 5 6 8X MUX F
OMINTIONL IRUITS pplications Multiplexer Implementing a Parallel-to-Serial conversion with a X multiplexer S S S S S time S time Y ata valid (stable states) - Y time time S S 5
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