EC 413 Computer Organization rithmetic Logic Unit (LU) and Register File Prof. Michel. Kinsy
Computing: Computer Organization The DN of Modern Computing Computer CPU Memory System LU Register File Disks Main Memory Cache Comparator dder Multiplier Latch Decoder Controller RM Decoder Cacheline Line Selection Logic it Cell
rithmetic Logic Unit (LU) Recall our binary adder Cin Sum Cin Sum Cin Cout Single it Full dder (F) Cout
rithmetic Logic Unit (LU) How to support the 32 bits operations in the MIPS IS? Cin Sum Cout Single it Full dder (F)
rithmetic Logic Unit (LU) How to support the 32 bits operations in the MIPS IS? c 3 c 2 c 1. C in Cin Sum + 3 2 1 + 3 2 1 Cout Single it Full dder (F) C out S 3 S 2 S 1 S
rithmetic Logic Unit (LU) How to support the 32 bits operations in the MIPS IS? c 3 c 2 c 1. C in Cin Sum + 3 2 1 + 3 2 1 C out S 3 S 2 S 1 S 3 2 1 Single it Full dder (F) Cout 3 2 1 F F F F C 4 C S 3 C 3 S 2 C 2 S 1 1 S
rithmetic Logic Unit (LU) C out 3 2 1 3 2 1 LU (dder) C in c 3 c 2 c 1 C in. + 3 2 1 + 3 2 1 C out S 3 S 2 S 1 S S 3 S 2 S 1 S 3 2 1 3 2 1 F F F F C 4 C S 3 C 3 S 2 C 2 S 1 1 S
rithmetic Logic Unit (LU) Carry Propagate inary dder x 7 x 6 x 5 x 4 y7 y 6 y 5 y 4 x 3 x 2 x 1 x y3 y 2 y 1 y 3 2 1 3 2 1 3 2 1 3 2 1 C y C C y C S 3 S 2 S 1 S S 3 S 2 S 1 S S 7 S 6 S 5 S 4 S 3 S 2 S 1 S
rithmetic Logic Unit (LU) There are many ways to build these components dders Time Complexity Space Complexity Type Time Space Ripple Carry O(n) O(n) Carry Lookahead Carry Skip Carry Select O(log n) O(n log n) ( n ) ( n ) O(n) O(n)
Overflow Unsigned inary Numbers x 3 x 2 x 1 x y 3 y 2 y 1 y F F F F Carry 2 s Complement Numbers C 4 C S 3 C 3 S 2 C 2 S 1 1 S x 3 x 2 x 1 x y 3 y 2 y 1 y F F F F Overflow C 4 C S 3 C 3 S 2 C 2 S 1 1 S
rithmetic Logic Unit (LU) Preform 2 s complement subtraction with binary adder x y = x + (-y) = x + y + 1 x 3 x 2 x 1 x y 3 y 2 y 1 y 3 2 1 3 2 1 C y inary dder S 3 S 2 S 1 S C 1 S 3 S 2 S 1 S
rithmetic Logic Unit (LU) inary dder/subtractor Op: Control Signal (Operation) Op= à S = x + y Op=1 à S = x y Op x 3 x 2 x 1 x 3 y 2 y 1 y 3 y 2 y 1 y 3 2 1 3 2 1 C y inary dder S 3 S 2 S 1 S C S 3 S 2 S 1 S
rithmetic Logic Unit (LU) LU may contain multiple operation units Floating point unit S i g n E x p o n e n t S i g n i f i c a n d S i g n E x p o n e n t S i g n i f i c a n d S t a r t Exponents dder 1. C o m p a r e t h e e x p o n e n t s o f t h e t w o n u m b e r s. S h i f t t h e s m a l l e r n u m b e r t o t h e r i g h t u n t i l i t s e x p o n e n t w o u ld m a t c h t h e la r g e r e x p o n e n t E x p o n e n t d i f f e r e n c e 2. d d t h e s ig n if ic a n d s 1 1 1 3. N o r m a liz e t h e s u m, e i t h e r s h i f t i n g r ig h t a n d in c r e m e n t in g t h e e x p o n e n t o r s h if t in g le f t a n d d e c r e m e n t in g t h e e x p o n e n t Control S h i f t r i g h t Significands dder O v e r f l o w o r u n d e r f lo w? Y e s N o E x c e p t i o n 1 I n c r e m e n t o r d e c r e m e n t 1 S h i f t l e f t o r r i g h t 4. R o u n d t h e s i g n i f i c a n d t o t h e a p p r o p r i a t e n u m b e r o f b i t s N o S t i l l n o r m a l i z e d? R o u n d i n g h a r d w a r e Y e s S i g n E x p o n e n t S i g n i f i c a n d D o n e
rithmetic Logic Unit (LU) LU may contain multiple operation units Comparator unit Magnitude Comparator 3 2 1 3 2 1 < = > 3 3 3 3 3 x + = 2 2 2 2 2 x + = 1 1 1 1 1 x + = x + = 1 2 3 ) ( x x x x = = 1 2 3 1 1 2 3 2 2 3 3 3 ) ( x x x x x x + + + = > 1 2 3 1 1 2 3 2 2 3 3 3 ) ( x x x x x x + + + = <
rithmetic Logic Unit (LU) LU may contain multiple operation units Comparator unit 3 2 1 3 2 1 3 x 3 3 Magnitude Comparator 2 x 2 2 1 x 1 (<) < = > 1 x (>) (=)
rithmetic Logic Unit (LU) LU may contain multiple operation units Comparator unit x 7 x 6 x 5 x 4 y7 y 6 y 5 y 4 x 3 x 2 x 1 x y3 y 2 y 1 y 1 3 2 1 3 2 1 I (>) I (=) I (<) Magnitude Comparator < = > 3 2 1 3 2 1 I (>) I (=) I (<) Magnitude Comparator < = > < = >
rithmetic Logic Unit (LU) n n slt add sub fp cmp mlt Control multiplexer S n
rithmetic Logic Unit (LU) rithmetic circuits is built in a hierarchical fashion Input: data and operation to perform Output: result of operation and status information LU Control 4 32 LU 32 Zero Result Overflow 32 CarryOut
rithmetic Logic Unit (LU) Operation Examples LU control lines Function LU Control 4 ND 1 OR 1 DD 11 SU 32 LU 32 Zero Result Overflow 111 SLT 11 NOR 32 CarryOut
Register File Register D D 1 D 2... D n-1 En Clk ff ff ff... ff Q Q 1 Q 2... Q n-1
Register D D 1 D 2... D n-1 Register File En Clk ff Q ff Q 1 ff Q 2...... ff Q n-1 5 ws clk Register File wd rd1 rd2 32 32 32 rs1 5 rs2 5 reg we reg 1 1 reg 31
Register D D 1 D 2... D n-1 En Clk ff Q ff Q 1 ff Q 2...... Register File ff Q n-1 Register File Module Clock WE Register File we ws clk wd rd1 rd2 5 32 32 32 reg reg 1 reg 31 rs1 5 rs2 5 1 ReadSel1 ReadSel2 WriteSel WriteData rs1 rs2 ws wd we Register file 2R+1W rd1 rd2 ReadData1 ReadData2
Register File - MIPS Support 5 Read register number 1 read data 1 32 5 Read register number 2 5 Write register Register file 32 Write data read data 2 32 Write
Computer Organization v1 Recall our second view of computer organization RegWrite clk inst<25:21> inst<2:16> inst<15:11> inst<5:> we rs1 rs2 rd1 ws wd rd2 GPRs LU Control LU 3 2 1 1 17 114 Instruction Processor Data transfer ddress 2 Data Memory
MIPS Instructions There 3 types of instruction in MIPS 1. R-Type 31 26 25 21 2 16 15 11 1 6 5 2. I-Type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 25 21 2 16 15 op rs rt Immediate 31 26 25 21 2 16 15 op rs rt/funct Displacement 3. J-Type 31 26 25 op target
There 3 types of instruction in MIPS 1. R-Type 31 26 25 21 2 16 15 11 1 6 5 add rd, rs, rt MIPS Instructions op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits LU Control Instruction rs rt rd 32 5 5 5 read register 1 Read register 2 Write register Write data Register file Write read data 1 read data 2 32 32 4 LU CarryOut Zero Overflow
There 3 types of instruction in MIPS 2. I-Type MIPS Instructions 31 26 25 21 2 16 15 op rs rt Immediate 31 26 25 21 2 16 15 Instruction lw rt, index(rs) rs rt rt Write Data Immediate op Read Reg. 1 Read Reg. 2 Registers Write Reg. 16 RegWrite Read Data 1 Read Data 2 rs rt/funct Displacement Sign Extend 32 LU Control LU zero ddress Data Memory Write Data MemWrite MemRead Read Data
There 3 types of instruction in MIPS 2. I-Type MIPS Instructions 31 26 25 21 2 16 15 op rs rt Immediate 31 26 25 21 2 16 15 Instruction beq rs, rt, displ rs rt rt op Read Reg. 1 Read Reg. 2 Registers Write Reg. Write Data RegWrite Read Data 1 Read Data 2 rs rt/funct Displacement PC+4 LU LU Control zero Shift left 2 DD To ranch Control Logic ranch Target ddress Immediate 16 Sign Extend 32
There 3 types of instruction in MIPS 3. J-Type MIPS Instructions 31 26 25 op target j label PC+4[31-28] Instr[25-] Shift 26 left 2 28 32 Jump Target ddress rs rt Instruction rt
LU Operation LU operation is based on instruction type and function code Performs subtraction for branches (beq) Performs no operation for jumps Performs the operation is specified by the function field for R-type instructions LU Control unit will have the following inputs: 2-bit control field called LUOp 6-bit function field
LU Operation Instruction opcode Instruction operation LUop Funct field Desired LU action LU Control LW Load word xxxxxx add 1 SW Store word xxxxxx add 1 EQ ranch equal 1 xxxxxx subtract 11 R-type DD 1 1 add 1 R-type SU 1 11 subtract 11 R-type ND 1 11 and R-type OR 1 111 or 1 R-type SLT 1 111 slt 111
Class fter Exam Central Processing Unit (CPU) Organization