Alternative deposition solution for cost reduction of TSV integration

Alternative deposition solution for cost reduction of TSV integration J. Vitiello, F. Piallat, L. Bonnet KOBUS 611 rue Aristide Bergès, Z.A. de Pré Millet, Montbonnot-Saint-Martin, 38330 France Ph: +33 (0) 456 526 800; Fax: +33 (0) 456 526 801 Email: contact@kobus-tech.com Abstract As one of the key enabler of 3D integration, Through Silicon Via (TSV) was widely investigated but not largely adopted in the advanced packaging industry. At the present time, TSV key films, i.e. isolation, barrier and Cu seed layers, are depending on (Plasma Enhanced) Chemical Vapor Deposition ((PE)CVD) and Physical Vapor Deposition (PVD) systems in high volume manufacturing. Those deposition methods are not able to answer actual TSV needs: thick and conformal layers. They have forced engineers to compensate with other TSV fabrication steps while degrading fabrication cost. The innovative Fast Atomic Sequential Technology (F.A.S.T. ), a unique combination of optimized CVD reactor with Atomic Layer Deposition (ALD) pulsing capability, has been extensively evaluated to answer the thick and conformal layer request of TSV integration scheme while reducing integration cost. Based on commercially available molecules, actual isolation, copper barrier and Cu seed materials can be layered with advantageous conformality in TSV with aspect ratio up to 20:1. Furthermore, extended process window is at reach with the technique, thanks to additional parameters enabling fine tuning of the layer s properties to fit actual needs and future requirements. Assisted by plasma to deposit SiO 2 liner, and TiN copper barrier, or combined with reducing gas for Cu seed deposition, highly conformal films compared to PVD or PECVD can be obtained while offering deposition rate much higher than PEALD. Additionally, a unique in-situ cleaning capability was also developed to remove deposition material from the reactor walls in the Cu Seed deposition chamber, thus answering the requirements of high volume manufacturing players. Key words Fast Atomic Sequential Technology, Through Silicon Via, Pulsed CVD, PEALD, PECVD, Advanced Packaging. I. Introduction As one of the key enabler of 3D integration, Through Silicon Via (TSV) was widely investigated but not largely adopted in the advanced packaging industry [1]. The main factor limiting its adoption is the higher overall integration cost when compared to standard packaging solution. Since the first mention of TSV, new schemes have emerged to tackle this cost issue, like Fan-Out wafer level package, but they rise new problematic and are likely to face the same scaling/price trend for the next generations, while solutions can already be easily implemented for TSV. At the present time, TSV key films, i.e. isolation, barrier and Cu seed layers, are depending on (Plasma Enhanced) Chemical Vapor Deposition ((PE)CVD) and Physical Vapor Deposition (PVD) systems in high volume manufacturing. Those deposition methods are not able to answer actual TSV needs: thick and conformal layers [2, 3]. They have forced engineers to compensate with other TSV fabrication steps while degrading fabrication cost; i.e. longer etch process step to limit scalloping effect and its influence on the ability to deposit a continuous layer in the TSV; or increased CMP process time to remove the thick top Cu layer mandatory to get a thin layer down to the bottom of TSV. Increasing top layer thickness has also created integration constraints while artificially increasing aspect ratio of TSV during integration process, limiting extendibility of this solution to the next nodes which 1

require more compact designs. Alternative solutions are already studied and evaluated by major tool suppliers or chemistry suppliers. Based on electroless processes or Atomic Layer Deposition (ALD) method, they successfully overcome the conformality issue restraining actual PECVD and PVD reactors. However, to do so they introduce new chemistries [4, 5], making their adoption difficult, and they have low throughput processes [6, 7] that do not comply with the low-cost integration needed for TSV adoption in high volume manufacturing. Originally developed by Altatech, the innovative Fast Atomic Sequential Technology (F.A.S.T. ), a unique combination of optimized CVD reactor with ALD pulsing capability, has been extensively evaluated to answer the thick and conformal layer request of TSV integration scheme [8, 9]. This method allows to combine the ALD film performances at the CVD speed and it is best suited for thick and conformal deposition, as illustrated in figure 1. Figure 1: Thin film deposition comparison of ALD, CVD/PVD and F.A.S.T. in 5:1 aspect ratio TSV. II. TSV opportunities & constraints As one of the key technology for Advanced Packaging, TSV offers advantageous over other packaging solution like: - reduced distance between the 2 parts to be contacted to fulfill form factor reduction of devices - the lowest transmission delay thanks to the shortest path over other packaging methods Supported by the growing application like mobility (smart watches, smartphones ), augmented reality, or server and graphic processor unit (GPU), TSV offers performances and low losses that are required for next generation devices: 3D memory, smart camera, MEMS, micro-display and LEDs. Depending on the application, the structure of the TSV differs in size, aspect ratio, density, materials and technology. Each application has its own requirements which affect the integration scheme. The most important parameters for TSV fabrication are via diameter and aspect ratio. They will define 2 mainstream integration processes presented in figure 2: - Via middle in which the TSV is formed after the device realization but before the interconnect process; - Via last where the TSV is formed after all the device fabrication including the interconnect steps. Figure 2: Mainstream integration schemes for TSV. Combining this 2 integration approaches and the requests from application, TSV can be splitted into 2 main categories: - Narrow High Aspect Ratio TSV (NHAR) can be described as diameter below 10µm and aspect ratio greater than 10:1. Mainly used for high-end products like network, GPU or imager, those applications are driven by the need of more performances, less power consumption in reduced form factor package. - Deep Low Aspect Ratio TSV (DLAR) represents TSV of diameter greater than 20µm, with aspect ratio below 10:1. More oriented for low-end products like MEMS and sensors, they are typically fabricated in via last integration mode. In all the cases, the fabrication process consists mainly of the following steps: etching, deposition of insulator, deposition of barrier and seed layers, and electrochemical plating. Thus NHAR and DLAR TSVs present their own requirements and constraints: - NHAR: perfect etch profile globally and locally to avoid any tip effect and facilitate conformal deposition; highly conformal films to manage the low TSV diameter constraint; excellent electrical properties of seed layer to allow electroplating in high aspect ratio hole; limited Chemical Mechanical Polishing (CMP) layer removal in the case of TSV filling; and controlled stress in the final stack. - DLAR: optimized etch rate with regards to the wall profile to achieve the hole depth; low temperature deposition to be compatible with via last integration scheme; and controlled stress in the final stack. Among all the steps of fabrication, the insulator and the barrier/seed layers are the most critical for integration costs. Figure 3 present the NHAR TSV roadmap that illustrates 2

the integration cost increase due to the hole diameter reduction and aspect ratio increase. On one hand, the actual deposition methods are PVD and CVD. They are limited in terms of conformality capability when aspect ratio increases. That s why they cannot answer to next generation requirements. On the other hand, ALD is the best conformal process. But due to its low deposition rate, it is not economically viable when hole design requests layers of several 10s or 100s of nanometer thickness. deposition rate remains very slow even with the plasma assistance. At the crossroads of both, F.A.S.T. can leverage conformality and deposition rate to achieve satisfying film properties while not degrading too much the deposition rate. Moreover, electrical properties of the film are enhanced thanks to the pulsed process of this solution. Measured with MIM capacitor devices (with TiN electrodes), dielectric breakdown voltage of more than 10MV/cm can be obtained for deposition temperature above 300 C, and 9MV/cm for deposition temperature at 150 C. Figure 3: NHAR TSV roadmap. In figure 4, the same comparative is performed for DLAR TSVs. In this case, the conformality capability is plotted versus the aspect ratio. Conclusions are similar to the ones for NHAR: PECVD and PVD conformality limitation and ALD weakness in terms of deposition rate. Figure 5: SiO2 liner conformality vs aspect ratio deposited in 3 different methods, PEALD, PECVD and F.A.S.T.. Finally, by adjusting the deposition rate, F.A.S.T. offers also the ability to choose one define conformality to manage the integration needs like top to bottom thickness during via etch opening. If film properties are critical to get the best compromise for TSV performances, SiO 2 layer conformality has also a huge influence for the next deposition steps, as illustrated in figure 6. Figure 4: DLAR TSV roadmap. III. Via Formation & Integration cost First of all, based on precursor molecule already implemented in fabs, TetraEthylOrthoSilicate or TEOS, the SiO 2 layer for isolation deposited by F.A.S.T. present the best balance between film properties and deposition rate for all TSV categories: NHAR and DLAR. As illustrated with figure 5, PECVD deposition method offers the highest deposition rate but present poor conformality capability when TSV aspect ratio is increasing. At the opposite, PEALD stay close to 100% conformality whatever the aspect ratio, based on its selflimiting monolayer chemisorption process. But the Figure 6: SiO 2 liner conformality influence on top via diameter. The thickness on field can be defined as the thickness of the deposited layer on the top horizontal surface of the substrate. With the increase in aspect ratio of holes, and for a non-conformal deposition process like CVD or PVD, the 3

available diameter after oxide deposition is drastically reduced. It artificially increases the TSV aspect ratio for the following integration steps like barrier, seed layer and electroplating. With their conformal capabilities, ALD and F.A.S.T. can overcome this issue and relax integration constraints. Second of all, for barrier and seed layer, F.A.S.T. can be used to deposit: - TiN barrier from TetrakisDiEthylAmidoTitanium or TDEAT; - Cu seed layer from CupraSelect. While the barrier can be easily deposited by CVD or ALD, the Cu seed layer has been so far, a difficult step on the path of TSV formation. Only obtained using PVD, the poor step coverage capability of this method induces a lot of constraints on integration but it was the only way to get Cu seed layer. Based on F.A.S.T. solution, and combined with reducing gas, conformity close to 100% in 10:1 and up to 70% in 20:1 is obtained while offering deposition rate higher than 30 nm/min. When comparing PVD and F.A.S.T. for TSV of 10:1 aspect ratio (figure 7), the influence of this deposition step in the integration flow becomes clear. The total field thickness, to get 200nm at the bottom of the TSV for electroplating, is divided by 10 from PVD to F.A.S.T.. This allows to reduce the total Cu thickness to be removed afterwards by CMP of a factor close to 2. Figure 7: Cu seed conformality for F.A.S.T. and PVD. Additionally, CVD of Cu can only be implemented if chamber deposition solution offer in-situ cleaning capability to answer the requirements of high volume manufacturing players. It has been achieved with the F.A.S.T. reactor with a unique in-situ cleaning capability to remove deposition material from the reactor walls in the Cu Seed deposition chamber. All those elements have been computed in the TSV integration cost breakdown to evaluate the benefits of conformal deposition solution (figure 8). Based on 10:1 aspect ratio TSV (10µm diameter), the cost breakdown when using conventional CVD and PVD deposition methods evidence that there is 3 main contributors at roughly same weight: the etching step, the deposition/filling step and the CMP step. Figure 8: TSV integration cost breakdown comparing conventional CVD/PVD approach with F.A.S.T. solution. Etching step cost is driven by hole profile and hole dimensions. At a defined generation, whatever the deposition methods used to fabricate the TSV, the integration cost remains globally the same. Deposition step can be optimized by moving from PVD. With the influence of conformality, F.A.S.T. can reduce the Seed layer deposition step cost with 10 times lower total thickness required. Even if the difference is huge, it is counterbalance by the lower deposition rate that minimize the cost gain. Regarding CMP, cost is directly linked to the total thickness that needs to be removed. This is where conformal deposition methods can offer a massive cost reduction. With overburden about 3µm due to electroplating, using a conformal seed layer allows to reduce the total stack to be polished of more than 40%. With a single step representing about 35% of total TSV integration cost, a reduction of about 24% of the total can be expected. It makes the TSV fabrication more affordable, and available for the next nodes. Alternative deposition solution can also be proposed like ALD or electro-less deposition. Without any aspect ratio limitation, they are the best candidate to answer TSV roadmap on long term. But those solutions need the introduction of new materials, like Ni, Ru, WN and so on. It will impose a complete change of the integration toolset and will request a lot of development to be implemented in production. Thus, making those alternatives a long-term solution. 4

III. Conclusion Based on precursor molecules already implemented in fabs and standard reactor architecture, actual isolation, copper barrier and Cu seed materials can be layered with advantageous conformality in TSV with aspect ratio up to 20:1 with the F.A.S.T. deposition method. Furthermore, TSV integration cost was computed for an integration based on liner, barrier and seed layers deposited by F.A.S.T. technology. Compared to standard (PE)CVD/PVD solution, it can reduce integration cost of TSV of more than 20%. To conclude, PECVD and PVD deposition methods have been in production to fabricate TSV, whatever the sizes. Due to the dimensional roadmap imposed by the products, they will be no longer usable. PEALD and electro-less plating solutions are of great interest when aspect ratio increases. But due to the need of new material introduction, they will require a lot of engineering and time to be adopted by TSV makers. As an alternative for the next generation, F.A.S.T. proposes to combine thick and conformal deposition, based on standard materials. Whatever the solution that will be used for next TSV products, it will require integration cost reduction to be successfully implemented in high volume manufacturing. References [1] M. G. Farooq et al., "3D integration review", (2011) 54: 1012. [2] T. Gupta, Copper Interconnect Technology (Springer, New York, 2010). [3] S. Killge et al., 3D Stacked Chips, SIPS 2016, XXIII, pp. 9-28 [4] M. Leskelä and M. Ritala, Angew. Chem. Int. Ed. 42, 5548 (2003). [5] M. Leskelä and M. Ritala, Thin Solid Films 409, 138 (2002). [6] J.-Y. J. Y. Kim, G. G.-H. H. Choi, Y. Y. Do Kim, and H. Jeon, Jpn. J. Appl. Phys. 42, 4245 (2003). [7] F. Piallat et al., Microelectron. Eng. 107, 156 (2013). [8] F. Piallat et al., J. of Vac. Sci. & Tech. B. 34, Issue 2 (2016). [9] F. Piallat et al., Materials for Advanced Metallization conference 2017. 5