Single Pulse Unclamped Inductive Switching: ARatingSystem Application Note March 2002 AN-7514 (AN9321) Title N75 ) ubct ine lse ncla ped duce witch g: A ating s- m) utho ) eyords nter- orpo- ion, minctor, ngle lse ncla ped duce witch g: A ating s- m) Unexpected transients in electrical circuits are a fact of life. The most potentially damaging transients enter a circuit on the power source lines feeding the circuit. Power control and conversion circuits are vulnerable because of their close proximity to the incoming lines. The circuit designer must provide protection or face frequent field failures. Fairchild offers power MOS devices that are avalanche failure resistant. Most semiconductor devices are intolerant of voltage transients in excess of their breakdown rating. Avalanche capable devices are designed to be robust. The Fairchild MegaFET product line typifies the best in rugged power devices. To assist the designer in their use, Fairchild has devised a Rating System that is application specific. This application note is intended to explain and illustrate the use of the single pulse Unclamped Inductive Switching Rating curves. Failure Mechanisms Early Power MOSFET devices, not designed to be rugged, failed when the parasitic bipolar transistor indigenous to the vertical DMOS process turned on. Figure 1 shows a cross section of a unit cell from an N-channel enhancement mode device. n+ p R n+ BE n- n++ BIPOLAR TRANSISTOR SOURCE GATE DRAIN FIGURE 1. VDMOS STRUCTURE WITH PARASITIC BIPOLAR TRANSISTOR When a unit is in avalanche, the bipolar transistor is in a V CER mode, thus, it will rapidly heat. The avalanche-induced base-emitter voltage rises because of a positive resistive temperature coefficient. Simultaneously, the base emitter voltage at which the transistor will become forward biased decreases because of a negative V BE temperature coefficient. If a forward bias condition is reached, device failure initiates. Blackburn s measurements showed that this failure mode is a function of avalanche current and junction temperature and not energy related. Ruggedness improvement technology has advanced to such a level that devices fail because of a different mechanism. Devices have been manufactured in which the parasitic bipolar transistor never turns on. The failure is thermally induced. At the start of avalanche, any localized increase in temperature can initiate the formation of a current filament with a current-controlled negative-resistance characteristic. At a high current density, this can lead to the formation of a mesoplasma resulting in second breakdown and device failure. If there is heat transfer from the filament to the bulk material, the time to second breakdown is inversely proportional to the square of the current. The Fairchild MEGAFET product line typifies this type of failure mode. UIS capability testing of these devices show that the failure current versus the time in avalanche closely approximates a negative one-half slope when the locus of device destruction points is plotted on a log-log graph. Device failure is not inversely proportional to current only as it would be in the case of constant energy. Fairchild supplies rating curves at starting junction temperatures of 25 o C and 150 o C. l AS -AMP 0 ldm V GS = 20V STARTING T J = 25 o C STARTING T J = 150 o C IF R = 0 t AV = (L)(l AS )/(1.3 RATED BV DSS - V DD ) IF R > 0 t AV = (L/R) ln[(i AS *R)/(1.3 RATED BV DSS - V DD ) + 1] 1 0.01 0. 1.00.00 TIME IN AVALANCHE (t AV ) - MILLISECONDS FIGURE 2. UNCLAMPED-INDUCTIVE-SWITCHING SAFE OPERATING-AREA CURVE (SINGLE PULSE UIS SOA). SEE FIGURE 3 FOR TEST CIRCUIT.
TABLE 1. CIRCUIT CONDITIONS TIME IN AVALANCHE AVALANCHE ENERGY AVERAGE AVALANCHE POWER ROW # V DD R T AV E AS P AS(AVE) = (E AS /t rep ) 1 V DD R (L/R)ln[1/ln(1 +1/K) -K] (LI AS V DSX(SUS) /R)[1-Kln(1+1/K)] [I AS V DSX(SUS) ] [1/ln(1 +1/K) -K] - 0 R - - - - 2 V DD 0 LI AS /(V DSX(SUS) -V DD ) LI 2 AS /2(1-VDD/ V DSX(SUS) ) I AS V DSX(SUS) /2 3 0 0 LI AS /V DSX(SUS) LI 2 AS /2 I AS V DSX(SUS) /2 I AS - The peak current reached during device avalanche. t AV - The time duration of device avalanche. V DSX(SUS) - The effective (constant) device breakdown voltage during avalanche. L - Inductance R - Resistance V DD - The output circuit supply voltage. K - (V DSX(SUS) -V DD )/I AS R - The ratio of the inductor plus the resistor voltage to the resistor voltage drop. Test Circuit Equations The circuit model (Figure 3) used to describe a UIS test is a simple lumped parameter series inductor/resistor circuit in which both the power supply and device avalanche voltage are presumed to be constant. All the equations that result from the mathematical analysis are listed in Table 1 by the V DD, R conditions commonly referenced in the JEDEC test method and commercial data sheets. The equations in Row 1 are for the general case. The factor K is the ratio of the net voltage across the inductor and resistor to the resistor voltage drop. When K is large (K >30), the equations in Row 1 reduce to those in Rows 2 and 3. This can be accomplished mathematically by substituting the series expansion: ln(1 + X) = X -X 2 /2 +... Only the first term is needed for t AV, while two terms are required for E AS and P AS(AVE). Time in avalanche, t AV, is the important parameter for a rugged device. Reviewing the expressions for t AV in Table 1, the following observations can be made: 1. Series circuit resistance reduces the device avalanche stress. 2. A supply voltage approaching the device avalanche voltage increases t AV. Stress increases and the allowable avalanche current is reduced. 3. When the supply voltage is zero, t AV varies inversely with the device avalanche voltage. Integrated Technology Corporation, Tempe, AZ manufactures test equipment that works on this principle. When a device avalanches, the supply voltage is disconnected and current is commutated through an antiparallel diode. Power MOSFETs tested in this manner will receive the same heating energy independently of varying device-to-device avalanche voltages. The equations of Table 1 presume that the device avalanche voltage is constant. In an actual test it is not. Experiments have been performed using devices with similar low current room temperature BV DSS readings. V DD, L, R, I AS and t AV were carefully measured and the avalanche breakdown was calculated. All units yielded similar results. The effective avalanche voltage in all cases was 30% larger than BV DSS. V DSX(SUS) is the effective voltage referenced in the JEDEC test method. Fairchild has chosen to list V DSX(SUS) in the t AV equations on the rating curves for these devices as 1.3 times the rated low current breakdown voltage. It has been industry practice to refer only to B VDSS. V DS DUT L t P V DSX(SUS) R G + - V DD I AS V DS V DD V GS 0 t p I L 0.01Ω #2 t AV t AV FIGURE 3. UIS TEST CIRCUIT AND WAVEFORMS
Single point avalanche energy ratings at T J = 25 o C are not application specific nor are they useful for comparing similar devices offered by different manufacturers. To highlight the difficulty, a hypothetical example is in order. Let s attempt to determine the safe single pulse avalanche current for an application that uses L = 0µH and a V DD = 30V. Typical industry data sheet information is as follows: E AS = 19mJ Maximum T J = 25 o C (Starting) BV DSS = 60V L = 50µH V DD = 25V I AS = 21A Only a starting junction temperature of 25 o C can be assessed. In lieu of a rating curve, a failure mode must be assumed. Parasitic Bipolar Turn-on There is no basis from which to estimate the safe avalanche current for the intended application. Constant Energy To use the relationship E AS = (L I 2 AS /2)(1-V DD /V DSX(SUS) ) we must use V DSX(SUS) = BV DSS. The predicted safe I AS would then be equal to 13.8A. Thermal (I 2 AS t AV = Constant) Again using V DSX(SUS) = BV DSS in the relationship t AV = L I AS /(V DSX(SUS) -V DD ) we have t AV = 30µs for the data sheet condition and I 2 AS t AV = 0.0132. For the intended application then: I 3 AS = 0.0132 (V DSX(SUS) -V DD )L where L = 0µH, V DD = 30V and V DSX(SUS) = BV DSS and I AS = 15.8A. It is a simple matter to establish the safe avalanche current for an Fairchild MegaFET supplied with rating curves. Figure 2 is the rating chart for the RPF22N, a 0V BV DSS device. FOR T JS = 25 O C I 2 AS t AV = constant = C = 0.06 and V DSX(SUS) = 1.3 BV DSS and I 3 AS = C (V DSX(SUS) -V DD )/L for the application I AS = 39A FOR T JS = 150 O C I 2 AS t AV = 0.025 Thus at the maximum rated starting junction temperature, I AS = 29.2A. The safe avalanche current for any starting T J can be established from the Fairchild rating curves. Stoltenburg showed that for MegaFET devices avalanche failure was a linear function of starting T J for a fixed inductor. This is also true for a constant t AV. Figure 4 shows the relationship for the RFP22N device. It is a simple matter then to establish the I 2 AS t AV = constant for any starting T J. T JS = 0o C is a common operating temperature for a practical application. L AS AMP 50 40 30 20 30 60 120 480 t AV µs 0 0 0 200 300 400 FIGURE 4. RFP22N LAS vs TJS Entering the Fairchild curves at any convenient t AV, in this case. 0.6ms, the I AS temperature sensitivity is found to be - 3.55A/+125 o C or -28.4mA/ o C. Therefore, I AS = -(0.0284) (75) = 7.87A at t AV = 0.6ms and I 2 AS t AV = 0.0372. Using I 3 AS = 0.0372 (V DSX(SUS) -V DD )/L for the hypothetical application I AS = 33.4A for a starting T J = 0 o C. Rail Voltage (V DD ) Transients Development of a single pulse UIS rating curve for a specific load inductance and junction temperature has been illustrated. This information can be used to develop the amplitude and duration of rail voltage transients that are within the device rating. Figure 5 shows an idealized rail voltage pulse with the resultant avalanche current waveform. The equations that describe the current waveform based on a V = Ldi/dt relationship are: V SPK - V DSX(SUS) = LI AS /t SPK and V DSX(SUS) - V DD = LI AS /t AV T JPK = 378 o C Calculating the junction temperature rise caused by the voltage transient will allow the use of UIS rating curve information to determine a corresponding V SPK, t SPK rating curve for L = 0µH, V DD = 30V and a T J = 0 o C. Under the condition of no die heat loss and constant V DSX(SUS), the temperature at t SPK is: T SPK = T JS + HV DSX(SUS) I AS t SPK /2 where H is a constant defined by the rating curves. The UIS rating curves contain two important items of information. First, each curve regardless of starting T J, represents the locus of points of a single allowable peak junction temperature to be reached during avalanche. Second, for any fixed t AV, the 25 o C I AS and the 150 o C I AS values are two points on a linear Ias versus starting T J
relationship whose intercept at I AS = 0 is that peak junction temperature. Continuing the analysis, T JPK may be determined from the rating curves at a constant t AV by: T JPK = (150-25 I AS150 /I AS25 )/(1 - I AS150 /I AS25 ) for the RFP22N, T JPK = +378 o C. A value for H may be found from the time/temperature relationship during t AV. t T J = [HV DSX(SUS) ] t I(t)dt + T SPK where I(t) = I AS (1 - t/t AV ) o ο and T J = HV DSX(SUS) I AS (t - t 2 /2t AV ) + T SPK Stoltenburg has reported that device failure generally occurred between t AV /3 and t AV /2. If the delay time to second breakdown is proportional to (T J /I(t)) 2, then a maximization leads to a t AV /3 result. If the delay time is proportional to T J /I(t) then t AV /2 is the result. t AV /3 is used here to obtain I AS t AV T JPK = 5H V DSX(SUS) ----------------------- + T 18 SPK Setting T SPK = T JS = 25 o C and using T JPK = +378 o C, V DSX(SUS) = 130V and entering the 25 o C rating curve for I AS and t AV, H is found to be 1.63 x 3 o C/J. It is now possible to calculate the allowable I AS corresponding to a rail voltage spike using the relationship T SPK -T JS = H VDSX(SUS) I AS t SPK/ 2 The rating curve limits T SPK to 150 o C. For T JS = 0 o C: I AS150 t SPK = 472 X -6 For each t SPK in this equation there is a circuit defined t AV = LI AS /(V DSX(SUS) - V DD ) that should not exceed the t AV = C 150 /I 2 AS rating. This in turn defines a maximum spike induced I AS that should not be exceeded. This current is I 3 ASM = C 150 (V DSX(SUS) - V DD )/L. For this example I ASM = 29.2A for t SPK 18.2 microseconds. The bounds for the relationship V SPK = LI AS /t SPK + V DSX (SUS) have been defined and V SPK vs t SPK can be plotted. The rating curve is illustrated in Figure 6. The Application Environment With a rating curve in hand, the intended application transient environment must be assessed to determine if added protection is required. The expected rail transient voltage amplitude, duration, and frequency of occurrence can vary greatly. Figure 7 illustrates measured results on AC power service. Several organizations such as ANSI/IEEE, IEC, UL, NEMA have and are developing guidelines and test standards to describe what a specific environment is likely to be on the basis of field experience. Reference 6 contains an overview of voltage transients and provides the means for selecting an appropriate Metal-Oxide Varistor should it be required for an application. V SPK V DD = 30V, L = 0µH, T JS = 0 o C V DD l AS V SPK KILOVOLTS 1 0 T SPK T AV 0.1 1 0 T SPK, µs FIGURE 5. IDEALIZED RAIL VOLTAGE TRANSIENT FIGURE 6. RFP22N RAIL TRANSIENT RATING
References For Fairchild documents available on the internet, see web site http://www.fairchildsemi.com/ Fairchild AnswerFAX (321) 724-7800. [1] Rodney R. Stoltenburg, Boundary of Power-MOSFET, Unclamped Inductive-Switching (UIS) Avalanche- Current Capability, Proc. 1989 Applied Power Electronics Conference, pp 359-364, March 1989. [2] EIA/JEDEC Minutes Meeting No. 87, Oct. 85 thru Meeting No. 1 June 1990 of the JC-25 Committee on Transistors. [3] D. L. Blackburn, Turn-off Failure of Power MOSFETs, Proc. 1985 IEEE Power Electronics Specialists Conference, pp 429-435, June 1985. [4] Miroslav Glogolja, Ruggedness Test Claims Demand Another Careful Look, Powertechnics Magazine, pp 23-28, July 1986. [5] S. K. Ghandhi, Semiconductor Power Devices, John Wiley & Sons, New York, pp 15-29, 1977. [6] Transient Voltage Suppression Devices, Fairchild Corporation, SSD-450, 1990. FREQUENCY OF VOLTAGE TRANSIENT/YEAR,000 1,000 0 1.0 0.1 0.01 0.1 0.2 0.4 0.6 1 2 4 6 PEAK VALUE OF VOLTAGE TRANSIENT (kv) SERVICE ENTRANCE OF BANK BUILDING IN BASEL, SWITZERLAND. LANDIS AND GYR. PLANT, ZUG, OUTLET IN LAB. FARMHOUSE SUPPLIED BY OVERHEAD TRANSMISSION LINES. SERVICE ENTRANCE, 16 FAMILY HOUSE, UNDERGROUND SYSTEM (HEAD STATION). 16 FAMILY HOUSE, UPSTAIRS LIVING ROOM OUTLET. U.S. COMPOSITE CURVE. LANDIS AND GYR., ZUG, OUTLET IN FURNACE ROOM. FIGURE 7. FREQUENCY OF OCCURRENCE OF TRANSIENT OVERVOLTAGES IN 220V AND 120V SYSTEMS
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