DATASHEET CD4093BMS. Features. Pinout. Functional Diagram. Applications. Description. CMOS Quad 2-Input NAND Schmitt Triggers

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DATASHEET CD9BMS CMOS Quad -Input NAND Schmitt Triggers FN Rev. December 199 Features High Voltage Types (V Rating) Schmitt Trigger Action on Each Input With No External Components Hysteresis Voltage Typically.9V at = V and.v at = 1V Noise Immunity Greater than % No Limit on Input Rise and Fall Times Standardized, Symmetrical Output Characteristics 1% Tested for Quiescent Current at V Maximum Input Current of 1 A at 1V Over Full Package Temperature Range, 1nA at 1V and + o C V, 1V and 1V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard No. 1B, Standard Specifications for Description of B Series CMOS Devices Pinout Functional Diagram A B J = A B K = C D C D 1 7 CD9BMSMS TOP EW 1 1 1 11 1 9 H G M = G H L = E F F E Applications Wave and Pulse Shapers High Noise Environment Systems A B 1 J = A B 1 1 H Monostable Multivibrators Astable Multivibrators NAND Logic J K K = C D L = E F 1 11 G M Description C 1 L CD9BMS consists of four Schmitt trigger circuits. Each circuit functions as a two input NAND gate with Schmitt trigger action on both inputs. The gate switches at different points for positive and negative going signals. The difference between the positive voltage (VP) and the negative voltage (VN) is defined as hysteresis voltage (VH) (see Figure 1). D 7 M = G H 9 F E The CD9BMS is supplied in these 1 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack HH H1B HW FN Rev. Page 1 of 9 December 199

CD9BMS Absolute Maximum Ratings DC Supply Voltage Range, ()............... -.V to +V (Voltage Referenced to Terminals) Input Voltage Range, All Inputs.............-.V to +.V DC Input Current, Any One Input 1mA Operating Temperature Range................ to +1 o C Package Types D, F, K, H Storage Temperature Range (TSTG)........... - o C to +1 o C Lead Temperature (During Soldering)................. + o C At Distance 1/1 1/ Inch (1.9mm.79mm) from case for 1s Maximum Reliability Information Thermal Resistance................ ja jc Ceramic DIP and FRIT Package..... o C/W o C/W Flatpack Package................ 7 o C/W o C/W Maximum Package Power Dissipation (PD) at +1 o C For TA = to +1 o C (Package Type D, F, K)...... mw For TA = +1 o C to +1 o C (Package Type D, F, K)..... Derate Linearity at 1mW/ o C to mw Device Dissipation per Output Transistor............... 1mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature.............................. +17 o C TABLE 1. DC ELECTRICAL PERFORMANCE GROUP A PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS Supply Current IDD = V, N = or GND 1 + o C - A +1 o C - A = 1V, N = or GND - A Input Leakage Current IIL N = or GND = 1 + o C -1 - na +1 o C -1 - na = 1V -1 - na Input Leakage Current IIH N = or GND = 1 + o C - 1 na +1 o C - 1 na = 1V - 1 na Output Voltage VOL1 = 1V, No Load 1,, + o C, +1 o C, - mv Output Voltage VOH1 = 1V, No Load (Note ) 1,, + o C, +1 o C, 1.9 - V Output Current (Sink) IOL = V, VOUT =.V 1 + o C. - ma Output Current (Sink) IOL1 = 1V, VOUT =.V 1 + o C 1. - ma Output Current (Sink) IOL1 = 1V, VOUT = 1.V 1 + o C. - ma Output Current (Source) IOHA = V, VOUT =.V 1 + o C - -. ma Output Current (Source) IOHB = V, VOUT =.V 1 + o C - -1. ma Output Current (Source) IOH1 = 1V, VOUT = 9.V 1 + o C - -1. ma Output Current (Source) IOH1 = 1V, VOUT = 1.V 1 + o C - -. ma N Threshold Voltage VNTH = 1V, ISS = -1 A 1 + o C -. -.7 V P Threshold Voltage VPTH = V, IDD = 1 A 1 + o C.7. V Functional F =.V, N = or GND 7 + o C VOH > VOL < V = V, N = or GND 7 + o C / / = 1V, N = or GND A +1 o C = V, N = or GND B Positive Trigger VPV = V (Note ) 1,, + o C, +1 o C,.. V Threshold Voltage VP1V = 1V (Note ) 1,, + o C, +1 o C,. 1. V Positive Trigger VPV = V (Note ) 1,, + o C, +1 o C,.. V Threshold Voltage Negative Trigger VNV = V (Note ) 1,, + o C, +1 o C,.9. V Threshold Voltage VN1V = 1V (Note ) 1,, + o C, +1 o C,. 7. V Negative Trigger VNV = V (Note ) 1,, + o C, +1 o C, 1.. V Threshold Voltage Hysteresis Voltage VHV = V (Note ) 1,, + o C, +1 o C,. 1. V VH1V = 1V (Note ) 1,, + o C, +1 o C, 1.. V Hysteresis Voltage VHV = V (Note ) 1,, + o C, +1 o C,. 1. V NOTES: 1. All voltages referenced to device GND, 1% testing being implemented.. Inputs on terminals 1,,, 1. Input on Terminal 1. Input on terminals 1 and, and, and 9, or 1 and 1. For accuracy, voltage is measured differentially to. Limit is.v max. FN Rev. Page of 9 December 199

CD9BMS TABLE. AC ELECTRICAL PERFORMANCE GROUP A PARAMETER SYMBOL CONDITIONS (NOTES 1, ) SUBGROUPS TEMPERATURE MIN MAX UNITS Propagation Delay TPHL = V, N = or GND 9 + o C - ns TPLH 1, 11 +1 o C, - 1 ns Transition Time TTHL = V, N = or GND 9 + o C - ns TTLH 1, 11 +1 o C, - 7 ns NOTES: 1. CL = pf, RL = K, Input TR, TF < ns.. and +1 o C limits guaranteed, 1% testing being implemented. TABLE. ELECTRICAL PERFORMANCE PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD = V, N = or GND 1,, + o C - 1 A +1 o C - A = 1V, N = or GND 1,, + o C - A +1 o C - A = 1V, N = or GND 1,, + o C - A +1 o C - 1 A Output Voltage VOL = V, No Load 1, + o C, +1 o C, - mv Output Voltage VOL = 1V, No Load 1, + o C, +1 o C, Output Voltage VOH = V, No Load 1, + o C, +1 o C, Output Voltage VOH = 1V, No Load 1, + o C, +1 o C, - mv.9 - V 9.9 - V Output Current (Sink) IOL = V, VOUT =.V 1, +1 o C. - ma. - ma Output Current (Sink) IOL1 = 1V, VOUT =.V 1, +1 o C.9 - ma 1. - ma Output Current (Sink) IOL1 = 1V, VOUT = 1.V 1, +1 o C. - ma. - ma Output Current (Source) IOHA = V, VOUT =.V 1, +1 o C - -. ma - -. ma Output Current (Source) IOHB = V, VOUT =.V 1, +1 o C - -1.1 ma - -. ma Output Current (Source) IOH1 = 1V, VOUT = 9.V 1, +1 o C - -.9 ma - -1. ma Output Current (Source) IOH1 =1V, VOUT = 1.V 1, +1 o C - -. ma - -. ma Propagation Delay TPHL = 1V 1,, + o C - 1 ns TPLH = 1V 1,, + o C - 1 ns Transition Time TTHL = 1V 1,, + o C - 1 ns TTLH = 1V 1,, + o C - ns FN Rev. Page of 9 December 199

CD9BMS Positive Trigger Threshold Voltage Negative Trigger Threshold Voltage TABLE. ELECTRICAL PERFORMANCE (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE VP1V = 1V 1,, + o C, +1 o C, VP1V = 1V 1,, + o C, +1 o C, VP1V = 1V 1,, + o C, +1 o C, VN1V = 1V 1,, + o C, +1 o C, VN1V = 1V 1,, + o C, +1 o C, VN1V = 1V 1,, + o C, +1 o C, Hysteresis Voltage VH1V = 1V 1,, + o C, +1 o C, VH1V = 1V 1,, + o C, +1 o C, VH1V = 1V 1,, + o C, +1 o C,. 7.1 V.. V. 1.7 V.. V.. V. 9. V 1.. V 1.. V 1.. V Input Capacitance CIN Any Input 1, + o C - 7. pf NOTES: 1. All voltages referenced to device GND.. The parameters listed on Table are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics.. CL = pf, RL = K, Input TR, TF < ns.. Input on terminals 1,,, 1. Input on terminals 1 and, and, and 9, or 1 and 1 MIN MAX UNITS TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD = V, N = or GND 1, + o C - 7. A N Threshold Voltage VNTH = 1V, ISS = -1 A 1, + o C -. -. V N Threshold Voltage VTN = 1V, ISS = -1 A 1, + o C - 1 V Delta P Threshold Voltage VTP = V, IDD = 1 A 1, + o C.. V P Threshold Voltage VTP = V, IDD = 1 A 1, + o C - 1 V Delta Functional F = 1V, N = or GND = V, N = or GND 1 + o C VOH > / Propagation Delay Time TPHL TPLH NOTES: 1. All voltages referenced to device GND.. CL = pf, RL = K, Input TR, TF < ns. VOL < / = V 1,,, + o C - 1. x + o C Limit. See Table for + o C limit.. Read and Record V ns FN Rev. Page of 9 December 199

CD9BMS TABLE. BURN-IN AND LIFE TEST DELTA PARAMETERS + O C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD. A Output Current (Sink) IOL % x Pre-Test Reading Output Current (Source) IOHA % x Pre-Test Reading Logic Diagram TABLE. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD- METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) 1% 1, 7, 9 IDD, IOL, IOHA Interim Test 1 (Post Burn-In) 1% 1, 7, 9 IDD, IOL, IOHA Interim Test (Post Burn-In) 1% 1, 7, 9 IDD, IOL, IOHA PDA (Note 1) 1% 1, 7, 9, Deltas Interim Test (Post Burn-In) 1% 1, 7, 9 IDD, IOL, IOHA PDA (Note 1) 1% 1, 7, 9, Deltas Final Test 1%,, A, B, 1, 11 Group A Sample 1,,, 7, A, B, 9, 1, 11 Group B Subgroup B- Sample 1,,, 7, A, B, 9, 1, 11, Deltas Subgroups 1,,, 9, 1, 11 Subgroup B- Sample 1, 7, 9 Group D Sample 1,,, A, B, 9 Subgroups 1, NOTE: 1. % Parameteric, % Functional; Cumulative for Static 1 and. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD- TEST READ AND RECORD CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup 1, 7, 9 Table 1, 9 Table TABLE. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND 9V -.V Static Burn-In 1,, 1, 11 1,, -9, 1, 1 1 Note 1 Static Burn-In Note 1 Dynamic Burn- In Note 1 Irradiation Note NOTES:,, 1, 11 7 1,,,,, 9, 1-1 - 7 1,, 1, 11 1,,,,, 9, 1, 1,, 1, 11 7 1,,,,, 9, 1-1 OSCILLATOR khz khz 1. Each pin except and GND will have a series resistor of 1K %, = 1V.V. Each pin except and GND will have a series resistor of 7K %; Group E, Subgroup, sample size is dice/wafer, failures, = 1V.V - 1 (,, 1) (, 9, 1) * * (, 1, 11) * All inputs protected by CMOS protection network 1 OF SCHMITT TRIGGERS FN Rev. Page of 9 December 199

CD9BMS VP VN VH VO VH VH = VP - VN VO VO VN VP (a) DEFINITION OF VP, VN, VH (b) TRANSFER CHARACTERISTIC OF 1 OF GATES (c) TEST SETUP FIGURE 1. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP OUTPUT CHARACTERISTIC INPUT CHARACTERISTIC VOH LOGIC 1 OUTPUT REGION LOGIC OUTPUT REGION VP VN VOL LOGIC INPUT REGION LOGIC 1 INPUT REGION DRIVER VOH VOL LOAD FIGURE. INPUT AND OUTPUT Typical Performance Curves OUTPUT VOLTAGE (VO) (V) 1. 1. 1. 7.. AMBIENT TEMPERATURE (T A ) = + o C SUPPLY VOLTAGE () = 1V CURRENT PEAK V 1V CURRENT PEAK VO ID VO ID ALL OTHER INPUTS TO 1. 1.. DRAIN CURRENT (ID) (ma) OUTPUT VOLTAGE (VO) (V) 1 1 SUPPLY VOLTAGE () = 1V V 1V +1 o C VO ALL OTHER PACKAGE INPUTS TO... 7. 1. 1. 1. INPUT VOLTAGE () (V) 1 1 INPUT VOLTAGE () (V) FIGURE. TYPICAL CURRENT AND VOLTAGE TRANSFER FIGURE. TYPICAL VOLTAGE TRANSFER CHARACTERIS- TICS AS A FUNCTION OF TEMPERATURE FN Rev. Page of 9 December 199

CD9BMS Typical Performance Curves (Continued) OUTPUT LOW (SINK) CURRENT (IOL) (ma) 1 1 AMBIENT TEMPERATURE (T A ) = + o C GATE-TO-SOURCE VOLTAGE (VGS) = 1V 1V V OUTPUT LOW (SINK) CURRENT (IOL) (ma) 1. 1. 1. 7... AMBIENT TEMPERATURE (T A ) = + o C GATE-TO-SOURCE VOLTAGE (VGS) = 1V 1V V 1 1 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE. TYPICAL OUTPUT LOW (SINK) CURRENT 1 1 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -1-1 - AMBIENT TEMPERATURE (T A ) = + o C GATE-TO-SOURCE VOLTAGE (VGS) = -V -1V -1V - -1-1 - - - OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -1-1 - AMBIENT TEMPERATURE (T A ) = + o C GATE-TO-SOURCE VOLTAGE (VGS) = -V -1V -1V - -1-1 OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE 7. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE. MINIMUM OUTPUT HIGH (SOURCE) CURRENT PROPAGATION DELAY TIME (tphl, tplh) (ns) 7 1 AMBIENT TEMPERATURE (T A ) = + o C LOAD CAPACITANCE (CL) = pf 1 1 SUPPLY VOLTAGE () TRANSITION TIME (tthl, ttlh) (ns) AMBIENT TEMPERATURE (T A ) = + o C 1 SUPPLY VOLTAGE () = V 1 1V 1V 1 LOAD CAPACITANCE (CL) (pf) FIGURE 9. TYPICAL PROPAGATION DELAY TIME vs. SUPPLY VOLTAGE FIGURE 1. TYPICAL TRANSITION TIME vs. LOAD CAPACITANCE FN Rev. Page 7 of 9 December 199

CD9BMS Typical Performance Curves (Continued) TRIGGER THRESHOLD VOLTAGE (VP, VN) (V) 1 1 AMBIENT TEMPERATURE (T A ) = + o C INPUT ON TERMINALS 1,,, 1 OR,, 9, 1; OTHER INPUTS TIED TO VP VN 1 1 SUPPLY VOLTAGE () (V) VH HYSTERESIS ( x 1) (%) 1 1 AMBIENT TEMPERATURE (T A ) = + o C 1 1 SUPPLY VOLTAGE () (V) FIGURE 11. TYPICAL TRIGGER THRESHOLD VOLTAGE vs. FIGURE 1. TYPICAL PERCENT HYSTERESIS vs. SUPPLY VOLTAGE POWER DISSIPATION (PD) ( W) 1 AMBIENT TEMPERATURE (T A ) = + o C SUPPLY VOLTAGE () = 1V, CL = pf 1 1V, 1pF 1V, pf 1 V, pf 1 1 1 1-1 1 1 1 1 1 1 FREQUENCY (f) (khz) POWER DISSIPATION (PD) ( W) 1 1 1 1 SUPPLY VOLTAGE () = 1V, FREQUENCY (f) = 1kHz 1V, 1kHz 1V, 1kHz 1V, 1kHz 1 V, 1kHz AMBIENT TEMPERATURE (T A ) = + o C LOAD CAPACITANCE (CL) = 1pF 1-1 1 1 1 1 1 1 RISE AND FALL TIME (tr, tf) (ns) FIGURE 1. TYPICAL POWER DISSIPATION vs. FREQUENCY FIGURE 1. TYPICAL POWER DISSIPATION vs. RISE AND FALL TIMES Applications TO CONTROL SIGNAL OR 1 1/ CD9BMS FREQUENCY RANGE OF WAVE SHAPE IS FROM DC TO 1MHz TO CONTROL SIGNAL OR R 1 1/ CD7A C 1/ CD9BMS tm tm = RC n -VP k R 1M 1pF C 1 F FOR THE RANGE OF R AND C GIVEN s < tm < 1s FIGURE 1. WAVE SHAPER FIGURE 1. MONOSTABLE MULTIBRATOR FN Rev. Page of 9 December 199

CD9BMS Applications (Continued) TO CONTROL SIGNAL OR 1/ CD9BMS 1 C R ta VP -VN ta = RC n VN -VP k R 1M 1pF C 1 F FOR THE RANGE OF R AND C GIVEN s < ta <.s FIGURE 17. ASTABLE MULTIBRATOR Chip Dimensions and Pad Layout Dimension in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (1 - inch). METALLIZATION: Thickness: 11kÅ 1kÅ, AL. PASSIVATION: 1.kÅ - 1.kÅ, Silane BOND PADS:. inches X. inches MIN DIE THICKNESS:.19 inches -.1 inches Copyright Intersil Americas LLC 1999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN Rev. Page 9 of 9 December 199