Sequential Circuit esign
esign Procedure. Specification 2. Formulation Obtain a state diagram or state table 3. State Assignment Assign binary codes to the states 4. Flip-Flop Input Equation etermination Select flip-flop types and derive flip-flop equations from next state entries in the table 5. Output Equation etermination erive output equations from output entries in the table 6. Optimization Optimize the equations 7. Technology Mapping Find circuit from equations and map to flip-flops and gate technology 8. Verification Verify correctness of final design 2
Mealy Machine Typical Sequential Circuit x(t) present inputs C s(t+) next state State Register s(t) present state C2 z(t) clock 3
Typical Sequential Circuit x Q A Example Next State C Q A Q B CP C Q' y Output 4
Sequence etector sequence etector = Z = (time: 2 3 4 5 6 7 8 9 2 3 4 5) 5
esign of Sequence etector State iagram: 6
esign of Sequence etector State iagram (final): 7
esign of Sequence etector State Table: Present state S S S 2 AB Present Next State Output = = = = S S S 2 S S State Table with State Assignment: A B S A + B + Z = = = = 8
esign of Sequence etector erive Boolean Equations: A B A A B A B B A =.B B = A B A Z =.A B 9
esign of Sequence etector Compare with Typical Mealy Machine x(t) present inputs C s(t+) next state clock State Register s(t) present state C2 z(t)
esign of Sequence etector A Moore Sequence etector: x(t) present inputs C s(t+) next state State Register s(t) present state C2 z(t) clock
Sequence etector sequence etector = Z = (time: 2 3 4 5 6 7 8 9 2 3 4 5) 2
esign of a Sequence etector S : start S : got S 2 : got S 3 : got 3
esign of a Sequence etector S : start S : got S 2 : got S 3 : got 4
esign of a Sequence etector State Table Transition Table with State assignment Prese nt state Next State = = Present Output (Z) AB A B A + B + = = Z S S S 2 S 3 S S 2 S S 2 S S S 3 S 5
State iagram evelopment To develop a sequence recognizer state diagram:. Construct some sample input and output sequences to make sure that you understand the problem statement. 2. Begin in an initial state in which NONE of the initial portion of the sequence has occurred (typically reset state). 3. Add a state that recognizes that the first symbol has occurred. 4. Add states that recognize each successive symbol occurring. 5. Each time you add an arrow to the state graph, determine it can go to one of the previously defined states or whether a new state must be added 6. The final state represents the input sequence occurrence. 7. Add state transition arcs which specify what happens when a symbol not in the proper sequence has occurred. 8. Check your state graph for completeness and non-redundant arcs. 9. When your state graph is complete, test it by applying the input sequences formulated in part and make to be sure the output sequences are correct 6
State Assignment Each of the m states must be assigned a unique code Minimum number of bits required is n such that n log2 m where x is the smallest integer x There are 2 n - m unused states 7
Sequence etector Example: sequence efine states for the sequence to be recognized: assuming it starts with first symbol, continues through each symbol in the sequence to be recognized, and uses output to mean the full sequence has occurred, with output otherwise. Starting in the initial state (Arbitrarily named "A"): / A B Add a state that recognizes the first "." State "A" is the initial state, and state "B" is the state which represents the fact that the "first" one in the input subsequence has occurred. The output symbol "" means that the full recognized sequence has not yet occurred. 8
Sequence etector After one more, we have: C is the state obtained when the input sequence has two ""s. Finally, after and a, we have: A / B A / B / / C / C / Output on the arc from means the sequence has been recognized To what state should the arc from state go? Remember:? Note that is the last state but the output occurs for the input applied in. This is the case when a Mealy model is assumed. 9
etector A / B / / C / Clearly the final in the recognized sequence is a sub-sequence of. It follows a which is not a sub-sequence of. Thus it should represent the same state reached from the initial state after a first is observed. We obtain: A / B / / C / 2
etector A / B / C / / The states have the following abstract meanings: A: No proper sub-sequence of the sequence has occurred. B: The sub-sequence has occurred. C: The sub-sequence has occurred. : The sub-sequence has occurred. The / on the arc from to B means that the last has occurred and thus, the sequence is recognized. 2
etector The other arcs are added to each state for inputs not yet listed. Which arcs are missing? A / B / C / Answer: "" arc from A "" arc from B "" arc from C "" arc from. / 22
etector / / A / / B C / / / / Note that the arc from state C to state C implies that State C means two or more 's have occurred. 23
etector From the State iagram, we can fill in the State Table. There are 4 states, one input, and one output. We will choose the form with four rows, one for each current state. From State A, the and input transitions have been filled in along with the outputs. A / / Present State A B C / / B / C / / / Next State x= x= Output x= x= A B 24
etector: State Table / / A / B / C / Present Next State Output State x= x= x= x= A A B B A C C C A B / / / What would the state diagram and state table look like for the Moore model? 25
Sequence etector: Moore Model For the Moore Model, outputs are associated with states. We need to add a state "E" with output value for the final in the recognized input sequence. This new state E, though similar to B, would generate an output of and thus be different from B. The Moore model for a sequence recognizer usually has more states than the Mealy model. 26
Sequence etector: Moore Model We mark outputs on states for Moore model Arcs now show only state transitions Add a new state E to produce the output E produces the same behavior in the future as state B. But it gives a different output at the present time. A/ B/ C/ / E/ 27
Sequence etector: Moore Model The state table is shown below More state in the Moore model: Moore is More. Present State Next State x= x= A A B B A C C C A E E A C Output y A/ B/ C/ / E/ 28
State Assignment: Example Present State Next State x= x= Output x= x= A A B B A C C C A B How may assignments of codes with a minimum number of bits? 4 3 2 = 24 oes code assignment make a difference in cost? 29
State Assignment: Example 2 Present State Next State x= x= Output x= x= A A B B A B How may assignments of codes with a minimum number of bits? Two A =, B = or A =, B = oes it make a difference? Only in variable inversion, so small, if any. 3
State Assignment: Example 2 Assignment : A =, B =, C =, = The resulting coded state table: Present State Next State x = x = Output x = x = 3
State Assignment: Example 2 Assignment 2: A =, B =, C =, = The resulting coded state table: Present State Next State x = x = Output x = x = 32
A B Flip-Flop Input and Output Equations: Example 2 (version ) Assume flip-flops Interchange the bottom two rows of the state table, to obtain K-maps for A, B, and Z: A A B A A = A.B +.A.B B B B =.A.B +.A.B +.A.B 33
Flip-Flop Input and Output Equations: Example 2 (version ) A B A B Z = A.B. Gate Input Cost = 22 34
A B Flip-Flop Input and Output Equations: Example 2 (version 2) Assume flip-flops Interchange the bottom two rows of the state table, to obtain K-maps for A, B, and Z: A A B A B B A = A.B +.B B = 35
Flip-Flop Input and Output Equations: Example 2 (version 2) A B A B Z = A.B. Gate Input Cost = 9 Select this state assignment 36
Library: Flip-flops with Reset (not inverted) NAN gates with up to 4 inputs and inverters Implementation Initial Circuit: C R Y Y 2 Z Clock C R Reset 37
Technology Mapping Y C R Z Y 2 Clock Reset C R 38
Example : Vending Machine General Machine Concept: eliver package of gum after 5 cents deposited Single coin slot for dimes ( ), nickels (5 ) No change 39
Example : Vending Machine Step : Understand the problem: raw a picture Coin Sensor 5 Reset Vending Machine FSM Open Gum Release Mechanism Clk 4
Example : Vending Machine Step 2: raw state diagram: All possible sequences Inputs: N,, reset Reset S Output: open N S S2 ime: Nickel: 5 Notes: If neither N nor, goes to itself. Both N and is not possible. N S7 [open] N N S3 S4 S5 S6 [open] [open] [open] S8 [open] 4
Example : Vending Machine Step 3: State minimization: reuse states whenever possible Reset N ime: 5 Nickel: 5 N N, 5 [open] 42
Example : Vending Machine Step 4: Symbolic State table: Present State Inputs N Next State Output Open Reset N 5 N N, 5 [open] 5 5 5 5 5 5 5 5 From 5 state, you may want to go to reset state 43
Example : Vending Machine Step 5: State Encoding: Present State Q Q Inputs N Next State Output Open 44
Example : Vending Machine Step 6: Choose FF for implementation: FF easiest Q Q Q N Q Q N Q Q Q N Q N N N Q K-map for Q K-map for Q K-map for Open Q N N \Q Q Q CLK Q R \reset Q \Q OPEN = Q + + Q N = N Q + Q N + Q N + Q Q \N Q N Q Q CLK Q R \reset Q \Q OPEN = Q Q 8 Gates 45
Equivalence of Moore and Mealy Machines Moore Machine Reset N + Reset Reset/ (N + Reset)/ Mealy Machine Reset [] N Reset/ N/ N 5 [] N / 5 / N N/ [] N+ N / N+/ N / 5 5 [] Reset Reset/ Outputs are associated with State Outputs are associated with Transitions 46
Using Other FFs for esign Characteristic Table: defines the next state of the flip-flop in terms of flip-flop inputs and current state. Used in Circuit Analysis Excitation Table: defines the flip-flop input variable values as function of the current state and next state. Used in Circuit esign 47
Characteristic Table: SR FF Tables S R Q(t +) Operation Q(t) No change Reset Set? Undefined Excitation Table: Q(t) Q(t+ ) S R Operation No change / Reset Set Reset No change / Set 48
Characteristic Table: FF Tables Q(t ) + Operation Reset Set Excitation Table: Q(t) Q(t +) Operation x Reset Set 49
Characteristic Table: JK FF Tables J K Q(t+) Operation Q(t) Q(t) No change Reset Set Complement Excitation Table: Q(t) Q(t+) J K Operation No change / Reset Set / Toggle Reset / Toggle No Change / Set 5
Characteristic Table: T FF Tables T Q(t+) Q(t) Q(t) Operation No change Complement Excitation Table: Q(t) Q(t+) T Operation No change Toggle Toggle No Change 5
esign by FF Example 52
Example A(t + ) = A(A,B,) = m(2,4,5,6) B(t + ) = B(A,B,) = m(,3,5,6) Y(A,B,) = m(,5) A B A B A = AB + B B = A + B + AB A B Y = B 53
Example Logic iagram for Circuit with Flip-Flops 54
Example esign by JK FF Q(t) Q(t+) J K Operation No change/reset Set/Toggle Reset/Toggle No Change/set on t cares lead to simpler combinational circuit 55
Example: Boolean Equations JA = B JB = KA = B KB = A + A 56
Example: Logic iagram 57