9-4728; Rev 7; 9/08 Improved, Quad, General escription Maxim s redesigned analog switches now feature low on-resistance matching between switches (3Ω max) and guaranteed on-resistance flatness over the signal range (Δ4Ω max). These low on-resistance switches conduct equally well in either direction. They guarantee low charge injection, low power consumption, and an E tolerance of 2000V minimum per Method 305.7. The new design offers lower off-leakage current over temperature (less than 5nA at +85 ). The are quad, single-pole/single-throw (PT) analog switches. The G4 is normally closed (N), and the is normally open (NO). The has two N switches and two NO switches. witching times are less than 50ns max for t ON and less than 00ns max for t. These devices operate from a single +0V to +30V supply, or bipolar ±4.5V to ±20V supplies. Maxim s improved are fabricated with a 44V silicongate process. Applications ample-and-hold ircuits Test Equipment Heads-Up isplays Guidance & ontrol ystems Military Radios ommunication ystems Battery-Operated ystems PBX, PABX Audio ignal Routing New Features Plug-In Upgrade for Industry-tandard Improved R(ON) Match Between hannels (3Ω max) Guaranteed RFLAT(ON) Over ignal Range (Δ4Ω) Improved harge Injection (0p max) Improved Off-Leakage urrent Over Temperature (< 5nA at +85 ) Withstand Electrostatic ischarge (2000V min) per Method 305.7 Existing Features Low R (ON) (35Ω max) ingle-upply Operation +0V to +30V Bipolar-upply Operation ±4.5V to ±20V Low Power onsumption (35µW max) Rail-to-Rail ignal Handling TTL/MO-Logic ompatible Ordering Information PART TEMP RANGE P-PAKAGE G4J 0 to +70 6 Plastic IP G4UE 0 to +70 6 TOP G4EUE -40 to +85 6 TOP G4Y 0 to +70 6 Narrow O G4/ 0 to +70 ice Ordering Information continued at end of data sheet. ontact factory for dice specifications. Pin onfigurations/functional iagrams/truth Tables TOP VIEW 6 2 6 2 6 2 2 5 2 2 5 2 2 5 2 3 4 2 3 4 2 3 4 2 4 5 G4 3 2 4 5 3 2 4 5 3 2 4 6 3 4 6 3 4 6 3 4 7 0 3 4 7 0 3 4 7 0 3 4 8 9 3 4 8 9 3 4 8 9 3 IP/O/TOP G4 LOGI WITH 0 ON IP/O/TOP LOGI WITH 0 ON WITHE HOWN FOR LOGI 0 PUT Pin onfigurations and Functional iagrams continued at end of data sheet. IP/O/TOP LOGI WITHE, 4 WITHE 2, 3 0 ON ON Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim irect at -888-629-4642, or visit Maxim s website at www.maxim-ic.com.
ABOLUTE MAXIMUM RATG (All Voltages Referenced to.)...44v...25v...( -0.3V) to ( +0.3V) igital Inputs, V, V (Note )...( -2V) to ( +2V) or 30mA (whichever occurs first) ontinuous urrent (any terminal)...30ma Peak urrent (pulsed at ms, 0% duty cycle max)...00ma ontinuous Power issipation (T A = +70 ) 6-Pin Plastic IP (derate 0.53mW/ above +70 ).842mW 6-Pin Narrow O (derate 8.70mW/ above +70 )...696mW 6-Pin ERIP (derate 0.00mW/ above +70 )...800mW 6-Pin TOP (derate 6.7mW/ above +70 )...457mW 6-Pin QFN (derate 9.2mW/ above +70 )...538mW Operating Temperature Ranges G4...0 to +70 G4...-40 to +85 G4_AK_...-55 to +25 torage Temperature Range...-65 to +50 Lead Temperature (soldering, 0s)...+300 Note : ignals on,, or exceeding or are clamped by internal diodes. Limit forward current to maximum current rating. tresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELETRIAL HARATERITI ual upplies ( = 5V, = -5V, = 5V, V = 0V, V H = 2.4V, V L = 0.8V,, unless otherwise noted.) PARAMETER WITH Analog ignal Range rain-ource On-Resistance On-Resistance Match Between hannels (Note 4) On-Resistance Flatness (Note 4) YMBOL V ANALOG R (ON) ΔR (ON) R FLAT(ON) (Note 3) = 3.5V, = -3.5V, V = ±8.5V, I = -0mA = 5V, = -5V, V = ±0V, I = -0mA = 5V, = -5V, V = ±5V, 0V, I = -0mA ONITION, A M TYP MAX (Note 2) -5 5 7 45 7 30 45 3 5 4 6 UNIT V Ω Ω Ω ource Off-Leakage urrent (Note 7) I () = 6.5V, = -6.5V, V = ±5.5V, V = ±5.5V T A = T M to T MAX,, A, A -0.25-0.0 0.25 na -0 0 rain Off-Leakage urrent (Note 7) I () = 6.5V, = -6.5V, V = ±5.5V, V = ±5.5V T A = T M to T MAX,, A, A -0.25-0.0 0.25-0 0 na rain On-Leakage urrent (Note 7) I (ON) + I (ON) = 6.5V, = -6.5V, V = ±5.5V, V = ±5.5V T A = T M to T MAX,, A, A -0.4-0. 0.4-20 20-40 40 na 2
ELETRIAL HARATERITI ual upplies (continued) ( = 5V, = -5V, = 5V, V = 0V, V H = 2.4V, V L = 0.8V,, unless otherwise noted.) PUT Input urrent with Input Voltage High Input urrent with Input Voltage Low UPPLY Power-upply Range Positive upply urrent Negative upply urrent Logic upply urrent Ground urrent YNAMI Turn-On Time Turn-Off Time PARAMETER Break-Before-Make Time elay harge Injection (Note 3) Off-Isolation (Note 5) rosstalk (Note 6) YMBOL I H I L I+ I- I L I t ON t t Q OIRR ONITION = 2.4V, all others = 0.8V = 0.8V, all others = 2.4V = 6.5V, = -6.5V, = 6.5V, = -6.5V, = 6.5V, = -6.5V, = 6.5V, = -6.5V, V = ±0V, Figure 2 V = ±0V, Figure 2 only, R L = 300Ω, L = 35pF, Figure 3 L =.0nF, V GEN = 0V, R GEN = 0Ω, Figure 4 R L = 50Ω, L = 5pF, f = MHz, Figure 5 R L = 50Ω, L = 5pF, f = MHz, Figure 6 M TYP MAX (Note 2) -0.500 0.005 0.500-0.500 0.005 0.500 ±4.5 ±20.0-0.000 - -0.000-0.000 - -0.000 0 75 220 00 45 60 25 5 0 68 85 UNIT V ns ns ns p db db ource Off-apacitance () f = MHz, Figure 7 9 pf rain Off-apacitance () f = MHz, Figure 7 9 pf rain On-apacitance (ON) + (ON) f = MHz, Figure 8 35 pf 3
ELETRIAL HARATERITI ingle upply ( = 2V, = 0V, = 5V, V = 0V, V H = 2.4V, V L = 0.8V,, unless otherwise noted.) WITH Analog ignal Range rain-ource On-Resistance UPPLY PARAMETER Positive upply urrent Negative upply urrent Logic upply urrent YMBOL V ANALOG R (ON) I+ I- I L (Note 3) = 0.8V, V = 3.8V, I = -0mA = 3.2V, = 3.2V, = 5.25V, ONITION T A = T MAX T A = T MAX T A = T MAX M TYP MAX (Note 2) 0 2 40 80 00-0.000-0.000-0.000 UNIT V Ω Ground urrent I = 5.25V, T A = T MAX - -0.000 YNAMI Turn-On Time Turn-Off Time t ON t V = 8V, Figure 2 V = 8V, Figure 2 75 250 35 95 25 40 ns ns Break-Before-Make Time elay harge Injection (Note 3) t Q only, R L = 300Ω, L = 35pF, Figure 3 L =.0nF, V GEN = 0V, R GEN = 0V, Figure 4 5 0 Note 2: The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. Note 3: Guaranteed by design. Note 4: ΔR ON = ΔR ON max - ΔR ON min. On-resistance match between channels and flatness are guaranteed only with bipolar-supply operation. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured at the extremes of the specified analog signal range. Note 5: Off-Isolation = 20log(V / V ), V = output, V = input to off switch. ee Figure 5. Note 6: Between any two switches. ee Figure 6. Note 7: Leakage parameters I (), I (), and I (ON) are 00% tested at the maximum-rated hot temperature and guaranteed by correlation at +25. 25 ns p 4
Typical Operating haracteristics (, unless otherwise noted.) R(ON) (Ω) R(ON) (Ω) 70 60 50 40 30 20 0 ON-REITANE vs. V AN POWER-UPPLY VOLTAGE A: = 5V, = -5V B: = 0V, A = -0V : = 5V, = -5V : = 20V, = -20V B 0-20 -0 0 0 20 80 70 60 50 40 = 2V = 0V V (V) ON-REITANE vs. V (GLE UPPLY) T A = +25 T A = +85 G4-0 G4-04 R(ON) (Ω) -LEAKAGE (na) 60 50 40 30 20 0 0 00 0 0. 0.0 = 5V = -5V ON-REITANE vs. V AN TEMPERATURE T A = +25 T A = -55 T A = +85-20 -0 0 0 20 V (V) -LEAKAGE URRENT vs. TEMPERATURE = 6.5V = -6.5V V = ±5V V = ±5V G4-02 G4-05 R(ON) (Ω) ON-LEAKAGE (na) 60 40 20 00 80 60 40 20 00 0 0. 0.0 ON-REITANE vs. V AN TEMPERATURE (GLE UPPLY) = 0V = 5V = 0V = 5V = 20V 0 5 0 5 20 V (V) ON-LEAKAGE URRENT vs. TEMPERATURE = 6.5V = -6.5V V = ±5V V = ±5V G4-03 G4-06 30 0.00 0.00 20 0 5 0 5 20 V (V) 0.000-55 +25 +25 TEMPERATURE ( ) 0.000-55 +25 +25 TEMPERATURE ( ) 60 40 = 5V = -5V = 5V HARGE JETION vs. ANALOG VOLTAGE L = nf G4-07 00 0 UPPLY URRENT vs. TEMPERATURE A: I+ at = 6.5V B: I- at = -6.5V : I L at = 5V G4-08 Q (p) 20 0-20 I+, I-, IL (μa) 0. 0.0 A B -40 0.00-60 -20-5 -0-5 0 5 0 5 20 V (V) 0.000-55 +25 +25 TEMPERATURE ( ) 5
IP/O/TOP P QFN NAME, 6, 9, 8 5, 4, 7, 6 4 Input 2, 5, 0, 7 6, 3, 8, 5 4 Analog witch rain Terminal 3, 4,, 6, 2, 9, 4 4 Analog witch ource Terminal 4 2 Negative-upply Voltage Input 5 3 Ground 2 0 Logic upply Voltage Applications Information Operation with upply Voltages Other Than 5V Using supply voltages other than 5V will reduce the analog signal range. The switches operate with ±4.5V to ±20V bipolar supplies or with a +0V to +30V single supply; connect to 0V when operating with a single supply. Also, all device types can operate with unbalanced supplies such as +24V and -5V. must be connected to +5V to be TTL compatible, or to for MO-logic level inputs. The Typical Operating haracteristics graphs show typical on-resistance with ±5V, ±0V, and ±5V supplies. (witching times increase by a factor of two or more for operation at ±5V.) Overvoltage Protection Proper power-supply sequencing is recommended for all MO devices. o not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause permanent damage to the devices. Always sequence on first, followed by VL,, and logic inputs. If power-supply sequencing is not possible, add two small, external signal diodes in series with supply pins for overvoltage protection (Figure ). Adding diodes reduces the analog signal range to V below and V below, without affecting low switch resistance and low leakage characteristics. evice operation is unchanged, and the difference between and should not exceed +44V. V g FUNTION 3 Positive-upply Voltage Input onnected to ubstrate EP Exposed Paddle (QFN Only). onnect EP to. Figure. Overvoltage Protection Using External Blocking iodes Pin escription 6
Timing iagrams/test ircuits LOGI PUT WITH OUTPUT +3V 0V 0V Figure 2. witching-time 50% V OUT t ON t tr < 20ns tf < 20ns 0.9 x V OUT 0.9 x V OUT LOGI PUT WAVEFORM VERTE FOR WITHE THAT HAVE THE OPPOITE LOGI ENE. LOGI PUT WITH PUT +5V +5V 0V -5V REPEAT TET FOR AN, FOR LOA ONITION, EE Electrical haracteristics. L LUE FIXTURE AN TRAY APAITANE. R V OUT = V ( L R L + R (ON) ) R L 300Ω G4 WITH OUTPUT V OUT L 35pF LOGI PUT WITH OUTPUT (VO) WITH OUTPUT 2 (VO2) +3V 0V 0V 0V 50% t 0.9 x VOUT t 0.9 x VOUT2 V = +0V V 2 = +0V LOGI PUT 2 +5V +5V -5V 2 R L2 L LUE FIXTURE AN TRAY APAITANE. V OUT2 L2 R L = 300Ω L = 35pF R L V OUT L Figure 3. Break-Before-Make V OUT ON ΔV OUT V GEN R GEN +5V +5V L G4 V OUT ON Q = (ΔV OUT )( L ) EPEN ON WITH ONFIGURATION; PUT POLARITY ETERME BY ENE OF WITH. -5V V = +3V Figure 4. harge-injection 7
Timing iagrams/test ircuits (continued) IGNAL GENERATOR ANALYZER R L Figure 5. Off-Isolation +5V +5V -5V G4 0V or 2.4V IGNAL GENERATOR 0dBm ANALYZER 0V or 2.4V R L Figure 6. rosstalk +5V +5V -5V 2 G4 50Ω 0V or 2.4V APAITANE METER f = MHz +5V +5V G4 0V or 2.4V APAITANE METER f = MHz +5V +5V G4 0V or 2.4V -5V -5V Figure 7. hannel Off-apacitance Figure 8. hannel On-apacitance 8
Ordering Information (continued) PART TEMP RANGE P-PAKAGE G4EGE -40 to +85 6 QFN-EP* G4J -40 to +85 6 Plastic IP G4Y -40 to +85 6 Narrow O G4K -40 to +85 6 ERIP G4AK -55 to +25 6 ERIP** G4MY/PR -55 to +25 6 O*** G4MY/PR-T -55 to +25 6 O*** J 0 to +70 6 Plastic IP UE 0 to +70 6 TOP EUE -40 to +85 6 TOP Y 0 to +70 6 Narrow O / 0 to +70 ice J -40 to +85 6 Plastic IP EGE -40 to +85 6 QFN-EP* Y -40 to +85 6 Narrow O K -40 to +85 6 ERIP AK -55 to +25 6 ERIP** MY/PR -55 to +25 6 O*** MY/PR-T -55 to +25 6 O*** J 0 to +70 6 Plastic IP UE 0 to +70 6 TOP EUE -40 to +85 6 TOP Y 0 to +70 6 Narrow O / 0 to +70 ice EGE -40 to +85 6 QFN-EP* J -40 to +85 6 Plastic IP Y -40 to +85 6 Narrow O K -40 to +85 6 ERIP AK -55 to +25 6 ERIP** 4 4 2 4 3 0.080" (2.03mm) hip Topography 2 3 2 3 0.097" (2.46mm) ontact factory for dice specifications. *EP = Exposed pad. **ontact factory for availability and processing to MIL-T-883B. ***ontact factory for availability. 9
TOP VIEW 2 6 5 4 2 G4 3 4 4 5 6 7 4 4 3 QFN *EP = ONNET EP TO. 2 3 8 3 Pin onfigurations/functional iagrams (continued) 2 2 2 0 3 9 3 4 4 6 5 4 2 2 5 4 3 2 2 0 9 3 7 8 3 3 6 4 QFN 2 3 4 4 2 2 6 5 4 3 5 4 6 4 7 3 8 3 QFN 2 2 0 9 3 0
Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PAKAGE TYPE PAKAGE OE OUMENT NO. 6 QFN-EP G655-3 2-009 6 Plastic IP P6-2-0043 6 TOP U6-2 2-0066 6 ERIP J6-3 2-0045 6 Narrow O 6-2-004 6 O 6-2-004
REVIION NUMBER REVIION ATE ERIPTION Revision History PAGE HANGE 6 9/07 Addition of exposed pad information, 6, 9, 4, 5 7 9/08 Addition of rugged plastic information, 9 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 2 Maxim Integrated Products, 20 an Gabriel rive, unnyvale, A 94086 408-737-7600 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.