7- Select SSS2 LLL2 LLL2 S 2 to MUX R R Select S 2 to MUX R S S 3 to MUX 2 us R S 2 to MUX R2 R2 (a) Dedicated multiplexers (b) Sigle us Fig. 7-6 Sigle us versus Dedicated Multiplexers 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-2 TALE 7-6 Examples of Register Trasfers Usig the Sigle us i Figure 7-6(b) Select Register Trasfer S S L2 L L R R2 R R, R2 R R R, R R Impossible Table 7-6 Examples of Register Trasfers Usig the Sigle us i Figure 7-6(b) 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-3 L L L2 L2 L L Eable E2 E E LOAD R Select 2 R R E us E 3ñtoñ MUX us R R E R E R2 R2 E (a) Register with bidirectioal iput-output lies ad symbol (b) Multiplexer bus (c) Three-state bus usig registers with bidirectioal lies Fig. 7-7 Three-State us versus Multiplexer us 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-4 Address bus decoder Timig ad cotrol Data bus destiatio decoder 2 3 2 Eable Data bus source decoder 2 3 Eable A A A2 D2 D D k Address bus Data bus Read Write Memory 2 k x Fig. 7-8 Memory Uit Coected to Address ad Data uses 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-5 eable A select select Write D data A address address R 2 2 R R2 2 3 MUX 2 3 MUX 2 3 Decoder R3 Register file 2 D address Costat i A data data Destiatio select M select S MUX us A us A G select H select 4 A 2 S 2: C i S V Arithmetic/logic uit (ALU) I R Shifter I L C G H N Z Zero Detect MF select MD select us D MUX F F MUX D Fuctio uit Address Out Data Out Data I Fig. 7-9 lock Diagram of a Datapath 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-6 A Data iput A Data iput A A -bit arithmetic/ logic uit (ALU) G G G Data output G Carry iput Operatio select { C i S S C out Carry output Mode select S 2 Fig. 7- Symbol for a -it ALU 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-7 C i A X S iput logic Y -bit parallel adder G = X + Y + C i S Fig. 7- lock Diagram of a Arithmetic Circuit C out 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-8 TALE 7-7 Fuctio Table for Arithmetic Circuit Select Iput G = A+ Y + C i S S Y C i = C i = all s G = A (trasfer) G = A+ (icremet) G = A+ (add) G = A+ + G = A+ G = A+ + (subtract) all s G = A (decremet) G = A (trasfer) Table 7-7 Fuctio Table for Arithmetic Circuit 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-9 Iputs Output S S i Y i (a) Truth table Y i = Y i = i Y i = i Y i = S S i (b) Map Simplificatio: Y i = i S + i S Fig. 7-2 Iput Logic for Oe Stage of Arithmetic Circuit 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-2 C i S S C A X Y FA C G A X Y FA C 2 G A 2 2 X 2 Y 2 FA C 3 G 2 A 3 3 X 3 FA G 3 Y 3 C 4 C out Fig. 7-3 Logic Diagram of a 4-it Arithmetic Circuit 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-2 S S S S 4 to MUX A i i 2 G i S S Output G = A G = A G = A G = A ^ ^ Operatio AND OR XOR NOT 3 (b) Fuctio Table (a) Logic Diagram Fig. 7-4 Oe Stage of Logic Circuit 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-22 C i C i + A i i Oe stage of arithmetic circuit 2 to MUX G i S S S S 2 Oe stage of logic circuit Fig. 7-5 Oe Stage of ALU 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-23 TALE 7-8 Fuctio Table for ALU Operatio Select S 2 S S C i Operatio Fuctio G = A Trasfer A G = A+ Icremet A G = A+ Additio G = A+ + Add with carry iput of G = A+ A plus s complemet of G = A+ + Subtractio G = A Decremet A G = A Trasfer A X G = A AND X G = A OR X G = A XOR X G = A NOT ( s complemet) Table 7-8 Fuctio Table for ALU 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-24 3 2 Serial output L I R Serial output R I L S 2 M U X S 2 M U X S 2 M U X S 2 M U X S 2 H 3 H 2 H H Fig. 7-6 4-it asic Shifter 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-25 D 3 D 2 D D S S 3 2 S S M U X 3 2 S S M U X 3 2 S S M U X 3 2 S S M U X Y 3 Y 2 Y Y Fig. 7-7 4-it arrel Shifter 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-26 TALE 7-9 Fuctio Table for 4-it arrel Shifter Select Output S S Y 3 Y 2 Y Y Operatio D 3 D 2 D D No rotatio D 2 D D D 3 Rotate oe positio D D D 3 D 2 Rotate two positios D D 3 D 2 D Rotate three positios Table 7-9 Fuctio Table for 4-it arrel Shifter 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-27 m D data Write D address 2 m x Register file m A address address m A data data Costat i M select MUX us A us Address out Data out FS 5 A V C N Fuctio uit Z F Data i MD select MUX D Fig. 7-8 lock Diagram of Datapath Usig the Register File ad Fuctio Uit 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-28 TALE 7- G Select, H Select, ad MF Select Codes Defied i Terms of FS Codes FS MF Select G Select H Select Microoperatio s F = A F = A + F = A + F = A + + F = A + F = A + + F = A F = A F = A F = A F = A F = A F = F = sr F = sl Table 7- G Select, H Select, ad MF Select Codes Defied i Terms of FS Codes 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-29 RW Write D data DA AA 6 5 4 3 2 D address 8 x Register file A address A data address data 9 8 A Costat i M 7 us A MUX us Address out Data out A V C N Z Fuctio uit 6 5 4 FS 3 2 Data i MD MUX D us D (a) lock Diagram 6 5 4 3 2 9 8 7 6 5 4 3 2 DA AA A M FS M D R W (b) Cotrol word Fig. 7-9 Datapath with Cotrol Variables 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-3 TALE 7- Ecodig of Cotrol Word for the Datapath DA, AA, A M FS MD RW Fuctio Code Fuctio Code Fuctio Code Fuctio Code Fuctio Code R Register F = A Fuctio No write R Costat F = A + Data I Write R2 F = A + R3 F = A + + R4 F = A + R5 F = A + + R6 F = A R7 F = A F = A F = A F = A F = A F = F = sr F = sl Table 7- Ecodig of Cotrol Word for the Datapath 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-3 TALE 7-2 Examples of Microoperatios for the Datapath, Usig Symbolic Notatio Microoperatio DA AA A M FS MD RW R R2 + R3+ R R2 R3 Register F = A + + Fuctio Write R4 sl R6 R4 R6 Register F = sl Fuctio Write R7 R7+ R7 R7 Register F = A + Fuctio Write R R+ 2 R R Costat F = A + Fuctio Write Data out R3 R3 Register No Write R4 Data i R4 Data i Write R5 R5 R R Register F = A Fuctio Write Table 7-2 Examples of Microoperatios for the Datapath, Usig Symbolic Notatio 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-32 TALE 7-3 Examples of Microoperatios from Table 7-, Usig iary Cotrol Words Microoperatio DA AA A M FS MD RW R R2 R3 R4 sl R6 R7 R7+ R R+ 2 Data out R3 R4 Data i R5 Table 7-3 Examples of Microoperatios from Table 7-, Usig iary Cotrol Words 2 Pretice Hall, Ic. M. Morris Mao & Charles R. Kime
7-33 Clock DA AA A M RW Costat i FS Data i MD R R R2 R3 R4 R5 R6 R7 Status bits Address out Data out 2 3 4 5 6 7 8 4 7 4 5 2 6 7 3 3 2 5 24 2 C 8 FF 2 2 3 4 C 8 5 6 7 8 4 8 2 7 3 6 3 Fig. 7-2 Simulatio of the Microoperatio 2 Pretice Hall, Ic. Sequece i Table 7-3 M. Morris Mao & Charles R. Kime