CHPTER 9 2008 Pearson Education, Inc. 9-. log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C 7 Z = F 7 + F 6 + F 5 + F 4 + F 3 + F 2 + F + F 0 N = F 7 9-3.* = S + S = S + S S S S0 C in C 0 dder G 0 C S S S0 dder G C 2 9-4.* (Errata: Delete after problem number) = S + S = (S + S ) = (S + ) =S + S, = (S + ) S F C i G S C 0 9-5. C in t t S t F C i + G 00: G = 0: G = + 0: G = + : G = S C in Cascade four such stages, connecting the carries. 2
9-6.* Two bits : The R, NR, NR and ND are all bitwise operations. The design for one stage remains the same as any other Stages. a) R = 00, NND = 0, NR = 0 NR = ut = S + S + S + S + S b) The above is a simplest expression. 9-7. + Logic table S2 S S0 peration 0 0 0 + 0 0 + + 0 0 0 + 0 0 Sr 0 v 0 S l ^ i S C i Ri (to stage to right) i i C L Carry to the left C R Carry to the right C Ri (from stage to left) C Rn 0 C Li (from stage to right) C L0 F C out 0 Mux 2 3 0 Mux S S 2 0 Mux S 2 F i C Li (to stage to left) 9-8.* 9-9. (a) 00 (b) 0 (c) 00 (d) 000 D M FS MD RW 5 4 3 2 0 9 8 7 6 5 4 3 2 0 (a) 0 0 0 0 0 0 0 0 0 0 (b) 0 - - - 0 0 0 (c) 0 - - - - - - - - - - - (d) 0 0 - - - 0 0 0 0 0 (e) 0 0 0 - - - 0 0 0 (f) 0 0 0 0 - - - - 0 0 0 0 (g) 0 0 0 0 0 0 0 0 0 (h) 0 0 0 0 0 0 0 0 0 9-0.* (a) R5 R4 R5 R5 = 0000 000 (d) R5 R0 R5 = 0000 0000 (b) R6 R2 + R4 + R6 = 0 (e) R4 srconstant R4 = 0000 00 (c) R5 R0 R5 = 0000 0000 (f) R3 Data in R3 = 000 0 9-. R3 R3 + R, R3 = 000 R4 R4 R, R4 = 0000 R5 R5 R, R5 = 0000 R R, R = 0 R... R7 = i, D, g, t, l, a, i R R +, R = 00000 R6 R6 + R +, R6 = 00000 R7 R7 + R +, R7 = 0000 R R7, R = 0000 Unscrambled is Digital 22
9-2. 9-3.* 9-4. 9-5. 9-6. 9-7. a) 64 x 64 = 4096 b) 32 c) 0 to 4294967295 d) 247483648 to +247483647 errata : bit 3 as the sign bit makes sense a) 8 bits b) 49 bits 4 + 6 + 28 = 48 Instruction Register Transfer D M FS MD RW MW PL J R[ 0] R[ 7] R[ 3] 000 0 0 00 0 0 0 x R[ ] MR4 [ [ ]] 00 00 xxx x xxxx 0 0 x R[ 2] R[ 5] + 2 00 0 xxx 000 0 0 0 x R[ 3] sl R[ 6] 0 xxx 0 0 0 0 0 0 x if R[ 4] = 0 then PC PC + se PC xxx 00 xxx x 0000 x 0 0 0 Instruction Register Transfer peration Code DR S S or perand R[ 0] = sr R[ 7] 000 0 000 000 R[ ] MR6 [ [ ]] 00 0000 00 0 000 R[ 2] R[ 5] + 4 00 000 00 0 000 R[ 3] R[ 4] R[ 3] 000 00 0 00 0 R[ 4] R[ 2] R[ ] 000 00 00 00 00 M: 5 - Correct for table specification MD: 3 - Correct for table specification RW:4 - Correct for table specification MW: 5 4 - Correct for table specification PL: 5 4 - Correct for table specification J: 3 - Correct for table specification C: 9 - Correct for table specification FS: The logic gives 0000 for FS for PL = which selects the value on the input to the Function Unit to be evaluated for branches and blocks the value on bit 9 which is otherwise used as C for branches. For PL = 0, the normal bits for FS are passed as required from the op code. Correct. Instruction Code Registers/Memory changed DD R0, R, R2 000 00 000 00 00 SU R3, R4, R5 000 00 0 00 0 R0 = 3 SU R6, R7, R0 000 00 0 000 R3 = - DD R0, R0, R3 000 00 000 000 0 R6 = 4 SU R0, R0, R6 000 00 000 000 0 R0 = 2 ST R7, R0 00 0000 000 000 R0 = -2 LD R7, R6 0 0000 0 000 M[7] = -2 DI R0, R6, 2 00 000 000 0 000 R7 = M[4] DI R3, R6, 3 00 000 0 0 0 R0 = 6 R3 = 7 23
9-8. R[ 4] R[ 4] R[ 4] V and C are produced by the arithmetic circuit. For the R FS code, S = 0, S0 =. and Cin = 0, giving arithmetic operation dd. For arbitrary contents in R[4], the values of C and V are a function of the sign and value of the contents of R4 and are unpredicable. 9-9. Part pcode VCNZ IL PS D M FS MD RW MM MW (a) E0 00000 xxxx E 0 0 0xxx 0xxx 0xxx 0 00 0 0 0 (b) E0 0000 xxxx INF 0 0 000 xxxx 000 0 0 0 0 0 E0 00000 xxx0 INF 0 0 xxxx 0xxx xxxx x 0000 0 0 0 0 (c) E0 00000 xxx INF 0 0 xxxx 0xxx xxxx x 0000 0 0 0 0 (d) E0 0000000 xxxx INF 0 0 0xxx 0xxx xxxx x 0000 0 0 0 9-20. Instruction R8 R9 Z E0 R8 RS [ ] 0 E E R9 zfp 0000000 x 0 E2 E2 R8 srr8 0000000 5 0 E3 E3 R9 R9 00000000 5 0 E2 E2 R8 srr8 00000000 4 0 E3 E3 R9 R9 000000000 4 0 E2 E2 R8 srr8 000000000 3 0 E3 E3 R9 R9 0000000000 3 0 E2 E2 R8 srr8 0000000000 2 0 E3 E3 R9 R9 0000000000 2 0 E2 E2 R8 srr8 0000000000 0 E3 E3 R9 R9 0000000000 E4 E4 RDR [ ] R8 0000000000 0 0 INF INF - 0000000000 0 - - 9-2. + Removal of the two decisions on zero operations does not affect the number of states in the state machine diagram. The reason for this is that the same states are required because the datapath of the computer only supports one register transfer per clock cycle. The transfers required by the instruction execution force the state structure. s a consequence, there can be no reduction of the number of clock cycles required to execute the instructions. The new state machine diagram is actually a worst case in terms of execution time for the instruction execution. The two decisions can only improve the execution times. So the analysis suggested is unnecessary. 24
9-22. Partial state machine diagram: E0 E E2 INF Problem Solutions Chapter 9 R8 RS [ ] R9 MRS [ [ ]] RDR [ ] R8 + R9, pcode VCNZ IL PS D M FS MD RW MM MW E0 00000 xxxx E 0 00 000 xxxx 0xxx 0 00 0 0 0 E 00000 xxxx E2 0 00 00 0xxx xxxx x xxxx 0 0 E2 00000 xxxx INF 0 0 0xxx 000 00 0 000 0 0 0 9-23. Partial state machine diagram: R8 R8 pcode = 0000 R8 R8 R8 pcode = 0000 E0 E pcode = 0000 RDR [ ] RS [ ] + RS [ ] Z ( pcode = 0000) V ( pcode = 0000) V ( pcode = 0000) E2 Z ( pcode = 0000) E3 pcode = 0000 INF pcode = 0000 PC PC + se D R8 R8 +, Part pcode VCNZ V RV IL PS D M FS MD RW MM MW E0 0000 xxxx E 0 00 0xxx 000 000 0 00 0 x 0 E 0000 xxx E2 0 00 0xxx 0xxx 0xxx 0 000 0 x 0 E 0000 0xxx INF 0 0 0xxx 0xxx 0xxx 0 000 0 x E2 0000 xxxx INF 0 0 000 000 xxxx 0 000 0 x 0 E0 0000 xxx0 E3 0 00 000 000 xxxx x 0000 0 x 0 E0 0000 xxx INF 0 0 000 000 xxxx x 0000 0 x 0 E3 0000 xxxx INF 0 0 xxxx xxxx xxxx x xxxx 0 0 x 0 25
9-24. Partial state machine diagram: E0 R8 R8 R8 E R9 RS [ ] RS [ ] Z ( ) E3 INF Z N ( ) E2 Z N ( ) R8 R8 + RDR [ ] R8 +, pcode VCNZ IL PS D M FS MD RW MM MW E0 00000 xxxx E 0 00 000 000 000 0 00 0 0 0 E 00000 xxx E3 0 00 00 0xxx 0xxx 0 00 0 0 0 E 00000 xx00 E2 0 00 00 0xxx 0xxx 0 00 0 0 0 E 00000 xx0 INF 0 0 00 0xxx 0xxx 0 00 0 0 0 E2 00000 xxxx E3 00 000 000 xxxx x 000 0 0 0 E3 00000 xxxx INF 0 0 0xxx 000 xxxx x 000 0 0 0 9-25.+ (Errata: dd a + and the following hint. Hint: In order to address all eight registers, it is necessary to provide eight values for S in the Instruction Register. Since the instruction register can only be loaded from memory, these instructions must be placed in memory temporarily during the instruction execution and loaded into the IR as data without using the normal instruction fetch. ) The operation code used for SMR and these instructions is 0 which is easy to generate by complementing all 0 s. The word to be stored in memory is built in a register by complementing all 0 s and NDing the result with the value of S from the original instruction. The register value generated is incremented, stored in memory and loaded into the IR after the execution of each transfer from a register to a memory location. Register Transfer pcode VCNZ IL PS D M FS MD RW MM MW R8 R[S] E0 0 xxxx E 0 00 000 0xxx xxxx 0 0000 0 0 R9 R9 R9 (R9 0) E 0 xxxx E2 0 0 00 00 00 0 00 0 0 0 R9 R9 E2 0 xxxx E3 0 0 00 00 xxxx x 0 0 0 0 R0 sr R9 E3 0 xxxx E4 0 0 00 00 xxxx x 0 0 0 0 0 R9 R0 zf S E4 0 xxxx E5 0 0 00 00 xxxx 000 0 0 0 R zf S E5 0 xxxx E6 0 0 0 xxxx xxxx 00 0 0 0 M[R0] R9 E6 0 xxxx E7 0 0 xxxx 00 00 0 xxxx x 0 0 IR M[R0] E7 0 xxxx E8 0 xxxx 00 xxxx x xxxx x 0 0 0 M[R8] R[S] E8 0 xxxx E9 0 0 xxxx 000 0xxx 0 xxxx 0 0 R8 R8 + E9 0 xxxx E0 0 0 000 000 xxxx x 000 0 0 0 R9 R9 + E0 0 xxxx E 0 0 00 00 xxxx x 000 0 0 0 R zf S, Z : E5 E 0 xxx0 E5 0 0 xxxx 0 xxxx 00 x 0 0 0 R zf S, Z : INF, inc PC E 0 xxx INF 0 0 xxxx 0 xxxx 00 x 0 0 0 26
9-26. (Errata: Solution of this problem with the architecture available is too difficult and while it can be solved, any solution is highly impractical. It will be removed in the 2nd and subsequent printings.) 27