- CPSC 352- Computer Organization
-2 Chapter Contents. Introduction.2 Combinational Logic.3 Truth Tables.4 Logic Gates.5 Properties of oolean lgebra.6 The Sum-of-Products Form, and Logic Diagrams.7 The Product-of-Sums Form.8 Positive vs. Negative Logic.9 The Data Sheet. Digital Components. Sequential Logic.2 Design of Finite State Machines.3 Mealy vs. Moore Machines.4 Registers.5 Counters
-3 Some Definitions Combinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs. e.g. an adder. Sequential logic: a circuit in which decisions are made based on combinations of the current inputs as well as the past history of inputs. e.g. a memory unit. Finite state machine: a circuit which has an internal state, and whose outputs are functions of both current inputs and its internal state. e.g. a vending machine controller.
-4 The Combinational Logic Unit Translates a set of inputs into a set of outputs according to one or more mapping functions. Inputs and outputs for a CLU normally have two distinct (binary) values: high and low, and, and, or 5 V and V for example. The outputs of a CLU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change. set of inputs i i n are presented to the CLU, which produces a set of outputs according to mapping functions f f m. i i i n... Combinational logic unit... f (i, i ) f (i, i 3, i 4 ) f m (i 9, i n )
-5 Truth Table Developed in 854 by George oole. Further developed by Claude Shannon (ell Labs). Outputs are computed for all possible input combinations (how many input combinations are there?) Consider a room with two light switches. How must they work? GND Inputs Output Hot Light Z Z Switch Switch
-6 lternate ssignment of Outputs to Switch Settings We can make the assignment of output values to input combinations any way that we want to achieve the desired input-output behavior. Inputs Output Z
-7 Truth Tables Showing ll Possible Functions of Two inary Variables Inputs Outputs The more frequently used functions have names: ND, XOR, OR, NOR, XOR, and NND. (lways use upper case spelling.) False ND XOR OR Inputs Outputs NOR XNOR + + NND True
-8 Logic Gates and Their Symbols Logic symbols shown for ND, OR, buffer, and NOT oolean functions. F F Note the use of the inversion bubble. F = F = + (e careful about the nose of the gate when drawing ND vs. OR.) ND F OR F F = F = uffer NOT (Inverter)
-9 Logic Gates and their Symbols (cont ) F NND F NOR F = F = + F Exclusive-OR (XOR) F = F Exclusive-NOR (XNOR) F =.
- Variations of Logic Gate Symbols C F = C F = + (a) (b) + + (c) (a) 3 inputs (b) Negated input (c) Complementary outputs
VO Output Voltage V - Transistor Operation of Inverter OUTPUT VOLTGE vs. INPUT VOLTGE 4. V CC 3.5 3. V CC = 5 V R L = 4 Ω V CC = +5 V GND = V ase V CC Collector Emitter V in R L V out 2.5 2..5..5.2.4.6.8.2.4.6.8 2 (a) (b) (c) V I Input Voltage V (d) (a) Inverter showing power terminals; (b) transistor symbol; (c) transistor configured as an inverter; (d) inverter transfer function.
-2 ssignments of and to Voltages +5 V +5 V Logical Logical 2.4 V.4 V V Forbidden Range Logical 2. V.8 V V Forbidden Range Logical (a) (b)
-3 Transistor Operation of Logic Gates V CC (a) NND; (b) NOR V out V CC V V out + V 2 V V 2 (a) (b)
-4 Tri-State uffers Outputs can be,, or electrically disconnected. C F ø ø C F ø ø C F = C or F = ø C F = C or F =ø Tri-state buffer Tri-state buffer, inverted control
-5 Properties of oolean lgebra Principle of duality: The dual of a oolean function is obtained by replacing ND with OR and OR with ND, s with s, and s with s. Theorems Postulates Relationship Dual Property = ( + C) = + C = = = = + = + + C = ( + ) ( + C) + = + = + = + = Commutative Distributive Identity Complement Zero and one theorems Idempotence ( C) = ( ) C + ( + C) = ( + ) + C ssociative = Involution = + + = DeMorgan s Theorem +C+C = +C ( + ) = (+)(+C)(+C) = (+)(+C) + = Consensus Theorem bsorption Theorem
-6 DeMorgan s Theorem = = + + DeMorgan s theorem: + = + = F = + F =
-7 ll-nnd Implementation of OR NND alone implements all other oolean logic gates. + +
-8 Sum-of-Products Form: The Majority Function The SOP form for the 3-input majority function is: M = C + C + C + C = m3 + m5 + m6 + m7 = Σ (3, 5, 6, 7). Each of the 2 n terms are called minterms, ranging from to 2 n -. Note relationship between minterm number and boolean value. Minterm Index 2 3 4 5 6 7 C F -side -side balance tips to the left or right depending on whether there are more s or s.
-9 ND-OR Implementation of Majority C Gate count is 8, gate input count is 9. C C F C C
-2 Notation Used at Circuit Intersections Connection No connection Connection No connection
-2 OR-ND Implementation of Majority C + + C + + C F + + C + + C
-22 Gate Logic: Positive vs. Negative Logic Normal Convention: Postive Logic/ctive High Low Voltage = ; High Voltage = Positive/Negative Logic ssignments Positive logic: logic is represented by high voltage; logic is represented by low voltage. Negative logic: logic is represented by high voltage; logic is represented by low voltage. lternative Convention sometimes used: Negative Logic/ctive Low F Voltage Truth T able Positive Logic Negative Logic low low high high low high low high F low low low high F F ehavior in terms of Electrical Levels Two lternative Interpretations Positive Logic ND Negative Logic OR Dual Operations
-23 Positive/Negative Logic ssignments (Cont ) Voltage Levels Positive Logic Levels Negative Logic Levels low low high high low high low high F low low low high F F Physical ND gate F F = F = + Voltage Levels Positive Logic Levels Negative Logic Levels low low high high low high low high F high high high low F F Physical NND gate F F = F = +
-24 ubble Matching Positive logic Positive logic x Positive Negative logic x x Logic Negative logic x Negative Logic (a) (b) Negative logic Negative logic x x ubble mismatch (c) Negative Logic Negative logic Negative logic x x ubble match ubble match (d) Negative Logic
-25 SN74 UDRUPLE 2-INPUT POSITIVE-NND GTES description Example Data Sheet These devices contain four independent 2-input NND gates. function table (each gate) INPUTS H L X H X L OUTPUT Y L H H package (top view) Y 2 2 2Y GND 2 3 4 5 6 7 4 3 2 9 8 V CC 4 4 4Y 3 3 3Y 4 kω schematic (each gate).6 kω 3 Ω Y V CC Simplified data sheet for 74 NND gate, adapted from Texas Instruments TTL Databook [Texas Instruments, 988] absolute maximum ratings Supply voltage, VCC 7 V Input voltage: 5.5 V Operating free-air temperature range: C to 7 C Storage temperature range 65 C to 5 C logic diagram (positive logic) 2 2 3 3 4 4 Y = Y 2Y 3Y 4Y recommended operating conditions V CC V IH V IL I OH I OL T Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature kω MIN NOM MX GND UNIT 4.75 5 5.25 V 2 V.8 V.4 m 6 m 7 C electrical characteristics over recommended operating free-air temperature range MIN TYP MX UNIT V OH V OL I IH I IL I CCH I CCL V CC = MIN, V IL =.8 V, I OH =.4 m V CC = MIN, V IH = 2 V, I OL = 6 m V CC = MX, V I = 2.4 V V CC = MX, V I =.4 V V CC = MX, V I = V V CC = MX, V I = 4.5 V 2.4 3.4.2 4 2.4 V V 4 µ.6 m 8 m 22 m switching characteristics, V CC = 5 V, T = 25 C PRMETER FROM (input) TO (output) TEST CONDITIONS MIN TYP MX UNIT t PLH R 22 ns or Y L = 4 Ω t C L = 5 pf PHL 7 5 ns
-26 Digital Components High level digital circuit designs are normally created using collections of logic gates referred to as components, rather than using individual logic gates. Levels of integration (numbers of gates) in an integrated circuit (IC) can roughly be considered as: Small scale integration (SSI): - gates. Medium scale integration (MSI): to gates. Large scale integration (LSI): -, logic gates. Very large scale integration (VLSI):,-upward logic gates. These levels are approximate, but the distinctions are useful in comparing the relative complexity of circuits.
Data Inputs -27 Multiplexer D D D 2 D 3 F F D D D 2 D 3 Control Inputs F = D + D + D 2 + D 3
-28 ND-OR Implementation of MUX D D D 2 F D 3
-29 MUX Implementation of Majority Principle: Use the 3 MUX control inputs to select (one at a time) the 8 data inputs. C M F C
-3 4-to- MUX Implements 3-Var Function Principle: Use the and inputs to select a pair of minterms. The value applied to the MUX data input is selected from {,, C, C} to achieve the desired behavior of the minterm pair. F C C C F C C
-3 Demultiplexer D F = D F = D F F F 2 F 3 F 2 = D F 3 = D D F F F 2 F 3
-32 Gate-Level Implementation of DEMUX F D F F 2 F 3
-33 Decoder Enable = Enable = D D Enable D 2 D 3 D D D 2 D 3 D D D 2 D 3 D = D = D 2 = D3 =
-34 Gate-Level Implementation of Decoder D D D 2 D 3 Enable
-35 Decoder Implementation of Majority Function Note that the enable input is not always present. We use it when discussing decoders for memory. C M
-36 Priority Encoder n encoder translates a set of inputs into a binary encoding. Can be thought of as the converse of a decoder. priority encoder imposes an order on the inputs. i has a higher priority than i+ F F 2 3 F F 2 3 F = 3 + 2 F = 2 3 +
-37 ND-OR Implementation of Priority Encoder F 2 3 F
-38 C Programmable Logic rray OR matrix PL is a customizable ND matrix followed by a customizable OR matrix. lack box view of PL: C PL F F Fuses ND matrix F F
-39 C Simplified Representation of PL Implementation of Majority Function C C C C F (Majority) F (Unused)
-4 Example: Ripple-Carry ddition Carry In Operand Operand + + + + + + + + Carry Out Sum Carry Operand Example: Operand Sum +
-4 Full dder i i C i S i C i+ i i C i+ Full adder S i C i
-42 Four-it Ripple-Carry dder Four full adders connected in a ripple-carry chain form a four-bit ripple-carry adder. b 3 a 3 b 2 a 2 b a b a c 3 c 2 c c Full adder Full adder Full adder Full adder c 4 s 3 s 2 s s
-43 C in PL Realization of Full dder Sum C out
-44 Sequential Logic The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs. There is a need for circuits with memory, which behave differently depending upon their previous state. n example is a vending machine, which must remember how many and what kinds of coins have been inserted. The machine should behave according to not only the current coin inserted, but also upon how many and what kinds of coins have been inserted previously. These are referred to as finite state machines, because they can have at most a finite number of states.
-45 Classical Model of a Finite State n FSM is composed of a combinational logic unit and delay elements (called flip-flops) in a feedback path, which maintains state information. Inputs Machine i o i k...... Combinational logic unit D s... n D n... s Synchronization n signal Delay elements (one per state bit)... f o f m Outputs State bits
-46 NOR Gate with Lumped Delay τ + + Timing ehavior The delay between input and output (which is lumped at the output for the purpose of analysis) is at the basis of the functioning of an important memory element, the flip-flop. τ
-47 S-R Flip-Flop The S-R flip-flop is an active high (positive logic) device. t S t R t i+ S S R (disallowed) (disallowed) R τ 2 τ τ 2 τ Timing ehavior
-48 NND Implementation of S-R Flip-Flop S S S R R R R S
-49 Hazard C C S S R τ Glitch caused by a hazard R τ Timing ehavior It is desirable to be able to turn off the flip-flop so it does not respond to such hazards. 2 τ
mplitude -5 Clock Waveform: The Clock Paces the System Time Cycle time = 25ns In a positive logic system, the action happens when the clock is high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs settle at the correct value when the clock next goes high.
-5 Scientific Prefixes For computer memory, K = 2 = 24. For everything else, like clock speeds, K =, and likewise for M, G, etc. Prefix bbrev. uantity milli m micro µ nano n pico p 3 6 9 2 Prefix bbrev. uantity Kilo K Mega M Giga G Tera T 3 6 9 2 femto f 5 Peta P 5 atto a 8 Exa E 8
-52 Clocked S-R Flip-Flop S S R CLK CLK R τ 2 τ Timing ehavior The clock signal, CLK, enables the S and R inputs to the flip-flop.
-53 Clocked D Flip-Flop The clocked D flip-flop, sometimes called a latch, has a potential problem: If D changes while the clock is high, the output will also change. The Master-Slave flip-flop (next slide) addresses this problem. D CLK Circuit D CLK Symbol D C τ 2 τ 2 τ Timing ehavior τ
-54 Master-Slave Flip-Flop The rising edge of the clock loads new data into the master, while the slave continues to hold previous data. The falling edge of the clock loads the new master data into the slave. Master Slave D D D M D S CLK CLK C Circuit C S M S Symbol D S τ 3 τ 2 τ 2 τ 2 τ Timing ehavior τ
-55 Clocked J-K Flip-Flop The J-K flip-flop eliminates the disallowed S=R= problem of the S-R flip-flop, because enables J while disables K, and vice-versa. However, there is still a problem. If J goes momentarily to and then back to while the flip-flop is active and in the reset state, the flip-flop will catch the. This is referred to as s catching. The J-K Master-Slave flip-flop (next slide) addresses this problem. J J CLK K K Circuit Symbol
-56 Master-Slave J-K Flip-Flop J J CLK K K Circuit Symbol
-57 Clocked T Flip-Flop The presence of a constant at J and K means that the flip-flop will change its state from to or to each time it is clocked by the T (Toggle) input. J T T K Circuit Symbol
-58 Negative Edge-Triggered D Flip-Flop When the clock is high, the two input latches output, so the Main latch remains in its previous state, regardless of changes in D. Stores D R When the clock goes high-to-low, values in the two input latches will affect the state of the Main latch. CLK S Main latch While the clock is low, D cannot affect the Main latch. D Stores D
-59 Example: Modulo-4 Counter Counter has a clock input (CLK) and a RESET input. Counter has two output lines, which take on values of,,, and on subsequent clock cycles. Time (t) RESET q 4 3 2 4 3 2 Time (t) 3-bit q Synchronous s Counter D CLK s D s s
-6 State Transition Diagram for RESET Output state / q q / / Output state Mod-4 Counter / / / / C / D Output state Output state
-6 State Table for Mod-4 Counter Present state Input RESET / / C/ / C D/ / D / / Next state Output
-62 State ssignment for Mod-4 Counter Present state (S t ) Input RESET : / / : / / C: / / D: / /
-63 Truth Table for Mod-4 Counter RESET r(t) s (t) s (t) s s (t+) q q (t+) s (t+) = r(t)s (t)s (t) + r(t)s (t)s (t) s (t+) = r(t)s (t)s (t) + r(t)s (t)s (t) q (t+) = r(t)s (t)s (t) + r(t)s (t)s (t) q (t+) = r(t)s (t)s (t) + r(t)s (t)s (t)
-64 Logic Design for Mod-4 Counter RESET CLK D s q D s q
-65 Example: Sequence Detector Example: Design a machine that outputs a when exactly two of the last three inputs are. e.g. input sequence of of. ssume input is a -bit serial line. Use D flip-flops and 8-to- Multiplexers. produces an output sequence Start by constructing a state transition diagram (next slide).
-66 Sequence Detector State Transition Diagram / Design a machine that outputs a when exactly two of the last three inputs are. / / / D E / / / / / C / F / / / G /
-67 Sequence Detector State Table Present state Input X / C/ D/ E/ C F/ G/ D D/ E/ E F/ G/ F D/ E/ G F/ G/
-68 Sequence Detector State ssignment X : / / Present state Input : C: D: E: / / / / / / / / F: / / S 2 S S S 2 S S Z S 2 S S Z G: / / (a) s x s d d s 2 (b) d d d d d d z s s s 2 Input and state at time t Next state and output at time t+
-69 Sequence Detector Logic Diagram x x x D S 2 x x x x x x x D S x x x x x x x D S x x x Z CLK
-7 Example: Vending Machine Controller Example: Design a finite state machine for a vending machine controller that accepts nickels (5 cents each), dimes ( cents each), and quarters (25 cents each). When the value of the money inserted equals or exceeds twenty cents, the machine vends the item and returns change if any, and waits for next transaction. Implement with PL and D flip-flops.
-7 Vending Machine State Transition / dime is inserted Diagram / = Dispense/Do not dispense merchandise N/ D/ / = Return/Do not return a nickel in change / = Return/Do not return a dime in change N/ D / D/ 5 5 / / D/ D/ N/ C N/ N = Nickel D = Dime = uarter
-72 Vending Machine State Table and State ssignment P.S. Input N D / C/ C/ D/ C D/ / D / / (a) / / / / Input P.S. s s N D x x x x x x s s / z 2 z z : / / : / / C: / / D: / / (b) / / / /
-73 PL Vending Machine Controller s s x x s s z 2 z z 2 4 5 6 8 9 2 3 4 (c) 5 5 PL z z x x (a) s D s D CLK d d d d d d d d d d d d d d d d 2 3 4 5 6 7 8 9 2 3 4 5 s s x x Present state Coin d d d d s s z 2 z z Next state Dispense Return nickel ase equivalent (b) Return dime z 2
-74 Moore Counter Mealy Model: Outputs are functions of Inputs and Present State. Previous FSM designs were Mealy Machines, in which next state was computed from present state and inputs. Moore Model: Outputs are functions of Present State only. z z x 4-to- MUX D S z 4-to- MUX D S z CLK
-75 Four-it Register Makes use of tri-state buffers so that multiple registers can gang their outputs to common output lines. D 3 D 2 D D Write (WR) CLK D D D D Enable (EN) WR D 3 D 2 D D 3 2 EN 3 2
-76 Left-Right Shift c Register with c Shift left output Shift right input D 3 D 2 D D Shift right input Parallel Read and c Write c CLK Enable (EN) D D D D Shift right output 3 2 Control Function c c No change Shift left Shift right Parallel load Shift right input Shift left output c c D 3 D 2 D D 3 2 Shift right output Shift right input
-77 Modulo-8 Counter Note the use of the T flip-flops, implemented as J-K s. They are used to toggle the input of the next flip-flop when its output is. CLK Enable (EN) J K J K J K RESET 2 CLK ENLE RESET MOD(8) COUNTER 2 2 Timing ehavior