1 EE 560 MOS INVERTERS: DYNAMIC CHARACTERISTICS
C gsp V DD C sbp C gd, C gs, C gb -> Oxide Caps C db, C sb -> Juncion Caps 2 S C in -> Ineconnec Cap G B D C dbp V in C gdp V ou C gdn D C dbn G B S C in C gb C gsn C sbn C gdn + C gdp + C dbn + C dbp + C in + C gb
V DD 3 S V in G D B i Dp i Dp i C - V ou i Dn D i Dn i C G B S C gdn + C gdp + C dbn + C dbp + C in + C gb
V in DELAY DEFINITIONS 4 V OL V ou τ PHL 1-0 τ PLH 3-2 V 50% V OL 0 1 2 3 V 50% V OL +0.5 [ - V OL ] 0.5 [V OL + ] Avg Prop Delay τ P τ PHL + τ PLH 2
OUTPUT VOLTAGE RISE & FALL TIMES 5 V ou τ fall B - A τ rise D - C V 90% V 10% V OL A B C D V 10% V OL +0.1 [ - V OL ] V 90% V OL +0.9 [ - V OL ]
CALCULATION OF DELAY TIMES QUICK ESTIMATES: ( ) τ PHL C V load HL C V V load OH 50% I avg,hl I avg,hl ( ) τ P LH C V load LH C V V load 50% OL I avg,lh I avg,lh I avg,hl -> approximae average curren during high-o-low V ou ransiion I avg,hl 1 2 i V C( V,V in OH ou ) + i C ( V in,v ou V 50% ) [ ] I avg,lh -> approximae average curren during low-o-high V ou ransiion I avg,lh 1 2 i V C( V,V in OL ou V OL ) + i C ( V in V OL,V ou V 50% ) V OL V ou V 50% V OL [ ] V in τ PHL 1-0 τ PLH 3-2 0 1 2 3 6
MORE ACCURATE CALCULATION OF τ PHL, τ PLH : 7 V DD G S B V in D i Dp i Dp i C - i Dn V ou G D S B i Dn i C i C dv ou d i Dp i Dn
1) V in -RISING CASE: V in 8 IC: V ou, V in V OL -> nmos - ON SAT V ou > V DD -V T0n p-mos OFF LIN 0 < V ou < V DD -V T0n i Dp 0 V ou V OL V in G D B i Dn i C V ou τ PHL 1-0 S - V T0n V 50% dv ou d NOTE THAT: i Dn i Dp << i Dn for all inverer ypes V OL 0 1 1 nmos SAT nmos LIN
V in 0 < < 1 : 9 i Dn k n 2 (V in V T 0n )2 V OL V ou τ PHL 1-0 k n 2 (V V dv OH T 0 n )2 C ou load d - V T0n V 50% for V T 0n <V ou V OL 0 1 1 Since i Dn is INDEP of V ou
V in 1 < < 1 : 10 V OL - V T0n V ou τ PHL 1-0 [ ] i Dn k n 2 2(V V )V V 2 in T 0 n ou ou [ ] dv ou k n 2 2(V V )V V 2 OH T 0n ou ou d V 50% for V ou V T 0n V OL 0 1 1 V ou V 50% 1 d 1 1 ' Vou VOH VT 0 n i Dn dv ou V ou V 50% 1 d 2 2 Vou VOH VT 0 n k n 2( V T 0n )V ou V ou 1 1 ' 1 1 ' [ ] 2 1 k n 2( V T 0n ) ln V ou 2( V T 0 n ) V ou dv ou V ou V 50% Vou VOH VT 0n
1 1 ' 2 1 k n 2( V T 0n ) ln V ou 2( V T 0 n ) V ou V ou V 50% Vou VOH VT 0n 11 k n ( V T 0 n ) ln 2(V V ) V OH T 0n 50% V 50% τ PHL 1-1 + 1-0 τ PHL 2 V T 0 n k n ( V T 0 n ) 2 + k n ( V T 0n ) ln 2(V V ) V OH T 0 n 50% V 50% k n ( V T 0 n ) 2V T 0n +ln 2(V T 0 n V ) T 0n V 50% 1
k n ( V T 0 n ) 2V T 0n +ln 2(V T 0 n V ) T 0n V 50% 1 12 SUBSTITUTING V 50% 0.5 [V OL + ] τ PHL k n ( V T 0 n ) 2V T 0n +ln 4(V T 0n V ) T 0n + V OL 1 WHERE for CMOS Inverers V OL 0, V DD τ PHL k n (V DD V T 0 n ) 2V T 0n +ln 4(V V DD T 0n V DD V ) T 0n V DD 1
EXAMPLE 6.1 Consider a CMOS inverer wih 1.0 pf, where he IV characerisics of he nmos ransior driver are specified as follows: 13 V GSn 5 V and V DSn > 4V > I Dn I Dnsa 5 ma Assume V in is a sep pulse ha swiches insananeously from 0 o 5 V. Calculae he delay ime necessary for he inverer oupu o fall from is iniial value of 5 V o 2.5 V. V 50% 0.5 [V OL + ] 0.5 [0 + 5 V] 2.5 V FROM IV DATA: a SAT V DSn 5V - V T0n 4 V > V T0n 1 V k n 2 I Dnsa (V GS V T 0n ) 2 10mA (4V) 2 0.625x10 3 A/V 2
0 < < 1 : where i Dn I Dnsa 5mA - V T0n 4 V 5 V 14 1 < < 1 : ' 1 1 k n ( V T 0 n ) ln 2(V V ) V OH T 0n 50% 1pF (0.625x10 3 A/V 2 )(5 1)V 1x10 12 F (0.625x10 3 A/V 2 )4V V 50% 2(5 1)V 2.5V ln 2.5V 5.5 ln 2.5 1.26 ns τ PHL 0.2 ns+1.26ns 1.46ns
EXAMPLE 6.2 Consider a CMOS inverer wih 1.0 pf and V DD 5 V, where he IV characerisics of he nmos ransior driver are specified as follows: k n µ n C ox 20 µa/v 2, (W/L) n 10, and V T0n 1.0 V Use boh he average-curren mehod and he differenial equaion mehod o calculae τ fall (ime elapased beween he ime V ou V 90% 4.5 V o he ime a which V ou V 10% 0.5 V). average-curren mehod 5V 4.5V 5V I avg,fall 1 2 i V V,V C in OH ou V 90% 1 2 0.5V [ ( ) + i C ( V in,v ou V 10% )] 1 2 k V V n in T 0 n ( ) ( ) 2 + 1 2 k 2(V V )V V 2 n in T 0 n ou ou [( ) 2 + 2( V T 0n )V 10% V 2 ] 10% 1 4 k n V T 0n ( ) 15 1 4 20x10 6 (A/V 2 )(10) ( 5 1) 2 V 2 + ( 2(5 1)0.5 (0.5) 2 )V 2 [ ] 0.9875mA
average-curren mehod con. τ fall V I avg,fall 1x10 12 F(4.5 0.5)V 0.9875x10 3 A differenial equaion mehod SAT for 4.0 V < V ou < 4.5 V dv ou d dv ou d 1 2 k V n ( V in T 0n) 2 5 V 4.05x10 9 s 4.09ns V 90% - V T0n V 10% ( ) 2 20x10 6 A/V 2 (10) k n V 2C in V T 0 n load 1.6x10 9 V/s 2(1x10 12 F) V ou SAT 0 (5 1) 2 τ fall 2-0 sa LIN 2 16 sa - 0 0.3125 ns
differenial equaion mehod con sa 0.3125 ns LIN for 0.5 V < V ou < 4.0 V dv ou d 2 V 90% - V T0n 1 2 k 2(V V )V V 2 n( in T 0n ou ou ) V ou SAT dv d 2 C ou load 2 Vou 4.0 V k n 2(V in V T 0n )V ou V ou sa V ou 0.5V ( ) 2 sa 1 k n (V in V T 0 n ) ln 2(V V ) V in T 0n 10% 5 V 5 V 1x10 12 F 1 20x10 6 A/V 2 (10) (5 1)V V 10% τ fall 2-0 V 10% 0 0 2 sa LIN 2(5 1) 0.5 ln 3.385ns 0.5 17 4.09 ns I avg mehod
2) V in -FALLING CASE: IC: V ou V OL, V in -> V V DD OL nmos - OFF SAT V ou < -V T0p p-mos ON LIN -V T0p < V ou < V DD V in 18 V OL 0 τ PLH 1-0 V in G S B V GS V in - V DD V DS V ou - V DD Vou V DD D i Dp i C i Dp V 50% dv ou d i Dn 0 i D p i C V ou -V T0p V OL 0 0 1 1 nmos SAT nmos LIN
τ PLH k p ( V OL V T 0 p ) V 50% 0.5 [V OL + ], τ PLH k p (V DD V T 0p ) 2 V T 0 p V T 0p +ln 2(V V V ) OH OL T 0 p 1 V 50% FOR CMOS INV: V OL 0, V DD 2 V T 0 p V DD V T 0p +ln 4(V V ) DD T 0p 1 V DD 19 τ PHL k n ( V T 0 n ) 2V T 0n +ln 2(V T 0 n V ) T 0n V 50% 1 FOR CMOS INV: V OL 0, V DD τ PHL k n (V DD V T 0 n ) 2V T 0n +ln 4(V V DD T 0n V DD V ) T 0n V DD 1
CONDITIONS FOR Balanced CMOS Inverer Propagaion Delays, i.e. τ PHL τ PLH 20 τ PLH k p (V DD V T 0p ) 2 V T 0 p V DD V T 0p +ln 4(V V ) DD T 0p 1 V DD τ PHL k n (V DD V T 0 n ) 2V T 0n +ln 4(V V DD T 0n V DD V ) T 0n V DD 1 where & FOR τ PHL τ PLH V T0n V T0p k n k p or
NOTE THAT: Calculaion of τ PHL, depends largely on NMOS driver, i.e. nearly same for all INV ypes. Calculaion of τ PLH, depends largely on he load device and is operaion, i.e. differen for all INV ypes. 21 CONSIDER depleion NMOS Load: dv C ou load i d D,L (V ou ) V T,L V T 0,L + γ 2φ F +V ou 2φ F ( ) SAT: V DS,L V DD - V ou > 0 - V T,L > V ou < V DD + V T,L [ ] 2 I D,L k n,l 2 V (V ) T,L ou LIN: V DS,L V DD - V ou < 0 - V T,L > V ou > V DD + V T,L [ ] I D,L k n,l 2 2( V (V ))(V V ) (V V T,L ou DD ou DD ou )2
22 τ PLH V ou V DD VT,L Vou V OL dv ou + i D,L (sa) Vou V 50% Vou V DD V T,L dv ou i D,L (lin) τ PLH k n,l V T,L 2( V DD V T,L V OL ) V T,L + ln 2 V (V V ) T,L DD 50% V DD V 50%
V DD Inpu Waveform Slope 23 V ou,v in i Dn ic V in i Dp V ou V DD V in,90% V in,10% τf τ r V in V DD i Dp i Dn i C V ou EMPERICAL DELAY CORRECTIONS FOR INPUT τ r, τ f : τ PHL (acual) τ 2 P HL (sep inpu) + τ r 2 2 τ PLH (acual) τ 2 PLH (sep inpu) + τ f 2 2
τ PHL INVERTER DELAY DESIGN FORMULAS k n (V DD V T 0 n ) 2V T 0n +ln 4(V V DD T 0n V DD V ) T 0n V DD 1 24 where τ PLH k p (V DD V T 0p ) where 2 V T 0 p V DD V T 0p +ln 4(V V ) DD T 0p 1 V DD
EXAMPLE 6.3 Design a CMOS inverer by deermining he W n and W p of he nmos and PMOS ransisors o mee he following specs: -> V h 2 V for V DD 5 V -> Delay ime of 2 ns for a V ou ransiion from 4 V o 1 V, wih 1.0 pf. The process and device parameers are specified as follows: k n µ n C ox 30 µa/v 2, k p µ p C ox 10 µa/v 2 L n L p 1.0 µm V T0n 1.0 V V T0p -1.5 V W min 2 µm (limied by design rules) 25 STEP #1: Saisfy he Delay Consrain:τ PHL from 4 V o 1 V HL > PULL-DOWN > τ PHL deermined by nmos driver NOTE V in and 1 < V ou < 4 V > nmos LIN
dv ou d µ n C ox 2 W n L n 2 [ 2( V T 0n )V ou V ou ] 26 τ delay 2.0x10 9 s 2 1 2 1 µ n C ox W n L n W µ n C n ox L n 1 V ou 1 Vou 4 dv ou 2 [ 2( V T 0n )V ou V ou ] 2( V T 0n ) ln V ou 2( V T 0 n ) V ou V ou 1 Vou 4 W n L n 1x10 12 F (2.0 x10 9 s)(30x10 6 A/V 2 )(4) ln(7) 1 ln(7) 8.108 (2.0)(0.03)(4)
W n 8.108, L L n 1µm > W n 8.108 (1 µm) 8.1 µm n From τ delay spec. STEP #2: Saisfy he V h consrain, where: 1 V T 0 n + ( V k DD + V ) 1 T 0 p 1.0V+ ( 5 + ( 1.5))V V h R k R 1 1 1+ 1+ 1.0V+ 1+ k R 1 ( 3.5)V k R 1 k R k R 2V > k R (1.5) 2 9 4 27 k R µ C ( W/L) n ox n 30W n µ p C ox ( W/L) p 10W p 3 W n W p 9 4 > W p 4 9 (3)W n wih L p 1 µm W p 4 (3)8.1µ m 10.8µ m 9
CMOS RING OSCILLATOR 28 1 V 2 3 1 V 2 V 3,1,2,3,1,2,3 and INV1 INV2 INV3 V 1 V 2 V 3 V 50% V OL τ PHL2τPLH3 τ PHL1τPHL2 τ PLH3τPHL1
V 1 V 2 V 3 29 V 50% V OL τ PHL2 τ PHL1 τ PLH3τPHL1 τ PLH3 τ PHL2 T,1,2,3 and INV1 INV2 INV3 T τ PHL2 + τ PLH3 + τ PHL1 + τ PHL2 + τ PLH3 + τ PHL1 6τ P f 1 T 1 2(3)τ P 1 6τ P For n INVERTERS: Oscillaion FREQ f 1 T 1 or τ 2nτ P 1 P 2nf
ESTIMATION OF INTERCONECT PARASITICS 30 L W MET Curren Flow h SIO 2 SUB PARASITIC RESISTANCE: R meal ρ L W R shee L W
fringing fields W 31 h C PP FF C oal /C PP -> FRINGING-FIELD FACTOR FF -> INC as /h -> INC, W/h <- DEC, and W/L -> INC (SEE PLOT FF in FIG. 6.18 of TEXT) W C oal ε 2 2π + h ln 1+ 2 h + 2h 2h + 2 pf/µm L for W > /2 C oal ε W π 1 0.0543 h + 2h ln 1+ 2 h + 2h +1.47 pf/µm L 2h + 2 for W < /2
W L 32 C in W in oxf p-sub C oxf C oxf C pa Double-meal double-poly n-well CMOS process C mm C meal-o-meal 2.5 nf/cm 2 C oxm C meal-o-subsrae 5.2 nf/cm 2 C oxp C poly-o-subsrae 6.5 nf/cm 2 C mm C meal-o-poly 12.0 nf/cm 2
B C D E passivaion A m2 m2 m2 m2 m1 m1 field ox poly poly poly field ox field ox F m2 m1 G m2 field ox field ox 33 A B C D E E F G subsrae Layer Poly-subsrae Meal2-sub Poly-meal2 Meal1-sub Meal1-poly Meal1-meal2 Meal1-diffusion Meal2-diffusion Cap Ox Thickness Typ Value C p 3000 Å 50 af/µm 2 C m2 9000 Å 20 af/µm 2 C m2p 6000 Å 30 af/µm 2 C m1 6000 Å 30 af/µm 2 C m1p 3000 Å 60 af/µm 2 C m2m1 6000 Å 50 af/µm 2 C m1d 3000 Å 60 af/µm 2 Passivaion 6000 Å 30 af/µm 2 field ox 1 µm CMOS Capaciances ox 200Å C g 1800 af/µm 2 af 10-18 F
A B 32 Z ou Z c RLCG Transmission Line C V A τ delay Z ou << Z c τ buffer + τ fligh τ rise τ sele
ROUTE-LENGTH DESIGN GUIDE Node: a region of conneced pahs where he delay associaed wih signal prop is small compared o gae delays. 35 To ignore he RC delay of inerconnec, τ W << τ Pgae L lengh of roue r shee resisance c cap per uni lengh EXAMPLE: Consider a minimum widh meal1 roue o a node wih an associaed gae delay of 200 ps. Conservaively, L W < 5000λ λ design rule parameer GUIDELINES FOR IGNORING RC DELAYS (Wese, pp 205) Layer Max Lengh (L W ) meal3 10,000 meal2 8000 meal1 5000 silicide 600 poly 200 diffusion 60
POWER DISSIPATION 36 P s Saic power dissipaion due o leakage curren or oher curren drawn coninuously from he power supply. P d dynamic power dissipaion due o charging and discharging load capaciances (v in assumed o be square-like) P sc shor circui power dissipaion due o charging and discharging load capaciances during he inie rise and fall imes of v in.
V DD DYNAMIC POWER DISSAPATION V in, V ou 37 G S B V in D i Dp i Dp i C - i Dn G D B S i Dn T V ou i C P d 1 T v()i()d 0 V OL i C nmos ON T/2 T pmos ON nmos ON P d 1 T T/ 2 V ()i ()d ou Dn + 1 0 T T ( V DD V ou ())i Dp ()d T/ 2 where dv i Dn () C ou load d i Dp () dv ou d
P d 1 T T/ 2 0 V ou () dv C ou load d d + 1 T T T/ 2 ( V DD V ou ()) dv C ou load d d 38 V in, V ou V OL i C 0 nmos ON T/2 T pmos ON VDD nmos ON P d 1 T C V ()dv load ou ou + 1 VDD T C V V load( () DD ou )dv ou 0 1 2 T C V ou V ou 0 load + C 2 V ou VDD load V DD V ou V 2 ou V ou V DD 2 V ou 0
P d 1 2 T C V ou load V ou 0 2 V ou VDD + V DD V ou V 2 ou V ou V DD 2 V ou 0 39 1 T C V 2 load DD 2 P d V DD f APPLIES TO GENERAL CMOS LOGIC CIRCUITS V DD pmos Logic nmos Logic i Dp i Dn i C V ou
POWER-DELAY PRODUCT 40 where P * average swiching power dissipaion a max avg operaing frequency f max. & AVERAGE ENERGY required for a gae o swich is oupu from LOW o HIGH and from HIGH o LOW FUNDAMENTAL PARAMETER used o for measuring qualiy and performance of a CMOS process and gae design
POWER METER SIMULATION 41 V DD i DD + V s 0 + i βi C s R y y s V y Periodic Inpu T Period DEVICE or CIRCUIT C y dv y d βi S V y R y IF R y C y >> T SET C β V y DD T 1 T V y (T) V DD T i DD(τ)d τ > P d 0