Ch 9. Sequential Logic Technologies Technology Contemporary Logic Design
Overview Basic Sequential Logic Components FSM Design with Counters FSM Design with Programmable Logic FSM Design with More Sophisticated Programmable Logic Case Study: Traffic Light Controller Technology Contemporary Logic Design 2
Sequential logic implementation Implementation discrete logic gates and flip-flops ROMs or PALs/PLAs CPLDs or FPGAs Design procedure state diagram state transition table state assignment next state and output functions Technology Contemporary Logic Design 3
Median filter FSM Remove single s between two s (output = PS3) Reset I PS PS2 PS3 NS NS2 NS3 X X X X X X Technology Contemporary Logic Design 4
Median filter FSM (cont d) Realized using the standard procedure and individual FFs and gates I PS PS2 PS3 NS NS2 NS3 X X X X X X NS = Reset (I) NS2 = Reset ( PS + PS2 I ) NS3 = Reset PS2 O = PS3 Technology Contemporary Logic Design 5
Median filter FSM (cont d) But it looks like a shift register if you look at it right Reset Reset Technology Contemporary Logic Design 6
Median filter FSM (cont d) An alternate implementation with S/R FFs Reset In R D S Q R D S Q R D S Q Out R = Reset S = PS2 I NS = I NS2 = PS NS3 = PS2 O = PS3 CLK The set input (S) does the median filter function by making the next state whenever the input is and PS2 is ( input to state xx) Technology Contemporary Logic Design 7
Implementation using PALs Programmable logic building block for sequential logic macro-cell: FF + logic D-FF Two-level logic capability like PAL (e.g., 8 product terms) D Q Q Technology Contemporary Logic Design 8
Using a Shift Register 4-bit string (, ) recognizer / / Reset / / / / / / / / / / / / / / / / / / / / / / / / / / / / Technology Contemporary Logic Design 9
Using a Shift Register Initial realization Correction by adding a counter Technology Contemporary Logic Design
FSM Design with Counters Synchronous counters: CLR, LD, CNT Four kinds of transition for each state: To State (CLR) To next state in sequence (CNT) To arbitrary next state (LD) Loop in current state CLR CNT n n+ m no signals asserted LD Careful state assignment is needed to reflect basic sequencing of the counter Technology Contemporary Logic Design
BCD to Excess 3 Serial Converter Conversion Process BCD Excess 3 Code Bits are presented in bit serial fashion starting with the least significant bit Single input X, single output Z Technology Contemporary Logic Design 2
BCD to Excess 3 Serial Converter (Cont d) Reset /, / / /, / S / S / S3 / S5 / S2 S4 S6 /, / / / State Diagram Present State S () S () S2 (4) S3 (2) S4 (5) S5 (3) S6 (6) Next State X= X= S S2 S3 S4 S4 S4 S5 S5 S5 S6 S S S -- Output X= X= -- State Transition Table Note the sequential nature of the state assignment Technology Contemporary Logic Design 3
Serial Converter: Transition Table Inputs/Current State Next State Outputs X Q2 Q Q Q2+ Q+ Q+ Z CLR LD EN C B A X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X CLR signal dominates LD which dominates Count Technology Contemporary Logic Design 4
Serial Converter (Cont d) Counter-based implementation of code converter When the state diagram has fewer out-of-sequence jumps, a counter based implementation can be very effective Technology Contemporary Logic Design 5
Rom-Based Design Combinational Logic Registers Inputs Output Function Next State Function Outputs Block Diagram for Synchronous Mealy Machine State ROM Registers Inputs A D An- Dk- An Dk An+m- Dk+m- State Outputs ROM-based Realization Inputs & Current State form the address ROM data bits form the Outputs & Next State Technology Contemporary Logic Design 6
Rom-Based Design (Cont d) ROM ADDRESS ROM Outputs X Q2 Q Q Z D2 D D X X X X X X Q2 Q Q converter ROM Z D2 D D CLK 9 3 2 5 4 \Reset D C B A CLK CLR 75 QD QD QC QC QB QB QA QA 5 4 7 6 2 3 Z X X X X X X X X Excess-3 synchronous Mealy ROMbased implementation Technology Contemporary Logic Design 7
PLA-Based Design State assignment with NOVA Reset S = S = S2 = S3 = S4 = S5 = S6 = /, / / /, / S / S / S3 / S5 / S2 S4 S6 /, / / / Technology Contemporary Logic Design 8
PLA-Based Design (Cont d).i 4.o 4.ilb x q2 q q.ob d2 d d z.p 6 --- - --- - --- -.e Espresso Inputs.i 4.o 4.ilb x q2 q q.ob d2 d d z.p 9 - - -- -- -- -- -- ---.e Espresso Outputs Q2 + = Q2 Q + Q2Q Q + = X Q2 Q Q + XQ2 Q + X Q2Q + QQ Q + = Q Z = XQ + X Q 9 product term implementation Technology Contemporary Logic Design 9 X X Q2 Q Q converter PLA Z D2 D D CLK 9 3 2 5 4 \Reset D C B A CLK CLR 75 QD QD QC QC QB QB QA QA 5 4 7 6 2 3 Z
PAL-Based Design (Cont d) PALH8: inputs, 8 outputs, 2 product terms per OR gate Q2+ = Q2 Q + Q2Q Q+ = X Q2 Q Q + XQ2 Q + X Q2Q + QQ Q+ = Q Z = XQ + X Q Q+ = Q+Q2 Q = X Q2 Q Q + XQ2 Q Q2 = X Q2Q + QQ 2 3 4 5 8 9 2 3 6 7 2 2 24 25 28 29 3 3 + X Q2 + X Q2 Q Q 2 3 4 5 6 7 8 9 PALH8 AND Gate Array 2 9 8 7 6 5 4 3 2 Q2 + Q + Q + Z Q2 Q Q Q Q2 8 9 6 7 24 25 32 33 4 4 Q Q2 Q + Q + Z Technology Contemporary Logic Design 2
Alternative PAL Architectures D2 = Q2Q + Q2 Q D = X Q2 Q Q + XQ2 + XQ + Q2Q + QQ D = Q Z = XQ + X Q Technology Contemporary Logic Design 2
Vending machine example (Moore PLD mapping) D D OPEN = reset'(q'n + QN' + QN + QD) = reset'(q + D + QN) = QQ CLK DQ Q N Seq DQ Q D Seq DQ Open Reset Technology Contemporary Logic Design 22 Com
Vending machine (synch. Mealy PLD mapping) OPEN = reset'(qqn' + QN + QD + Q'ND + QN'D) CLK DQ Q N Seq DQ Q D Seq OPEN DQ Open Reset Seq Technology Contemporary Logic Design 23
22V PAL Combinational logic elements (SoP) Sequential logic elements (D-FFs) Up to outputs Up to FFs Up to 22 inputs Technology Contemporary Logic Design 24
22V PAL Macro Cell Sequential logic element + output/input selection AR: Asynchronous Reset SP: Synchronous Preset Technology Contemporary Logic Design 25
CPLD (Complex Programmable Logic Device) Altera MAX (Multiple Array Matrix) Family Array of EPLD + Programmable Interconnect Array EPROM technology Logic Array Blocks LAB A LAB H Global Routing: Programmable Interconnect Array LAB B LAB G EPM528: LAB C P I A LAB F 8 Fixed Inputs 64 I/O Pins 8 LABs 6 Macrocells/LAB 32 Expanders/LAB LAB D LAB E Technology Contemporary Logic Design 26
FPGA (Field Programmable Gate Array) Array of programmable logic-blocks with programmable interconnects Actel Programmable Gate Array Multiplexer-based logic blocks Anti-fuse technology for interconnects Xilinx Logic Cell Array SRAM-based logic blocks and interconnects Technology Contemporary Logic Design 27
FPGA (Cont d) Actel Programmable Gate Arrays Rows of programmable logic building blocks + rows of interconnect Anti-fuse Technology: Program Once Use Anti-fuses to build up long wiring runs from short segments I/O Buffers, Programming and Test Logic I/O Buffers, Programming and Test Logic.................. I/O Buffers, Programming and Test Logic Logic Module Wiring Tracks 8 input, single output combinational logic blocks I/O Buffers, Programming and Test Logic FFs constructed from discrete cross coupled gates Technology Contemporary Logic Design 28
FPGA (Cont d) Actel Logic Module SOA S S D D 2: MUX Basic Module is a Modified 4: Multiplexer 2: MUX Y D2 D3 2: MUX R "" SOB Example: Implementation of S-R Latch "" "" 2: MUX 2: MUX 2: MUX Q S Technology Contemporary Logic Design 29
FPGA (Cont d) Xilinx Logic Cell Arrays CMOS Static RAM Technology: programmable on the fly! All personality elements connected into serial shift register Shift in string of 's and 's on power up General Chip Architecture: Logic Blocks (CLBs) IO Blocks (IOBs) Wiring Channels IOB IOB IOB IOB IOB CLB CLB IOB Wiring Channels IOB CLB CLB IOB Technology Contemporary Logic Design 3
FPGA (Cont d) IO block Inputs: OUT INV Program Controlled Options TS INV OUTPUT SOURCE SLEW RATE PASSIVE PULLUP Vcc Tri-state enable bit to output input, output clocks Enable Output Outputs: input bit Internal FFs for input & output paths Out D Q MUX Output Buffer PAD Fast/Slow outputs Direct In R 5 ns vs. 3 ns rise Pull-up used with unused IOBs Registered In Q R D TTL or CMOS Input Buffer Clocks Global Reset Technology Contemporary Logic Design 3
FPGA (Cont d) Xilinx LCA Architecture Configurable Logic Block (CLB) 2 4-bit address SRAMs Reset 2 FFs Any function of 5 Variables Global Reset Clock, Clock Enb DIN Clock A B C D E Q Combinational Function Generator Q2 F G Mux Mux Mux D D RD Q CE RD Q CE Mux Mux X Y Independent DIN Clock Enable Technology Contemporary Logic Design 32
FPGA (Cont d) n-input Majority Circuit Assert whenever n/2 or greater inputs are n-input Parity Functions 5 input = CLB, 2 Levels of CLBs yield up to 25 inputs! 5-input Majority Circuit CLB 9 Input Parity Logic CLB 7-input Majority Circuit CLB CLB CLB CLB Technology Contemporary Logic Design 33
FPGA (Cont d) 4-bit Binary Adder A3 B3 A2 B2 A B A B Cin CLB CLB CLB CLB Full Adder, 4 CLB delays to final carry out Cout S3 C2 S2 C S C S A3 B3 A2 B2 A B A BCin CLB S2 CLB S 2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out S3 S Cout C Technology Contemporary Logic Design 34
FPGA (Cont d) Interconnect Direct Connections Global Long Line Horizontal/Vertical Long Lines Switching Matrix Direct Connections Horizontal Long Line DI CE A B X C CLB K Y E D R Switching Matrix DI CE A B X C CLB K Y E D R Connections Horizontal Long Line DI CE A B X C CLB2 K Y E D R DI CE A B X C CLB3 K Y E D R Vertical Long Lines Global Long Line Technology Contemporary Logic Design 35
FPGA (Cont d) Xilinx Application Example (BCD to Excess 3 FSM) Q2+ = Q2 Q + Q2 Q Q+ = X Q2 Q Q + X Q2 Q + X Q2 Q + Q Q Q+ = Q Z = X Q + X Q Synchronous Mealy Machine No function has more than 4 variables + 4 FFs implies 2 CLBs Global Reset to be used Place Q2+, Q+ in one CLB and Q, Z in second CLB --> maximize use of direct & general purpose interconnections Technology Contemporary Logic Design 36
FPGA (Cont d) Implementing the BCD to Excess 3 FSM Clk Clk Q2+ = Q2 Q + Q2 Q Q+ = X Q2 Q Q + X Q2 Q + X Q2 Q + Q Q Q+ = Q Z = X Q + X Q X CE DI B C K CE Q2 Q Q A FG FG X Y Q2 Q DI B C K CE Q2 X Q Q X Q A FG FG X Y Q Z E D RES E D RES CLB CLB2 Technology Contemporary Logic Design 37
Case Study: Traffic Light Controller A busy highway is intersected by a little used farmroad Detectors C sense the presence of cars waiting on the farmroad with no car on farmroad, light remain green in highway direction if vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green these stay green only as long as a farmroad car is detected but never longer than a set interval when these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green even if farmroad vehicles are waiting, highway gets at least a set interval as green Assume you have an interval timer that generates: a short time pulse (TS) and farm road a long time pulse (TL), in response to a set (ST) signal. car sensors TS is to be used for timing yellow lights and TL for green lights highway Technology Contemporary Logic Design 38
Traffic Light Controller (cont d) Decomposition into primitive subsystems Controller FSM: next state/output functions, state register Short time/long time interval counter Car Sensor Output Decoders and Traffic Lights Technology Contemporary Logic Design 39
Traffic Light Controller (cont d) Block diagram of complete traffic light system Technology Contemporary Logic Design 4
Traffic Light Controller (cont d) Technology Contemporary Logic Design 4
Traffic Light Controller (cont d) Tabulation of inputs and outputs inputs description outputs description reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights TS short time interval expired ST start timing a short or long interval TL long time interval expired Tabulation of unique states some light configurations imply others state HG HY FG FY description highway green (farm road red) highway yellow (farm road red) farm road green (highway red) farm road yellow (highway red) Technology Contemporary Logic Design 42
Traffic Light Controller (cont d) Next State/Output Logic State Assignment: HG=, HY=, FG=, FY= P = CTLQ + TS QQ + C Q Q + TS QQ P = TSQQ + Q Q + TS QQ ST = CTLQ + C Q Q + TSQQ + TSQQ H = TSQQ + Q Q + TS QQ H = TS QQ + TSQQ F = Q F = TS QQ + TSQQ PAL/PLA Implementation 5 inputs, 7 outputs, 8 product terms PAL 22V 2 inputs, prog. IOs, 8 to 6 prod terms per OR ROM Implementation 32 word by 8-bit ROM (256 bits) Reset may double ROM size Technology Contemporary Logic Design 43
Traffic Light Controller (cont d) Next State Logic Counter-based Implementation HG=, HY=, FG=, FY= Technology Contemporary Logic Design 44
Traffic Light Controller (cont d) Next State Logic Counter-based Implementation Dispense with direct output functions for the traffic lights Technology Contemporary Logic Design 45
Sequential logic implementation summary Models for representing sequential circuits finite state machines and their state diagrams Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure deriving state diagram deriving state transition table assigning codes to states determining next state and output functions implementing combinational logic Implementation technologies random logic with FFs PAL/PLA/ROM with FFs CPLD/FPGA Technology Contemporary Logic Design 46