S.E. Sem. III [EXTC] Digital System Design Time : 3 Hrs.] Prelim Paper Solution [Marks : 80 Q.1 Solve following : [20] Q.1(a) Explain the following decimals in gray code form [5] (i) (42) 10 (ii) (17) 10 ns.: 1. (42) 10 : 42 21 10 5 2 1 0 1 0 1 0 1 Decimal to binary conversion : (42) 10 = (101010) 2 Gray Code conversion : 1 0 1 0 1 0 1 1 1 1 1 1 (42) 10 = (111111) 2 in gray code 2. (17) 10 : 17 8 4 2 1 1 0 0 0 1 Decimal to binary conversion (17) 10 = (10001) 2 Gray Code conversion : 1 0 0 0 1 1 1 0 0 1 (17) 10 = (10001) 2 in gray code. Q.1(b) Design a full adder using 3:8 Decoder [5] ns.: 3 : 8 decoder has 3 input lines and 8 output line. Full adder is designed the following : B C S Ca 0 0 0 0 0 0 1 0 0 1 1 0 2 0 1 0 1 0 3 0 1 1 0 1 4 1 0 0 1 0 5 1 0 1 0 1 6 1 1 0 0 1 7 1 1 1 1 1 Thus, S = m(1,2,4,7) Ca = m(3,5,6,7) 1
: S.E. DSD Q.1(c) Convert JK flip flop to T flip flop. [5] ns.: Truth table of T Flip-Flop Excitation table of JK flip-flop T Q n Q n+1 Q n Q n+1 J K 0 0 0 0 0 0 X 0 1 1 0 1 1 X 1 0 1 1 0 X 1 1 1 0 1 1 X 0 Q.1(d) ns.: Conversion Table : K-map simplification : T Q n Q n+1 J K For J For K 0 0 0 0 X T 0 1 T 0 1 Q 0 1 1 X 0 n Q n 1 0 1 1 X 0 0 1 0 X X 1 1 0 X 1 1 X X 1 0 1 J = T K = T Thus, T J K Perform the following operation using 2 s compliment (i) (7) 10 (15) 10 (ii) (50) 10 (2) 16 Comment on results of (i) and (ii) Q n Q n [5] 2
Prelim Question Paper 3
: S.E. DSD Q.2(a) Prove that NND and NOR gates are Universal gates. [10] ns.: NND and NOR are universal gates. This means using NND and NOR we can construct any other gates such as ND, OR NOT, XOR. This can be proved in the following way. 1) Constructing NOT : NND : NOR : 2) Constructing ND : NND : B NOR : B 3) Constructing OR : NND : B NOR : y 1 =.B B B y 1 =.B y =. = y 1 y 1 y 1 y = y.y = y 1 1 1 =.B =. B y = B =.B =. B y =.B = B = + B y = y y = y 1 1 1 = B = + B y = = B y 1 4
Prelim Question Paper 4) Constructing XOR / XNOR : XOR XNOR y = B y = B B NND Q.2(b) Design 3 bit Binary to gray code Converter [10] ns.: 5
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Prelim Question Paper Q.3(a) ns.: Minimize the following expression using Quine Mc cluskey technique. F(,B,C,D)= (0,1,2,3,5,7,9,11) No. B C D 0 m 0 0 0 0 0 1 m 1 0 0 0 1 2 m 2 0 0 1 0 3 m 3 0 0 1 1 5 m 5 0 1 0 1 7 m 7 0 1 1 1 9 m 9 1 0 0 1 11 m 11 1 0 1 1 1) Grouping according to number of 1 s Group B C D G 0 0 0m 0 0 0 0 0 G 1 1 0m 1 0 0 0 0 2 0m 2 0 0 1 1 G 2 3 0m 3 0 0 1 0 5 0m 5 0 1 0 1 9 0m 9 1 0 0 1 G 3 7 0m 7 0 1 1 1 11 0m 11 1 0 1 1 2) Comparing Group B C D G 0 G 1 m 0 m 1 0 0 0 m 0 m 2 0 0 0 G 1 G 2 m 1 m 3 0 0 1 m 1 m 5 0 0 1 m 1 m 9-0 0 1 m 2 m 3 0 0 1 G 2 G 3 m 3 m 7 0 1 1 m 3 m 11 0 1 1 m 5 m 7 0 1 1 m 9 m 11 1 0 1 3) Comparing Group B C D G 0 G 1 G 2 m 0 m 1 m 2 m 3 0 0 m 0 m 2 m 1 m 3 0 0 G 1 G 2 G 3 m 1 m 3 m 5 m 7 0 1 m 1 m 3 m 9 m 11 0 1 m 1 m 5 m 3 m 7 0 1 m 1 m 9 m 3 m 11 0 1 B D BD [10] 7
: S.E. DSD m 0 m 1 m 2 m 3 m 5 m 7 m 9 m 11 B ( ) ( ) (0,1,2,3) D ( ) ( ) (1,3,5,7) B D ( ) ( ) (1,3,9,11) F(,B,C,D) = B + D + B D Q.3(b) What are shift registers? How are they classified? Explain working of any one type of shift register. ns.: [10] 8
Prelim Question Paper 9
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Prelim Question Paper 11
: S.E. DSD Q.4(a) Design a 2 bit comparator and implement using logic gates [10] ns.: Input Truth table: B Input Output 1 0 B 1 B 0 < B = B > B n-bit comparator 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 > B = B < B 0 0 1 1 1 0 0 0 1 0 0 0 0 1 Output 0 1 0 1 0 1 0 0 1 1 0 1 0 0 K-map for < B : 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 1 0 K-map for = B : 12
Prelim Question Paper K-map for > B Implementation : 1 B1 0 B1 B0 1 0 B0 1 0 B1 B0 1 0 B1 B0 1 0 B1 B0 1 0 B1 B0 1 B1 1 0 B0 f(,b,c,d) Output > B < B 0 B1 B0 13
: S.E. DSD Q.4(b) Explain Master slave JK Flip flop [5] ns.: Master-Slave J-K flip flop is a cascade of two S-R flip flop with feedback from the outputs of the second to the inputs of the first, as shown in the figure below. Positive clock pulse are applied to the first flip-flop and the clock pulses are inverted before these are applied to the second flip-flop. When Clk = 1 the first flip-flop is enabled and the outputs Q m and Q m respond to the inputs J & K according to table below. Truth table of J.K flip flop. Inputs Outputs J n K n Q n+1 0 0 Q n 1 0 1 0 1 0 1 1 Q n t this time second flip-flop is inhibited because its clock is low (Clk 0) When Clk goes low Clk 1, the first flip-flop is inhibited and second flip-flop is enabled, because now its clock is HIGH Clk 1. Therefore the outputs Q & Q follows the outputs Q m & Q m respectively (Second & third row of table) Since the second flip-flop simply follows the first one. It is referred to as the slave and the first one as the master. Hence this configuration is referred to as masterslave (M-S) flip-flop. In this circuit the inputs to the gala G 3M & G 4m do not change during the clock pulse therefore the race round condition does not exit. The state to the master-slave flip-flop changes at the Pr negative transition (tracking edge) of the clock pulse. J Q The logic symbol of an M-S flip-flop is shown. M-S Fit the check input terminals the symbol is used to Clk J-K illustrate that the output changes when the clock makes Flip-Flop a transition & the accompanying bubble signifies negative transition (change is Clk from 1 to 0) K Q 14 Cr Logic Symbol
Prelim Question Paper Q.4(c) Convert T flip flop to D flip flop. [5] ns.: Q.5(a) What is shift register? Explain any one type of shift register. Give its [10] applications. ns. : Shift Register : n array of flip flops is required to store binary information, number of bits in binary word. Thus one flip flop is required for each bit. The combination of n f/p can therefore store n bit binary word. It is called a register. shift is an n bit register with a provision for shifting its stored data by one bit provision at each tick of the clock. Thus, it is a storage device that can be used to store data and shift it left or right. 15
: S.E. DSD pplications : They find themselves in a variety of applications including microprocessor. In 8085 have seven 8 bit registers, referred as general purpose register and five one bit registers referred to as flags. Types : They can be classified as follows based on the method which data can be loaded on and read from shift register : a) Serial in serial out shift registers. b) Serial in parallel out shift register. c) Parallel in serial out shift register. d) Parallel in parallel out shift register. Serial in serial out shift register (Left shift) Dout Q 3 D 3 Clk Q 2 D 2 Clk Clk The serial input (Din) is shifted by one bit position at each tick of the clock. This data bit (Din) appears at the Dout after 4 clock ticks. Thus a n bit serial in serial out shift register can be used to delay a signal by n clock ticks. Initially all flip flops are reset Q 3 Q 2 Q 1 Q 0 = 0000 Consider Din = 1 fter the 1 st clock pulse Q 3 Q 2 Q 1 Q 0 = 0 0 0 1 fter the 2 nd clock pulse Q 3 Q 2 Q 1 Q 0 = 0 0 1 1 fter the 3 rd clock pulse Q 3 Q 2 Q 1 Q 0 = 0 1 1 1 fter the 4 th clock pulse Q 3 Q 2 Q 1 Q 0 = 1 1 1 1 Q 1 D 1 Q.5(b) Explain Full dder circuit using PL having three inputs, 8 product terms and two outputs. ns.: Clk Q 0 D 0 Clk Din [10] 16
Prelim Question Paper 17
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Prelim Question Paper Q.6 Explain the following : [20] Q.6(a) Explain VHDL Code for Full Subtractor. [5] ns.: Lirary IEEE; Use IEEE.STD LOGIC 1164.LL; Use IEEE.STD LOGIC RITH.LL; Use IEEE.STD LOGIC UNSIGNED.LL; Entity full_sub is Port (a,b,c: in std_logic; bo, d: out std_logic); end full_sub; architecture behavioural of full_sub is begin d < = a xor b xor c; b 0 < = ((not a) and b) or (b and c) or ((not a) and c) end behavioural; Q.6(b) Explain SRM and DRM. [5] ns.: SRM DRM 1) It stands for static random access memory. It stands for dynamic random access memory. 2) It does not require periodic refreshing. It requires periodic refreshing. 3) Simple to construct. Difficult to construct. 4) No. of transistors required to hold the data is more. It requires a transistor & capacitor for every bit of data. 5) Consumes less power. Consumes more power. 6) It is more expensive. It is less expenses. Q.6(c) Compare TTL and CMOS logic families. [5] ns.: TTL CMOS 1) It utilizes BIT. It utilizes FET. 2) Less functional density. High functional density. 3) It consumes more power. It consumes less power. 4) Less susceptible to static discharge. They are more susceptible discharge. 5) Transmission of digital signal becomes difficult & more expensive. Due to longer rise & fall times, transmission becomes simpler & less. Q.6(d) Explain CPLD and FPG. [5] ns.: CPLDs FPGs rchitecture Large, wide fan-in blocks of ND- OR logic rray of small logic blocks surrounded by I/O 19
: S.E. DSD CPLDs FPGs pplications Bus interfaces complex state machines fast memory interfaces wide decoders PL-device integration Logic consolidation board integration replace obsolete devices simple state machines complex controllers / interfaces Key ttributes Fast pin-to-pin performance Predictable timing Easy to use Very high density lots of I/Os and flip-flops generally lower power SRM devices are reprogrammable. Gate Capacity 300-6,000 gates 800-100,000 gates Design Timing Fixed, PL-like very fast pin-topin performance pplication dependent very high shift frequencies Number 30-200 50-400 of I/Os Number of Flip-flops 30-200 100-5,500 EPROM SRM Process EEPROM nti-fuse Technology FLSH EEPROM In-System Programmable Some EEPROM- and FLSH-based devices SRM-based devices and some EEPROM-based devices One-Time Programmable (OTP) EPROM devices in plastic packages. ll anti-fuse-based devices Some EEPROM- and FLSH-based devices Power Consumption 0.5-2.0W static 0.5-4.0W dynamic Very low static dynamic consumption is application dependent, 0.1-2W typical 20