Motivation for CDR: Deserializer (1)

Motivation for CDR: Deserializer (1) Input data 1:2 DMUX 1:2 DMUX channel 1:2 DMUX Input clock 2 2 If input data were accompanied by a well-synchronized clock, deserialization could be done directly. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 1

Providing two high-speed channels (for data & clock) is expensive. Alignment between data & clock signals can vary due to different channel characteristics for the different frequency components. Hence retiming would still be necessary. Clock Data Motivation for CDR (2) input data Clock Recovery circuit retimed data recovered clock PLLs naturally provide synchronization between external and internal timing sources. A CDR is often implemented as a PLL loop with a special type of PD... EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 2

Return-to-Zero vs. Non-Return-to-Zero Formats S x ( f ) NRZ T b S x ( f ) 1 2 3 f T b T b T b RZ 1 0 1 1 0 1 0 2 T b f RZ spectrum has energy at 1/T b NRZ spectrum has null at 1/T b?? conventional phase detector can be used. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 3

Phase Detection of RZ Signals V data V R V d V data V R V d Phase detection operates same as for clock signals for logic 1. V d exhibits 50% duty cycle for logic 0. K pd will be data dependent. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 4

Phase Detection of NRZ Signals V data V R V d V data V R V d Since data rate is half the clock rate, multiplying phase detection is ineffective. RZ signals can use same phase detector as clock signals RZ data path circuitry requires bandwidth that is double that of NRZ. Different type of phase detection required for NRZ signals. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 5

Idea: Mix NRZ data with delayed version of itself instead of with the clock. Example: 1010 data pattern (differential signaling) T b 1 3 5 2T b 2T b 2T b X X 1 2T b 3 2T b 5 2T b = = 1 T b 2 T b fundamental generated EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 6

Operation of D Flip-Flips (DFFs) CMOS transmission gate: DFF: D QI Q latch: D QI Master Slave Symbol: Ideal waveforms: D D0 D1 D2 D Q Q D0 D1 D2 No bubble Q changes following rising edge of EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 7

DFF Setup & Hold Time At rising edge, the master latches and the slave drives. D t setup t hold Q When a data transition occurs within the setup & hold region, metastability occurs. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 8

DFF Clock-to-Q Delay D QI Q Master Slave D D0 D1 D2 t ck-q is determined by delays of transmission gate and inverter. Q D0 D1 D2 t ck-q EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 9

P Realization of Data/Data Mixing : R Q Same as, synchronized with R R early: R synchronized: D0 D1 D2 D3 D0 D1 D2 D3 R Q D0 D1 D2 D3 D0 D1 D2 D3 P D0 D1 D1 D2 D2 D3 D3 D4 D0 D1 D1 D2 D2 D3 D3 D4 Delay between to Q is related to phase between & R EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 10

Define zero phase difference as a data transition coinciding with R falling edge; i.e., R rising edge is in center of data eye. R early (Δφ < 0): R synchronized (Δφ = 0): R Q P Δt T b Δφ 2π = Δt 1 T b 2 Δt T b Δφ Δt =T b 2π + 1 2 EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 11

Phase detector characteristic also depends on transition density: R Q P 0101 pattern: 0011 pattern: R Q P V swing Δt V P = V swing 1 T b 2 Δt V P = V swing 1 2T b 2 In general, V P = V swing α Δt 1 where α average transition density T b 2 EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 12

Constructing CDR PD Characteristic V P Δt T b V swing = Δφ 2π + 1 2 = α Δt T c 1 2 V P = α (α 1) Δφ + V swing 2π 2 V P V swing α = 1 + 1 2 -π +π slope: K pd = α 2π Δφ intercept: Δφ = 0 V P V swing = α 1 2 α = 0.25 1 2 α = 0.5 Both slope and offset of phase-voltage characteristic vary with transition density! EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 13

To cancel phase offset: P Q D0 D1 D2 D3 R Q R R Q R D0 D1 D2 D3 Q R R Always 50% duty cycle; average value is (α 1) V swing 2 +1/2-1/2 -π V P V R V swing +π α = 1 α = 0.5 Δφ K pd still varies with α, but offset variation cancelled. C. R. Hogge, A self-correcting clock recovery circuit, IEEE J. Lightwave Tech., vol. 3, pp. 1312-1314, Dec. 1985. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 14

Transconductance Block I out+ P + P - R - R + I out- I SS I SS EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 15

Due to inherent mixing operation, Hogge PD is not a good frequency detector. A frequency acquisition loop with a reference clock is usually needed: J. Cao et al., OC-192 transmitter and receiver in 0.18µ CMOS, JSSC. vol. 37, pp. 1768-1780, Dec. 2002. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 16

Non-Idealities in Hogge Phase Detector: A. Clock-to-Q Delay (1) R Q P R Q t ck-q R Q R Q R P = Q t ck-q R = Q Q R EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 17

Non-Idealities in Hogge Phase Detector: A. Clock-to-Q Delay (2) Result is an input-referred phase offset: R V P V R V swing +α/2 Q t ck-q φ os Δφ -α/2 t ck-q Q R P R φ os = 2π t ck Q T b EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 18

Non-Idealities in Hogge Phase Detector: A. Clock-to-Q Delay (3) t ck-q R CDR D out R Phase offset moves R away from center of data, making retiming less robust. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 19

Use a compensating delay: Non-Idealities in Hogge Phase Detector: A. Clock-to-Q Delay (4) Set Δt t Q Δt D Δt D Δt R Q P R Q t ck-q R Q R Q R P t ck-q R EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 20

Non-Idealities in Hogge Phase Detector: B. Delay Between P & R (1) P R R Q Q R Q R Q R P R P and R are offset by 1/2 clock period EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 21

Non-Idealities in Hogge Phase Detector: B. Delay Between P & R (2) P R Average value of V control is well-controlled, but resulting ripple causes high-frequency jitter. P R Q V control to VCO R Q R EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 22

R Non-Idealities in Hogge Phase Detector: B. Delay Between P & R (3) Standard Hogge/charge pump operation for single input pulse: Idea: Based on R output, create compensating pulses: R DFF P R Q Q R P (up) R (dn) latch latch P ʹ R ʹ V control latch EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 23

Non-Idealities in Hogge Phase Detector: B. Delay Between P & R (4) P R R DFF Q 1 Q 1 R Q 2 Q 3 latch Q 2 ʹ P Q 4 P (up) latch Q 3 R (dn) ʹ R P (dn) latch Q 4 R (up) V control Cancels out effect of next pulse EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 24

Other Nonidealities of Hogge PD (1) 60 PD Differential Output (mv) 40 20 0-20 -40-60 simulated result of one linear PD response from ideal linear PD -50p -40p -30p -20p -10p 0 10p 20p 30p 40p 50p Data Delay in regard to Clock (s) EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 25

Other Nonidealities of Hogge PD (2) Effect of Transition Density: EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 26

Other Nonidealities of Hogge PD (3) Effect of DFF bandwidth limitation: EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 27

Other Nonidealities of Hogge PD (4) Effect of XOR bandwidth limitation: Since the PD output signals are averaged, XOR bandwidth limitation has negligible effect. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 28

Other Nonidealities of Hogge PD (5) Effect of XOR Asymmetry: EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 29

Binary Phase Detectors Idea: Directly observe phase alignment between clock & data Clock falling edge early: Decrease V control Clock falling edge centered: No change to V control Clock falling edge late: Increase V control Ideal binary phase-voltage characteristic: +1/2 V P V swing Also known as bang-bang phase detector -1/2 Δφ EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 30

D Flip-Flop as Phase Detector Early clock: Data transitions align with clock low R Late clock: Data transitions align with clock high R Realization using double-clocked DFF; note that R/Din connections are reversed: R V P = Top (bottom) DFF detects on Din rising (falling) edge; DFF selected by opposite Din edge to avoid false transitions due to clock-q delay. R V P EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 31

What happens if Δφ=0? t setup t hold If transition at put occurs within setup/hold time, metastable operation results. Q output can hang for an arbitrarily long time if zero crossings of D & occur sufficiently close together. Metastable operation is normally avoided in digital circuit operation(!) D Q EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 32

Dog Dish Analogy??? A dog placed equidistant between two dog dishes will starve (in theory). EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 33

Non-Idealities in Binary DFF Phase Detector 1. Metastable operation difficult to characterize & simulate, varies widely over processing/temperature variations. K pd (and therefore jitter transfer function parameters) are difficult to analyze. Exact value of K pd depends on metastable behavior and varies with input jitter. 2. Large-amplitude pattern-dependent variation is present in phase detector output while locked. 3. During long runs phase detector output remains latched, resulting in VCO frequency changing continuously: R V P f vco EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 34

Idea: Change VCO frequency for only one clock period R V P R early R late Circuit realization should sample data with clock (instead of clock with data) while maintaining bang-bang operation. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 35

Alexander Phase Detector DN UP Q 1 Q 2 R Q 3 Q 4 R Q 1 Q 2 Q 3 Q 4 DN UP R early Q 1 leads Q 3 ; Q 2 /Q 4 in phase R late Q 3 leads Q 1 ; Q 1 /Q 4 in phase EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 36

Simulation Results: Alexander PD DFF outputs VCO control voltage EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 37

Simulation Comparison: Linear vs. Binary V control V control Linear PD very small freq. acquisition range low steady-state jitter Binary PD high freq. acquisition range high steady-state jitter EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 38

Half-Rate CDRs To relax speed requirements for a given fabrication technology, a halfrate clock signal can be recovered: input data R full-rate recovered clock R2 half-rate recovered clock Can be used in in applications (e.g., deserializer) where full-rate clock is not required. Duty-cycle distortion will degrade bit-error ratio & jitter tolerance compared to full-rate versions. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 39

Idea 1: Input data can be immediately demultiplexed with half-rate clock D A R2 D B R2 D0 D1 D2 D3 D4 D A D B D0 D2 D4 D1 D3 synchronized with clock transitions EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 40

Splitting D flip-flops into individual latches: R2 latch X A latch D A X B D B latch latch R2 X A X B synchronized with both R2 & These pulse widths contain phase information. D A D B synchronized with R2 EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 41

Complete Linear Half-Rate PD X A D A R2 R2 P 1 2 R X A X B D B X B P = X A X B J. Savoj & B. Razavi, A 10Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector, JSSC, vol. 36, pp. 761-768, May 2001. D A D B R = D A D B EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 42

Idea 2: Observe timing between, R and quadrature RQ R R RQ RQ S 0 S 1 S 2 Clock early S 0 S 1 S 2 Clock late S 0, S 2 sampled with R transitions S 1 sampled with RQ transitions Phase logic: ( S 0 S 1 = 0) and S 1 S 2 = 1 ( ) ( S 0 S 1 = 1) and ( S 1 S 2 = 0) ( S 0 S 1 = 0) and ( S 1 S 2 = 0) clock early clock late no transition EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 43

D I R V PD RQ D Q J. Savoj & B. Razavi, A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase detector, JSSC, vol. 38, pp. 13-21, Jan. 2003. R R RQ RQ D I D I D Q D Q V PD V PD Clock early Clock late EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 44

DLL-Based CDRs f ref CMU f ck phase generator phase MUX CDR loop CMU JBW can be optimized to minimize f ck jitter. No VCO inside CDR loop; less jitter generation. PD V C Can be arranged to have faster lock time. C D out retimer EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 45

Fast-Lock CDR for Burst-Mode Operation Gated ring oscillator: EN EN high: 7-stage ring oscillator EN low: no oscillation CDR based on 2 gated ring oscillators: R Each ring oscillation waveform is forced to sync with one of the phases. EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 46