FEMTO-ST/time & frequency department jmfriedt@femto-st.fr slides and references at jmfriedt.free.fr February 21, 2018 1 / 17
Basics ADC: discrete time (aliasing) and discrete levels (quantization) V = V ref bits 2 m 1 bits = V (2 m 1) V ref v(t) PM/AM 1/Vr 2 m n(t) x(t) r(t) q(t) Characteristics: sampling rate and resolution 8 bits=48 db dynamic range on input power (20 log 10 (256)) 10 bits=60 db dynamic range on input power 12 bits=72 db dynamic range on input power 16 bits=96 db dynamic range on input power 2 / 17
successive approximation (SAR): as many clock cycles as bits on the output (low cost, low power) Σ : 1-bit converter (comparator) followed by low-pass filtering (audiofrequency, very high resolution thanks to oversampling) flash: voltage ladder with comparator, for very fast (>100 MS/s) ADC pipelined ADC: mix between successive approximation and flash ADC (fast but introduces some latency, higher resolution than single-flash) +dithering Technologies Atmega32U4 datasheet Maxim APP1023 application note 3 / 17
Sample & hold Sample & hold (Track & hold): input stage for keeping the sampled voltage constant Defines the bandwidth over which noise is integrated Possibly much higher than the sampling (conversion) rate Example of external Track&Hold control: Linear Technology LTC1407 Application to stroboscopic measurements 1 : 100 MHz carrier, echo delays at 1.2 and 1.5 µs, 4 GS/s equivalent sampling rate 1 F. Minary, D. Rabus, G. Martin, J.-M. Friedt, Note: a dual-chip stroboscopic pulsed RADAR for probing passive sensors, Rev. Sci. Instrum. 87 p.096104 (2016) 4 / 17
Sample & hold Sample & hold (Track & hold): input stage for keeping the sampled voltage constant Defines the bandwidth over which noise is integrated Possibly much higher than the sampling (conversion) rate Example of external Track&Hold control: Linear Technology LTC1407 Application to stroboscopic measurements 1 : 100 MHz carrier, echo delays at 1.2 and 1.5 µs, 4 GS/s equivalent sampling rate 1 F. Minary, D. Rabus, G. Martin, J.-M. Friedt, Note: a dual-chip stroboscopic pulsed RADAR for probing passive sensors, Rev. Sci. Instrum. 87 p.096104 (2016) 5 / 17
Averaging for improved resolution Noise scales as 1/ M when averaging over M samples 4-times sampling rate loss for 1-additional bit 10 log 10 (4) = 6.02 db/bit Which input interface is better for sampling a 77500 Hz signal? a 16-bit sound card sampling at 192 ks/s or a 8-bit DVB-T sampling at 2 MS/s? 6 / 17
Averaging for improved resolution Noise scales as 1/ M when averaging over M samples 4-times sampling rate loss for 1-additional bit 10 log 10 (4) = 6.02 db/bit Which input interface is better for sampling a 77500 Hz signal? a 16-bit sound card sampling at 192 ks/s or a 8-bit DVB-T sampling at 2 MS/s? f ss = 4 p f s 10 log 10 (f ss /f s ) = 10 log 10 4 p i.e. 10 log 10 (50)/6.02 3 bits 7 / 17
Quantization noise samples are uniformly distributed from q/2 to +q/2 with q the quantization step quantization error e distribution σv 2 = E(e 2 ) = 1 +q/2 e 2 de = 1 [ ] e 3 +q/2 = 1 ( ) q 3 q q/2 q 3 q/2 q 3 8 q3 2 8 = 1 ( ) 2q 3 = q2 q 24 12 V e t 8 / 17
ENOB S v dbv 2 ) /Hz f s V FSR = ENOB = log 6.02 bit/db 2 (1 + 12 fn S floor Measurement: 50Ω load or sine wave on both channels and subtract measurements (impact of track & hold jitter) Sv flicker white noise floor f f =f /2 ENOB: Effective Number Of Bits practically 9 / 17 N s
ENOB S v dbv 2 ) /Hz f s V FSR = ENOB = log 6.02 bit/db 2 (1 + 12 fn S floor Measurement: 50Ω load or sine wave on both channels and subtract measurements (impact of track & hold jitter) v q = v fsr : here the target is M =ENOB. 2 M 1 σ 2 = v 2 q 12 Nt = then the total noise density over the bandwidth is N t = σ2 fs Now we express σ fs = v q 12fs = v fsr 12 fs(2m 1) so 2M = 1 + v fsr 12 fs Nt ENOB = M = log 2 (1 + ) v fsr 12 fs N t c PYB 10 / 17
ENOB S v dbv 2 ) /Hz f s V FSR = ENOB = log 6.02 bit/db 2 (1 + 12 fn S floor Measurement: 50Ω load or sine wave on both channels and subtract measurements (impact of track & hold jitter) PhD Carolina Cárdenas Olaya, Digital Instrumentation for the Measurement of High Spectral Purity Signals (2017), at http://porto.polito.it/2687860/1/polito_phd_thesis.pdf 11 / 17
ENOB S v dbv 2 ) /Hz f s V FSR = ENOB = log 6.02 bit/db 2 (1 + 12 fn S floor Measurement: 50Ω load or sine wave on both channels and subtract measurements (impact of track & hold jitter) 2 V ref, 14 bit ADC: 14 6.02 + 10 log 10 (125 10 6 ) + 10 log 10 (2) ideally ( 154 + 10 log 10 (125 10 6 ) + 1.76)/6.02 = 11.8 bits practically 12 / 17
Oscillator phase noise (a) Input carrier frequency ν 0 = 10 MHz. PhD Carolina Cárdenas Olaya, Digital Instrumentation for the Measurement of High Spectral Purity Signals (2017), at http://porto.polito.it/2687860/1/polito_phd_thesis.pdf σϕ 2 = S ϕ BW = BW 10 Sϕ(dB)/10 13 / 17
Impact of clock jitter jitter impact dependent on fastest slope of signal minimum impact at signal maximum (amplitude fluctuations) V dv dt t v(t) = A cos(ωt) max(dv/dt) = Aω Jitter τ dv = Aωτ σ v = Aωσ τ & τ = 2πϕ/ω σ v = Aσ ϕ 14 / 17
Impact of clock jitter ERROR: SNR degradation = 20 log 10 (2πf in σ τ ) 15 / 17
Bibliography Clock and voltage reference statistical noise impacts on ADC output stability. High bandwidth ADC needed for high frequency signals If low frequency signals, resolution is improved by averaging... but low frequency ADCs usually provide more bits. Adding noise before averaging can improve resolution! [1] M. Bellanger, Traitement numérique du signal : Théorie et pratique, 8e Ed., Sciences Sup, Dunod (2012) [2] B. Widrow & I. Kollár, Quantization Noise: Roundoff Error in Digital Computation, Signal Processing, Control, and Communications, Cambridge University Press (2008) [3] B. Morley, ESE488 Signals and Systems Laboratory (2016), classes.engineering.wustl.edu/ese488/lectures/lecture5a_qnoise.pdf [4] PhD Carolina Cárdenas Olaya, Digital Instrumentation for the Measurement of High Spectral Purity Signals (2017), at http://porto.polito.it/2687860/1/polito_phd_thesis.pdf [5] P.-Y. Bourgeois, T. Imaike, G. Goavec-Merou & E. Rubiola, Noise in High-Speed Digital-to-Analog Converters, IFCS 2015 16 / 17
Low-pass filtering the ADC measurements IIR: a k y n k = b k x n k FIR: y n = b k x n k Delay dependent on N number of coefficients, bits per sample? 17 / 17