Summary Last Lecture

EE247 Lecture 19 ADC Converters Sampling (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track & hold T/H circuits T/H combined with summing/difference function T/H circuit incorporating gain & offset cancellation T/H aperture uncertainty Effect of clock jitter on sampling EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 1 Summary Last Lecture ADC Converters Sampling (continued) Sampling switch considerations Switch induced distortion Sampling switch conductance dependence on input voltage Clock voltage boosters Sampling switch charge injection & clock feedthrough EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 2

Sampling Switch Charge Injection & Clock Feedthrough Summary Extra charge injected onto sampling capacitor @ switch device turn-off Channel charge injection Clock feedthrough to C s via C ov Issues due to charge injection & clock feedthrough: DC offset induced on hold C s Input dependant error voltage distortion Solutions: Complementary switch Addition of dummy switches Bottom-plate sampling EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 3 Switch Charge Injection & Clock Feedthrough Complementary Switch φ 1 V H V G φ 1 φ 1B φ 1B V i φ 1 φ 1B V L t In slow clock case if area of n & p devices widths are equal (W n =W p ) effect of overlap capacitor for n & p devices to first order cancel (cancellation accuracy depends on matching of n & p width and overlap length L D ) Since in CMOS technologies μ n ~2.5μ p choice of W n =W p not optimal from linearity perspective (W p >W n preferable) EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 4

Switch Charge Injection Complementary Switch Fast Clock ( ) Q = W C L V V V ch n n ox n H i th n ch p p ox p i L ( Vth p ) Q = W C L V V 1 Qch n Q ΔVo 2 Cs C ch p s V H V i V L V G t ( ε ) V = V 1+ + V o i os 1 WnCoxLn+ WpCoxLp ε 2 Cs In fast clock case To 1 st order, offset due to overlap caps cancelled for equal device width Input voltage dependant error worse! φ 1 φ 1B EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 5 Switch Charge Injection Dummy Switch M1 V G V GB M2 V O C s V H V G V GB V i Q 1 Q 2 V i W M2 =1/2W M1 1 Q Q Q 2 M1 M1 1 ch + ov V L t M2 M2 2 ch + ov Q Q 2Q 1 For W W Q Q & Q 2Q 2 M 1 M2 M 2 = M1 2 = 1 ov = ov EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 6

Switch Charge Injection Dummy Switch M1 V G V GB M2 V O C s V H V G V GB V i Q 1 Q 2 V i W M2 =1/2W M1 V L t Dummy switch same L as main switch but half W Main device clock goes low, dummy device gate goes high dummy switch acquires same amount of channel charge main switch needs to lose Effective only if exactly half of the charge stored in M1 is transferred to M2 (depends on input/output node impedance) and requires good matching between clock fall/rise EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 7 Switch Charge Injection Dummy Switch V i R V G M1 V GB M2 W M2 =1/2W M1 VO C s C s To guarantee half of charge goes to each side create the same environment on both sides Add capacitor equal to sampling capacitor to the other side of the switch + add fixed resistor to emulate input resistance of following circuit Issues: Degrades sampling bandwidth EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 8

Dummy Switch Effectiveness Test Dummy switch W=1/2W main As Vin is increased Vc1-Vin is decreased channel charge decreased less charge injection Note large Ls good device area matching Ref: L. A. Bienstman et al, An Eight-Channel 8 13it Microprocessor Compatible NMOS D/A Converter with Programmable Scaling, IEEE JSSC, VOL. SC-15, NO. 6, DECEMBER 1980 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 9 φ V i+ V O+ Switch Charge Injection Differential Sampling Cs V V = V V V = V o+ o od i+ i id V + V V + V Voc = = 2 2 Vo+ = Vi+ 1+ 1 + Vos1 V = V 1+ + V o+ o i+ i Vic ( ε ) ( ε ) ( ε + ε ) o i 2 os2 ( ε ε ) V = V + V + V + V V 2 1 2 od id id 1 2 ic os1 os2 V i- Cs To 1 st order, offset terms cancel V O- Note gain error ε still about the same Has the advantage of better immunity to noise coupling and cancellation of even order harmonics EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 10

Avoiding Switch Charge Injection Bottom Plate Sampling φ 1b φ 1a M1 V H V i V O Cs V L φ 1b φ 1a M2 t Switches M2 opened slightly earlier compared to M1 Injected charge by the opening of M2 is constant since its DS voltage is zero & eliminated when used differentially Since C s bottom plate is already open when M1 is opened No charge injected on C s EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 11 Flip-Around Track & Hold φ 2 φ 1 S2A φ 1D φ 1D φ 2 v IN φ 1D C φ 2 S3 S1A S2 v OUT φ 1 S1 Concept based on bottomplate sampling v CM EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 12

Flip-Around T/H-Basic Operation φ 1 high φ 2 φ 1 S2A φ 1D φ 1D φ 2 v IN φ 1D S1A C φ 2 S2 S3 Charging C vout Q φ1 =V IN xc φ 1 S1 v CM Note: Opamp has to be stable in unity-gain configuration EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 13 Flip-Around T/H-Basic Operation φ 2 high φ 2 φ 1 S2A φ 1D φ 1D φ 2 φ 1D C φ 2 S3 Holding v IN S1A S2 v OUT φ 1 S1 Q φ2 =V OUT xc V OUT =V IN v CM EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 14

Flip-Around T/H - Timing φ 2 S2A φ 1D φ 1 φ 1D v IN φ 1D C φ 2 S3 φ 2 S1A φ 1 S1 S2 v CM vout S1 opens earlier than S1A No resistive path from C bottom plate to Gnd charge can not change "Bottom Plate Sampling" EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 15 Charge Injection At the instant of transitioning from track to hold mode, some of the charge stored in sampling switch S1 is dumped onto C With "Bottom Plate Sampling", only charge injection component due to opening of S1 and is to first-order independent of v IN Only a dc offset is added. This dc offset can be removed with a differential architecture EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 16

Flip-Around T/H Constant switch V GS to minimize distortion φ 2 φ 1 S2A φ 1D φ 1D φ 2 v IN φ 1D S1A C φ 2 S2 S3 v OUT φ 1 S1 v CM Note: Among all switches only S1A & S2A experience full input voltage swing EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 17 Flip-Around T/H S1 is chosen to be an n-channel MOSFET Since it always switches the same voltage, it s onresistance, R S1, is signal-independent (to first order) Choosing R S1 >> R S1A minimizes the non-linear component of R = R S1A + R S1 Typically, S1A is a wide (much lower resistance than S1) & constant V GS switch In practice size of S1A is limited by the (nonlinear) S/D capacitance that also adds distortion If S1A s resistance is negligible delay depends only on S1 resistance S1 resistance is independent of V IN error due to finite time-constant independent of V IN EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 18

Differential Flip-Around T/H Choice of Sampling Switch Size THD simulated w/o sampling switch boosted clock -45dB THD simulated with sampling switch boosted clock (see figure) Ref: K. Vleugels et al, A 2.5-V Sigma Delta Modulator for Broadband Communications Applications IEEE JSSC, VOL. 36, NO. 12, DECEMBER 2001, pp. 1887 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 19 Differential Flip-Around T/H S11 S12 Offset voltage associated with charge injection of S11 & S12 cancelled by differential nature of the circuit During input sampling phase amp outputs shorted together Ref: W. Yang, et al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 1931 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 20

Differential Flip-Around T/H Gain=1 Feedback factor=1 φ 1 φ 1 φ2 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 21 Differential Flip-Around T/H Issues: Input Common-Mode Range ΔV in-cm =V out_com -V sig_com Amplifier needs to have large input common-mode compliance EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 22

Input Common-Mode Cancellation Note: Shorting switch M3 added Ref: R. Yen, et al. A MOS Switched-Capacitor Instrumentation Amplifier, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 23 Input Common-Mode Cancellation Track mode (φ high) V C1 =V I1, V C2 =V I2 V o1 =V o2 =0 Hold mode (φ low) V o1 +V o2 =0 V o1 -V o2 = -(V I1 -V I2 )(C 1 /(C 1 +C 3 )) Input common-mode level removed EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 24

T/H + Charge Redistribution Amplifier Track mode: (S1, S3 on S2 off) V C1 =V os V IN, V C2 =0 V o =V os EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 25 T/H + Charge Redistribution Amplifier Hold Mode 2 1 Hold/amplify mode (S1, S3 off S2 on) Offset NOT cancelled, but not amplified Input-referred offset =(C 2 /C 1 ) x V OS, & often C 2 <C 1 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 26

T/H & Input Difference Amplifier Sample mode (S1, S3 on S2 off) V C1 =V os V I1, V C2 =0 V o =V os EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 27 Input Difference Amplifier Cont d Subtract/Amplify mode (S1, S3 off S2 on) During previous phase: V C1 =V os V I1, V C2 =0 V o =V os 1 Offset NOT cancelled, but not amplified Input-referred offset =(C 2 /C 1 )xv OS, & C 2 <C 1 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 28

T/H & Summing Amplifier EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 29 T/H & Summing Amplifier Cont d Sample mode (S1, S3, S5 on S2, S4 off) V C1 =V os V I1, V C2 =V os -V I3, V C3 =0 V o =V os EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 30

T/H & Summing Amplifier Cont d Amplify mode (S1, S3, S5 off, S2, S4 on) 3 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 31 Differential T/H Combined with Gain Stage Employs the previously discussed technique to eliminate the problem associated with high common-mode voltage excursion at the input of the opamp Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 32

Differential T/H Combined with Gain Stage φ1 High Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 33 Differential T/H Combined with Gain Stage Gain=4C/C=4 Input voltage common-mode level removed opamp can have low input common-mode compliance Amplifier offset NOT removed Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 34

Differential T/H Including Offset Cancellation Operation during offset cancellation phase shown Auxilary inputs added with A main /A aux.=10 During offset cancellation phase: Aux. amp configured in unity-gain mode: Vout=V os main offset stored on C AZ & canceled Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930-938, December 1987. EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 35 Differential T/H Including Offset Cancellation Operational Amplifier Operational amplifier dual input folded-cascode opamp M3,4 auxiliary input, M1,2 main input To achieve 1/10 gain ratio W M3, 4 =1/10x W M1,2 & current sources are scaled by 1/10 M5,6,7 common-mode control Output stage dual cascode high DC gain V out =g m1,2 r o V in1 + g m3,4 r o V in2 Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930-938, December 1987. EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 36

Differential T/H Including Offset Cancellation Phase + - (V INAZ+ -V INAZ- )= -g m1,2 /g m3,4 V offset V offset During offset cancellation phase AZ and S1 closed main amplifier offset amplified by g m1 /g m2 & stored on C AZ Auxiliary amp chosen to have lower gain so that: Aux. amp charge injection associated with opening of switch AZ reduced by A aux /A main =1/10 Insignificant increase in power dissipation resulting from addition of aux. inputs Requires an extra auto-zero clock phase EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 37 V V CLK Track & Hold Aperture Time Error V CLK x V in +V TH V in M1 V O x V in C s x Time Transition from track to hold: Occurs when device turns fully off V CLK =V in +V TH Sharp fall-time wrt signal change no aperture error EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 38

V x V CLK x x Track & Hold Aperture Time Error V in +V TH V in Time Slow falling clock aperture error V in =A sin(2π f in t) ε= f in xax t fall /V CLK SDR= - 20logε -4[dB] (imperical see Ref.) Example: Nyquist rate 10-bit ADC & A=V CLK /4 SQNR=62dB for distortion due to aperture error < quant noise t fall < 2x10-3 /f in Worst case: f in = f s /2 t fall < 4x10-3 /f s e.g. f s =100MHz, t fall <40psec Ref: P. J. Lim and B. A. Wooley, "A high-speed sample-and-hold technique using a Miller hold capacitance," IEEE Journal of Solid-State Circuits, vol. 26, pp. 643-651, April 1991. EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 39 Track & Hold Aperture Time Error Aperture error analysis applies to simple sampling network Bottom plate sampling minimizes aperture error Boosted clock reduces aperture error Clock edge fall/rise trade-off between switch charge injection versus aperture error Ref: P. J. Lim and B. A. Wooley, "A high-speed sample-and-hold technique using a Miller hold capacitance," IEEE Journal of Solid-State Circuits, vol. 26, pp. 643-651, April 1991. EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 40

Effect of Clock Jitter So far assumption was that the clock signal controlling the sampling instants has no variability and have their edges spaced exactly T amount In practice the clock edges are not prefectly spaced and have some level of jitter Variability in T causes errors in data converter performance "Aperture Uncertainty" or "Aperture Jitter Question: for a given application how much clock jitter can be tolerated? EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 41 Clock Jitter Sampling jitter adds an error voltage proportional to the product of (t J -t 0 ) and the derivative of the input signal at the sampling instant x(t) x (t 0 ) actual sampling time t J Jitter doesn t matter when sampling dc signals (x (t 0 )=0) nominal (ideal) sampling time t 0 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 42

Clock Jitter The error voltage is e = x (t 0 )(t J t 0 ) x(t) x (t 0 ) actual sampling time t J error nominal sampling time t 0 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 43 Sinusoidal input Amplitude: Frequency: Jitter: max x x x Jitter Example A f x dt ( π x ) ( π ) x( t ) = Asin 2 f t x'(t) = 2π f Acos 2 f t x'(t ) 2π f A Requirement: e( t ) x' ( t ) d t e( t ) 2π f A d t x # of Bits 16 12 10 Worst case A= AFS f fs x = 2 2 Δ AFS e( t ) << B+ 1 2 2 1 dt << B 2 π f s f s 10 MHz 100 MHz 1000 MHz dt << 0.5 ps 0.8 ps 0.3 ps EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 44

Law of Jitter The worst case looks pretty stringent what about the average? Let s calculate the mean squared jitter error (variance) If we re sampling a sinusoidal signal x(t) = Asin(2πf x t), then x (t) = 2πf x Acos(2πf x t) E{[x (t)] 2 } = 2π 2 f x2 A 2 Assume the jitter has variance E{(t J -t 0 ) 2 } = τ 2 EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 45 Law of Jitter If x (t) and the jitter are independent E{[x (t)(t J -t 0 )] 2 }= E{[x (t)] 2 } E{(t J -t 0 ) 2 } Hence, the jitter error power is E{e 2 } = 2π 2 f x2 A 2 τ 2 If the jitter is uncorrelated from sample to sample, this jitter noise is white EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 46

Law of Jitter DR jitter 2 A / 2 = 2 2 2 2 2π f A τ x 1 = 2 2 2 2π f τ x = 20log 10 ( 2πf τ ) x Example: ENOB=12bit f in =35MHz τ<1ps rms! EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 47 More on Jitter The first requirement is to have a good enough clock generator Clock signal should be handled carefully on-chip to prevent additional excessive jitter Usually, clock jitter in the single-digit pico-second range can be prevented by appropriate design techniques: Separate supplies Separate analog and digital clocks Short inverter chains between clock source and destination Few, if any, other analog-to-digital conversion non-idealities have the same symptoms as sampling jitter: RMS noise proportional to input frequency RMS noise proportional to input amplitude In cases where clock jitter limits the dynamic range, it s easy to tell, but may be difficult to fix... EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 48

ADC Architecture & Design EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 49 ADC Architectures Slope type converters Successive approximation Flash Time-interleaved / parallel converter Folding Residue type ADCs Two-step Pipeline Oversampled ADCs EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 50

Various ADC Architectures Resolution/Conversion Rate Resolution Oversampled & Serial Algorithmic e.g. Succ. Approx. Subranging e.g. Pipelined Folding & Interpolative Parallel & Time Interleaved Conversion Rate EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 51 Serial ADC Single Slope V Ramp Ramp Generator V Ramp V IN "0" stop start B 1..B N.. Counter Clock Time Counter starts counting @ V Ramp =0 Counter stops counting for V IN =V Ramp Counter output proportional to V IN EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 52

Single Slope ADC Advantages: Low complexity & simple INL depends on ramp linearity & not component matching Inherently monotonic Disadvantages: Slow (2 N clock pulses for N-bit conversion) Hard to generate precise ramp Need to calibrate ramp slope versus V IN Better: Dual Slope, Multi-Slope EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 53 Serial ADC Dual Slope V IN V "0" Integrator o B 1..B N.. Counter -V REF Clock Flip Flop First: V IN is integrated for a fixed time (2 N xt CLK ) V o = 2 N xt CLK V IN /τ intg Next: V o is de-integrated with V REF until V o =0 Counter output = 2 N V IN /V REF EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 54

Dual Slope ADC Slope α V IN Slope = Const. http://www.maxim-ic.com/appnotes.cfm/appnote_number/1041 Integrate V in for fixed time (T INT ), de-integrate with V REF applied T De-Int ~ 2 Nx T CLK xv in /V REF Most laboratory DVMs use this type of ADC EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 55 Dual Slope ADC Advantage: Accuracy to 1st order independent of integrator time-constant and clock period Comparator offset referred to input is attenuated by integrator high DC gain Insensitive to most linear error sources DNL is a function of clock jitter Power supply (60Hz) xtalk effect on reading can be canceled by: choosing conversion time multiple of 1/60Hz High accuracy achievable (16+bit) Disadvantage: Slow (maximum 2x2 N xt clk per conversion) Integrator opamp offset results in ADC offset (can cancel) Finite opamp gain gives rise to INL EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 56

Successive Approximation ADC SAR Algorithmic type ADC Based on binary search over DAC output Reset DAC Set DAC[MSB]=1 V IN T/H 1 MSB Y V IN >V DAC? N 0 MSB V REF DAC Set DAC[MSB-1]=1 Control Logic Clock 1 [MSB-1] 1 [LSB] Y Y V IN >V DAC?. V IN >V DAC? N 0 [MSB-1] N 0 [LSB] DAC[Input]= ADC[Output] EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 57 Successive Approximation ADC Example: 6-bit ADC & V IN =5/8V REF V IN T/H V REF Control Logic Clock DAC + - 1 3/4 5/8 1/2 V DAC /V REF 1/2 3/4 5/8 11/16 21/32 41/64 V IN DAC Output Test MSB Test MSB-1 ADC 101000 Time / Clock Ticks High accuracy achievable (16+ Bits) Required N clock cycles for N-bit conversion (much faster than slope type) Moderate speed proportional to N (typically MHz range) EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 58

Example: SAR ADC Charge Redistribution Type S top Comparator 32C 16C 8C 4C 2C C C - Out b 4 (msb) b 3 b 3 b 2 b 1 b 0 V in Control Logic To switches V REF V in T/H inherent in DAC Operation starts by connecting all top plate to gnd and all bottom plates to Vin To test the MSB all top plate are opened bottom plate of 32C connected to V REF & rest of bottom plates connected to ground input to comparator= -V in +V REF /2 Comparator is strobed to determine the polarity of input signal if - MSB=1 if + MSB=0 The process continues until all bits are determined EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 59 Example: SAR ADC Charge Redistribution Type reset C P -Comparator 32C 16C 8C 4C 2C C C Out b 4 (msb) b 3 b 3 b 2 b 1 b 0 V in Control Logic To switches V REF V in To 1 st order parasitic (C p ) insensitive since top plate driven from initial 0 to final 0 by the global negative feedback Linearity is a function of accuracy of C ratios Possible to add a C ratio calibration cycle (see Ref.) Ref: H. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 15 bit CMOS A/D converter," IEEE Journal of Solid-State Circuits, vol. 19, pp. 813-819, December 1984. EECS 247 Lecture19: Nyquist Rate ADC: Track & Hold 2007 H.K. Page 60