S.E. Sem. III [ETRX] Digital ircuit Design Time : 3 Hrs.] Prelim Paper Solution [Marks : 80. Solve following : [20].(a) Explain characteristics of logic families. [5] haracteristics of logic families are as follows :. Voltage and current parameters 2. Speed of operation 3. Power dissipation 4. Figure of merit 5. Fan-out 6. Noise immunity 7. Operating temperature range 8. Power supply requirements 9. Flexibilities available Speed of Operation : The speed of a digital circuit is specified in terms of the propagation delay time. The delay times are measured between the 50 percent voltage levels of input and output waveforms. The propagation delay time of the logic gate is taken as the average of the two delay times. Input Output 50% 50% Power Dissipation : It is the amount of power dissipated in an I. It is determined by the current, I, that it draws from the V supply and is given by V I. Fan-Out : This is the number of similar gates which can be driven by a gate. High fanout is advantageous because it reduces the need for additional drivers to drive more gates..(b) State and Prove Demorgan Theorem. [5] De-Morgan s Theorem : This theorem states that the complement of a product is equal to addition of the complements. Theorem : A. A, NAND = ubbled OR A A. A A 0 0 0 0 0 0 0 0 0 0 LHS = A. = A = RHS t phl t plh Fig.: Input and output voltage waveforms to define propagation delay times.
: S.E. DM Theorem 2 : A = A., NOR = ubbled AND A A A A. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LHS = A = A. = RHS.(c) onvert JK flip flop to T flip flop. [5] For J : For K : n + J K T T 0 T 0 0 0 0 X 0 n n 0 X 0 0 0 X X 0 X X X 0 X 0 0 J = T K = T T LK onversion logic J K T Flip-Flop.(d) onvert the following numbers as mentioned against them: (I) () 2 convert to decimal number. (II) onvert (29.625) 0 Hexadecimal form. (III) Write ( 20) 0 in Two s complement form. (i) () 2 convert to decimal number 0 0 2 5 2 4 2 3 2 2 2 2 0 = 32 + 8 + 2 + = 43 () 2 = (43) 0 (ii) onvert (29.625) 0 Hexadecimal form : 6 29 0.625 6 = 0 6 8 8 0 (29.625) 0 =(8.A) 6 Output T n 0 0 0 X X J = T T n 0 0 X 0 X K = T [5] 2
(iii) Write ( 20) 0 in Two s complement for m 2 20 0 2 0 0 2 5 2 2 0 2 0.2(a) Minimize the following expression using uine Mcluskey technique : F(A,,,D) = (0,,2,3,5,7,9,) Step : Minterm inary representation 0 0 0 0 0 0 0 0 2 0 0 0 3 0 0 5 0 0 9 0 0 0 7 0 Prelim uestion Paper Step 2 : Grouping as per no. of s Minterm inary representation 0 0 0 0 0 0, 0 0 0 0 0 0 0,2 0 0 0 2 0 0 0 3, 0 0 3 0 0,5 0 0 5 0 0,9 0 0 9 0 0 2,3 0 0 0 3, 0 7 0 9, 0 3,7 0 5,7 0 Minterm inary representation Minterm inary representation 0,,2,3 0 0 0,,2,3 0 0 0,2,3, 0 0,3,9, 0,3,9, 0,3,5,7 0,9,3, 0,3,5,7 0 Prime inary Representation implicants A D 0,,2,3 0 0,3,9, 0,3,5,7 0 (20) 0 = 0 = ( ) 2 s (0) 2 s ( 20) = 0 [0] 3
: S.E. DM Minterm Group m 0 m m 2 m 3 m 5 m 9 m m 7 0,,2,3,3,9,,3,5,7 (,5,9,) (0,,2,3) (,3,5,7) Y = 0 + 0 0 + 0 Y = AD + D + A.2(b) Draw four bit Ring counter and explain its operation. [0].3(a) Sequence Table After clock 2 3 4 pulse 0 0 0 0 0 0 0 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0 6 0 0 0 7 2 3 4 LK D FF D 2 FF 2 2 2 D 3 The FFS are arranged such that output of each stage is connected to the D input of next stage, but the output of the last flip flop is connected back to the D input of first FF such that array of FF is arranged in a ring. Initially the first FF is preset to a, so the initial state is 0. After each clock pulse the contents of the shift register are shifted to the right by one bit & 4 is shifted to. The Sequence repeats after 4 clock pulses. Explain the Johnson s ounter. Design for initial state. From initial state [0] explain and draw all possible states. In a Johnson counter, the output of each stage of flip-flop is connected to the D input of the next stage. FF 3 3 3 D 4 FF 4 4 State Diagram 0 0 0 0 4
Prelim uestion Paper D A (A) () () (D) D D D D D LK Decimal Number lock Pulse D 6 0 0 0 0 5 2 0 0 2 3 0 0 0 9 4 0 0 4 5 0 0 0 0 6 0 0 3 7 0 Initially, the register is kept at state (initial state). So all the outputs,,, D consist of specified output at initial state. Therefore, complement output of last stage, D is one as the output of D at initial state is zero. This is connected back to first stage (D A ). Hence, D A is one. Timing Diagram : lk An n-stage Johnson counter will produced a modulus of 2 n, where n is the number of stages (i.e. flip-flops) in the counter..3(b) Implement the following function using only one 4: multiplexer and gates : Y = F(A,,,D) = m (2, 3, 5, 7, 0,, 2, 3) D 0 D D 2 D 3 DA 0 = A 2 3 4 5 Four bit Johnson ounter 2 3 4 5 6 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A 0 2 3 A 4 5 6 7 A 8 9 0 D [0] 5
: S.E. DM D = A A = (A + A ) = D 2 = A A = ( A + A) = D 3 = A A A = A + A = A +.4(a) Design a 2 bit comparator and implement using logic gates. [0] Input Truth table: A Input Output A A 0 0 A < A = A > n-bit comparator 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A > A = A < 0 0 0 0 0 0 0 0 0 Output 0 0 0 0 K-map for A < : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 K-map for A = : A D 0 D D 2 D 3 4 : S S 0 MUX D Y 6
Prelim uestion Paper K-map for A > Implementation : A A A A A A A A f(a,,,d) Output A > A < 7
: S.E. DM.4(b) Draw circuit diagram of 2 input TTL NAND gate and explain its operation. [0] V A I (4K R I I 2 T T 2 2 R 2.4K R E2 (K ) Assume load gates are not present & the voltages for logic 0 & are V E = 0.2V & V = 5V I G3 3 3 ondition (Atleast one input is LOW) : The E junction of T corresponding to the input in the LOW state is forward biased making voltage at V = 0.2 + 0.7 = 0.9V. For junction of T to be forward biased & for T 2 & T 3 to be conducting V 0 required to be at least 0.6 + 0.5 + 0.5 =.6 V. Hence T 2 & T 3 are OFF. Y = V ondition 2 (All inputs are HIGH) :.E junction of T is reverse biased. If we assume T 2 & T 3 are ON then V 2 = V = 0.8 + 0.8 =.6V. Since is connected to V (5V) through R, junction of T is forward biased. The transistor T is operating in active inverse mode, making I flow in the reverse direction. This current flows in the base of T 2 & T 3 into saturation. Y = 0.2 V ondition 3 : Let the circuit be operating under condition 2, when one of the inputs suddenly goes to V(0). The corresponding E junction of T starts conducting & V drops to 0.9V T 2 & T 3 will be turned off when the stored charge is removed since V = V 2 =.6V, - junction of T is back biased, making T operate in the normal active mode. This large current of T is in a direction which helps in the removal of stored base charge in T 2 & T 3 & improves speed of the circuit. T 3 R 3 (4K ) I 3 Y 8
Prelim uestion Paper.5(a) Design D Adder using the integrated circuit 4 bit binary adders. [0] S S 0 out 0 0 S 3 S 2 ombination circuit Addr S 3 S 2 S S 0 Y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4-bit binary adder S 3 S 2 S 4-bit binary adder S 3 S 2 S S 0 S 0 (correct D answer) Output arry Adder Adder 2 Sum is valid D number Y = 0 Y out ) Sum 9, arry = 0 S 3 S 2 S S 0 If sum is less than or equal to 9 and carry is zero then there is no need to add to get D number as it is already valid D number. 2) Sum > 9, arry = 0 If sum is greater than 9 than it is invalid D number hence (6) is added to sum to get valid D number. 3) Sum 9, arry = If sum is less than 9 but carry is that means the D number is more than 9 hence (6) is added to it. 3 3 2 2 0 0 0 A 3 0 4 2 8 5 3 9 3 4-bit binary adder 0 S 3 A 2 7 2 6 S 3 S 2 S S 0 Y 0 0 0 0 0 0 0 Y = S 3 S 2 + S 3 S Equation for combinational circuit S 2 4-bit binary adder A S A 0 S 0 5 4 Adder Adder 2 0 Sum is invalid D number Y = 9
: S.E. DM.5(b) Design lockout free mod 0 up synchronous counter using JKMS flip flops. [0] Step : No. of FFS : N 2 n 0 2 n n = 4 Step 2: State diagram 0 2 3 4 0 0 0 0 0 9 8 7 6 5 Excitation table for ircuit excitation table : J K flip flop Present State Next State Flip Flop inputs Present Next D D+ + + + J D K D J K J K J A K A State state J K 0 0 0 0 0 0 0 0 X 0 X 0 X X n+ 0 0 0 0 0 0 0 X 0 X X X 0 0 0 X 0 0 0 0 0 0 X 0 X X 0 X 0 X 0 0 0 0 0 0 X X X X 0 X 0 0 0 0 0 0 X X 0 0 X X X 0 0 0 0 0 0 X X 0 X X 0 0 0 0 X X 0 X 0 X 0 0 0 X X X X 0 0 0 0 0 X 0 0 X 0 X X 0 0 0 0 0 0 X 0 X 0 X X 0 0 0 0 0 0 X 0 X X 0 X 0 0 0 0 0 X 0 X X X 0 0 0 0 0 0 X X 0 X 0 X 0 0 0 0 0 X X 0 X X 0 0 0 0 0 X X X 0 X 0 0 0 0 X X X X K-maps : For JD D 0 0 0 0 0 0 0 0 0 0 0 J D = 0 3 2 2 3 5 4 8 9 0 c s n For KD 0 0 x x * x 0 0 0 3 2 2 3 5 4 0 * 8 9 0 K D = + + 0
Prelim uestion Paper D For J For K D 0 0 D 0 0 0 x x x x 0 D D 0 0 J = + 0 0 0 0 For J 0 0 0 0 0 0 x x 0 0 x x 0 0 x x J = D A 0 3 2 2 3 5 4 8 9 0 0 3 2 2 3 5 4 8 9 0 For JA 0 0 x x 0 3 2 x x 0 x x 0 2 3 5 4 x x 0 8 9 0 D 0 0 0 0 0 0 For K 0 0 D 0 3 2 0 0 0 2 3 5 4 8 9 0 K = + + D 0 3 2 x x 0 x x 2 3 5 4 x x 8 9 0 K = D + For KA D 0 0 x x x J A = K A = D D 0 3 2 x x x X 2 3 5 4 X X 8 9 0
: S.E. DM Logic ircuit : D LK J D K D D D D.6 Write short notes on following : [20].6(a) Write short note on Hazards. [5] Hazards : The electronic components used have associated propagation delays because of which the changes in response of a circuit do not occur instantaneously with the changes in the input. This may result in an unwanted phenomena known as Hazard. Detection of Hazard : The hazard in a digital circuit is detected b using K-map of the circuit : A 0 0 Y A 0 2 Y 2 J K t and t 2 are the propagation delays of paths through AND gate and 2 respectively. Types of Hazards : In case of hazard occurring in SOP form of realization the output goes to 0 momentarily when it should have remained, and in POS form its vice versa. The first type refers to static- hazard and second type refers to static-0 hazard. A third type of hazard, known as dynamic hazard, causes the output to change number of times when it should change from to 0 or from 0 to..6(b) Write short note on Hamming ode. [5] Hamming ode : Hamming code is an error-correcting code. It is constructed by adding a number of parity bits to each group of n-bit information or message in such a way so as to be able to locate the bit position in which error occurs. Let us assume K parity bits P, P 2, P k are added to the n-bit message to form an (n + k) bit code. 2 k n + k + The location of each of the n + k bits within a code word is assigned a decimal number, starting from to the MS and n + k to the LS. K parity checks are performed on selected bits of each code word. Each parity check includes one of the parity bits. The result of D J K Logic circuit Y J K logic 2
Prelim uestion Paper each parity check is recorded as if error has been detected and as 0 if no error has been detected. The parity bits P, P 2, P k are placed in locations, 2, 4, 2 k. 2 3 4 5 6 7 8 9 0 2 3 4 5 6 P P 2 D 0 P 3 D D 2 D 3 P 4 D 4 D 5 D 6 D 7 D 8 D 9 D 0 P 5.6(c) Write short note on Encoder and Decoder. [5] Encoder : An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n input lines and n output lines. In encoder the output lines generate the binary code corresponding to the input value. In encoders it is assumed that only one input has a value of at any given time, otherwise the circuit is meaningless. A A Decoder : A decoder is a combinational circuit that D converts binary information from n input lines to a 0 = A maximum of 2 n unique output lines. Here, 2 inputs are decoded into four output each output representating one of the minterms of the 2 inputs variables..6(d) ompare TTL and MOS logic families. [5] Parameter MOS TTL Silicon gate Metal gate 74 7425 74AS 74A25 MOS MOS V H(min) 3.5 3.5 2.0 2.0 2.0 2.0 V L(max).0.5 0.8 0.8 0.8 0.8 V 0H(min) 4.9 4.95 2.4 2.7 2.7 2.7 V 0L(max) 0. 0.05 0.4 0.5 0.5 0.4 V NH.4.45 0.4 0.5 0.7 0.7 V NL 0.9.45 0.4 0.3 0.3 0.4 Propagation delay 8 05 0 0.5 4 Power per gate (mv) 0.7 0. 0 2 8.5 Speed power.4 pj 0.5 pj pj 20 pj 2.8 pj 4 pj Product or Input cannot be left open. Input can be left open. It is treated figure of merit It has to be connected to O or to as logic high input. in connection V DD or to another input Power dissipation Very less More than MOS Fan-out Fan-out is more than TTL(50) Fan-out for TTL is 0 Noise More susceptible to noise Less susceptible to noise D = A D 2 = A D 3 = A 3