Lecture 12 Logistics HW was due yesterday HW5 was out yesterday (due next Wednesday) Feedback: thank you! Things to work on: ig picture, ook chapters, Exam comments Last lecture dders Today Clarification of dders Summary of Combinational Logic Introduction to Sequential Logic The basic concepts simple example 1 dders allow computers to add numbers 2-bit ripple-carry adder 32 1-it dder Sum 33 0 1 1 C in C out 2 2 C in C out C in ND2 11 ND2 OR3 12 1 Cout C out Sum 1 Sum 2 ND2 13 Sum CSE370, Lecture 13 11 12 Overflow 2
Problem: Ripple-carry delay Carry propagation limits adder speed (we want to add fast) 32 0 @2N 33 Sum @2N+1 0 S0 @2 C1 @2 @2N ND2 11 1 1 S1 C2 @2N ND2 OR3 12 1 @2N+2 2 Cout 2 2 S2 @5 C3 @6 ND2 13 CSE370, Lecture 13 11 12 C out takes two gate delays C in arrives late 3 3 S3 @7 Cout @8 3 One Solution: Carry lookahead logic Get Pi (propagate) and Gi (generate) @2N @2N 32 ND2 11 Pi @1 ND2 OR3 @2N 12 1 ND2 13 33 Sum @2N+1 @2N+2 Cout @2 0 0 P0 G0 1 1 2 2 S0 @2 C1 @2 P1 G1 Gi C 2 = G 1 + P 1 C 1 = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 C = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 1 = G 0 + P 0 C 0 0 C = G 3 + P 3 C 3 S1 C2 P2 G2 3 3 S2 @5 C3 @6 P3 G3 S3 @7 C@8 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0
Cascaded carry-lookahead adder (in your HW5) four-bit adders with internal carry lookahead Second level lookahead extends adder to 16 bits [15-12] [15-12] -bit dder P G C12 [11-8] [11-8] -bit dder P G C8 [7-] [7-] -bit dder P G C [3-0] [3-0] -bit dder P G C0 S[15-12] @8 @2 @5 S[11-8] @8 @2 @5 S[7-] @7 @2 S[3-0] @2 P3 G3 C3 P2 G2 C2 P1 G1 C1 P0 G0 C16 @5 C Lookahead Carry Unit C0 C0 P3-0 G3-0 @5 CSE370, Lecture 13 11 12 5 nother solution: Carry-select adder Redundant hardware speeds carry calculation Compute two high-order sums while waiting for carry-in (C) Select correct high-order sum after receiving C C8 C8 -bit adder [7:] -bit adder [7:] 0 1 adder low adder high I 0S I 1 Z @6 five 2:1 muxes 1 0 1 0 1 0 1 0 1 0 C -it dder [3:0] C0 @5 C8 S7 S6 S5 S S3 S2 S1 S0 @6 CSE370, Lecture 13 11 12 6
We've finished combinational logic... What you should know Twos complement arithmetic Truth tables asic logic gates Schematic diagrams Timing diagrams Minterm and maxterm expansions (canonical, minimized) de Morgan's theorem ND/OR to NND/NOR logic conversion K-maps, logic minimization, don't cares Multiplexers/demultiplexers PLs/PLs ROMs dders CSE370, Lecture 13 11 12 We had no way to store memory: When the input changed, the output changed Next: Sequential logic can store memory 7 Sequential Logic (next 5 weeks!) We learn the details Latches, flip-flops, registers (storage) Shift registers, counters (we can count now!) State machines Timing and timing diagrams timing more important than combinational logic Synchronous and asynchronous inputs Metastability (problem!) Moore and Mealy machines (types of state machines) More... 8
Sequential versus combinational C pply fixed inputs, Wait for edge Observe C Wait for another edge Observe C again Combinational: C will stay the same Sequential: C may be different 9 Sequential versus combinational (again) Combinational systems are memoryless Outputs depend only on the present inputs Inputs System Outputs Sequential systems have memory Outputs depend on the present and the previous inputs Inputs System Outputs Feedback 10
Synchronous sequential systems Memory holds a system s state Changes in state occur at specific times periodic signal times or s the state changes The period is the time between state changes C State changes occur at rising edge of pulsewidth period duty cycle = pulsewidth/period (here it is 50%) 11 Steady-state abstraction Outputs retain their settled values The period must be long enough for all voltages to settle to a steady state before the next state change C Clock hides transient behavior C Settled value 12
What did I just say about sequential logic? Has Synchronous = ed Exception: synchronous Has state State = memory Employs feedback ssumes steady-state signals Signals are valid after they have settled State elements hold their settled output values 13 Example: sequential system Door combination lock Enter 3 numbers in sequence and the door opens If there is an error the lock must be reset fter the door opens the lock must be reset Inputs: Sequence of numbers, reset Outputs: Door open/close Memory: Must remember the combination CSE370, Lecture 1312 1
Understand the problem Consider I/O and unknowns How many bits per input? How many inputs in sequence? How do we know a new input is entered? How do we represent the system states? new value reset open/ 15 Implement using sequential logic ehavior Clock tells us when to look at inputs fter inputs have settled Sequential: Enter sequence of numbers Sequential: Remember if error occurred Need a finite-state diagram ssume synchronous inputs State sequence Enter 3 numbers serially Remember if error occurred ll states have outputs Lock open or new value reset open/ 16
Finite-state diagram States: 5 Each state has outputs Outputs: t open/ Inputs: reset, new, results of comparisons ssume synchronous inputs We use state diagrams to represent sequential logic System transitions between finite numbers of states reset ERR C1!= value C2!= value C3!= value &new S1 S2 S3 OPEN C1== value C2== value C3== value open 17 Separate data path and control Data path Stores combination Compares inputs with combination Control Finite state-machine controller Control for data path State changes ed value C1 C2 C3 multiplexer comparator mux control equal new controller reset open/ 18
Refine diagram; generate state table Refine state diagram to include internal structure reset ERR not equal not equal not equal S1 S2 S3 OPEN mux=c1 equal mux=c2 equal mux=c3 equal open Generate state table next reset new equal state state mux open/ 1 S1 C1 0 0 S1 S1 C1 0 1 0 S1 ERR 0 1 1 S1 S2 C2... 0 1 1 S3 OPEN open... 19