Spring 04 S. Hoyos - EEN-60 ELEN 60 Data onverters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group
Spring 04 S. Hoyos - EEN-60 Electronic Noise Signal to Noise ratio SNR Signal Power Psignal ~ DD Noise Power Pnoise=kT/ SNR = Psignal / Pnoise Technology Scaling DD goes down goes up Power goes up Noise is critical in low power design
Spring 04 S. Hoyos - EEN-60 3 Thermal Noise Brownian Motion : Thermal agitation of particles Stochastic Process: Statistical model Noise Power : P N ktδf k=.3806503 0-3 J/K Noise power in bandwidth Δf deliver to a matched load For Δf= Hz P N =4*0 - W (or - 74 dbm ) (@T=90K) Reference: J.B Johnson : Thermal agitation of electrons in conductors July 98
Spring 04 S. Hoyos - EEN-60 4 Thermal Noise R en R P N ktδf en 4 R e n 4kTRΔf e n 4 n / Room temperature, R=KΩ rms spectral density Room temperature, R=50Ω rms spectral density e n 0. 9n / Hz Hz in R e R n in 4 ktδf R 4 ktgδf
Spring 04 S. Hoyos - EEN-60 5 Noise Bandwidth Δf H pk 0 H(f) df H pk is the peak value of the magnitude of the filter voltage transfer function H(f) For a single-pole R low-pass filter Δf π df f 0 db πfr 3 4 R.57 times the -3 db bandwidth HW: Find the noise bandwidth for critically damped second-order low-pass filter.
Noise in S ircuits Spring 04 S. Hoyos - EEN-60 6
Spring 04 S. Hoyos - EEN-60 7 Noise of T Integrator H (f) R R i o N o N H (f) on N f H f df f H f df N Output noise can be simulated with SPIE.
Spring 04 S. Hoyos - EEN-60 8 Noise of S Integrator i o S circuits are NOT noise-free! Switches and op amps introduce noise.
Spring 04 S. Hoyos - EEN-60 9 Sampling ( ) KT/ Noise N i R N R N H f f f 0 0 kt N 4kTR N 4kTR jf R df R df Noise indistinguishable from signal after sampling.
Integration ( ) H 34 (f) N3 N4 R 4 o R 3 N5 H 5 (f) N H f df f H f df f f N 3 N 4 34 N 5 5 on N N What techniques you know to simulate the aggregated output noise? K. Kundert, "Simulating switched-capacitor filters with SpectreRF," available at http://www.designers-guide.org/analysis/sc-filters.pdf. Spring 04 S. Hoyos - EEN-60 0
Spring 04 S. Hoyos - EEN-60 Sampling ( ) Noise Revisited N3 N4 R 4 N R ' N R 3 N5 R All switches and op amp contribute noise simultaneously. Finite op-amp BW and R time constant tend to limit the noise bandwidth, resulting in less overall KT/ noise (noise filtering). Output and load resistors also add noise.
Spring 04 S. Hoyos - EEN-60 Sampled Noise Spectrum T PSD 0 f s f s DT PSD Alias 0 f s / f s 3/f s Total integrated noise power remains constant. SNR remains constant.
Spring 04 S. Hoyos - EEN-60 3 harge-sampling Noise HW: Show that the total integrated noise for the charge sampling circuit is given by: N N T T kt s kt s G m s Δt for for Δt s Δt G m G s m
MOSFET- Active Filters Spring 04 S. Hoyos - EEN-60 4
Spring 04 S. Hoyos - EEN-60 5 MOSFET Resistor GS G S D I DS DS = GS - th GS S D 0 DS MOSFET in triode region is a variable resistor. ompact, small parasitics compared to passive resistors.
Spring 04 S. Hoyos - EEN-60 6 MOSFET Resistor In triode region, I DS ox W L GS th DS DS Small signal, R DS I DS DS ox W L ox for 0. GS W L th GS th DS DS But the large-signal response is quite nonlinear.
Spring 04 S. Hoyos - EEN-60 7 A Linear MOSFET Resistor MOSFET resistor is linear when driven by balanced differential signals!. i ic th G ox i i i ic th G ox th G ox DS DS th GS ox DS L W L W L W L W I In triode region, G, i ic i ic
Spring 04 S. Hoyos - EEN-60 8 MOSFET- Integrator M i+ o+ i- o- M = i+ o- i- o+ Sources of M and M are always equal-potential due to virtual ground. The linearity is not surprising as the fully-differential circuit rejects the ndorder harmonic (also all even-order distortions). Triode resistance strongly depends on process (threshold, mobility, etc.), temperature, and DD. Filter response needs to be tuned.
Spring 04 S. Hoyos - EEN-60 9 G m - Active Integrator I G m i i I T i i o G s o m i Differential input with programmable gain constant G m /.
Spring 04 S. Hoyos - EEN-60 0 Nonideal Effects in S ircuits
Spring 04 S. Hoyos - EEN-60 Nonzero On-Resistance GS R on PMOS NMOS out S Tp Tn S R MOS 0 out DD on ox W L DD th out FET channel resistance depends on signal level. Usually (R on S ) - (3-5) ω -3dB for settling purpose.
Spring 04 S. Hoyos - EEN-60 lock Bootstrapping S DD In M Out MOS Bootstrapped NMOS Small on-resistance leads to large switches, which have large parasitics and need large clock buffers. lock bootstrapping keeps GS of the switch constant, thus constant onresistance; also less parasitics w/o the PMOS.
Simplified lock Bootstrapper DD In M Out DD M Better linearity for S/H. Device reliability. M Out omplexity. In SS Ref: A. M. Abo and P. R. Gray, "A.5-, 0-bit, 4.3-MS/s MOS pipeline AD," IEEE Journal of Solid-State ircuits, vol. 34, pp. 599-606, issue 5, 999. Spring 04 S. Hoyos - EEN-60 3
Spring 04 S. Hoyos - EEN-60 4 Switch-Induced Errors Z i gs gd out lock feedthrough in Q ch S harge injection hannel charge injection and clock feedthrough (on the drain side) result in charge trapped on S after switch is turned off.
Spring 04 S. Hoyos - EEN-60 5 lock Feedthrough and harge Injection Z i gs gd out DD 0 in + th in Q ch S Switch on Switch off Both phenomena are sensitive functions of Z i, S, and clock SR. Nonlinear signal-dependent errors introduce distortion. lock feedthrough can be simulated. harge injection cannot be simulated with lumped transistor models.
lock SR Dependence Z i gs gd out DD 0 in + th in Q ch S Switch on Switch off Fast turn-off Slow turn-off lock feedthrough gs gs gs S S DD harge injection Spring 04 S. Hoyos - EEN-60 6 ox WL gs in th 0 DD gs th S in
Spring 04 S. Hoyos - EEN-60 7 Switch Size Optimization To minimize switch-induced error voltages, small transistor size, slow turn-off, low source impedance should be used. Always use minimum channel length for switches. For fast settling (high-speed design), large (W/L) should be used, which implies that the error voltages tend to be large also. For a given speed, switch sizes can be optimized through simulation. minimum size transistors should be used to meet the speed spec. Be aware of the limitations of the simulator (SPIE etc.) that uses lumped device models.
Spring 04 S. Hoyos - EEN-60 8 Dummy Switch in W L W L S out The nonlinear dependence of Δ on Z i, S, and clock SR makes it difficult to achieve a precise cancellation. Sensitive to phase alignment between and _.
Spring 04 S. Hoyos - EEN-60 9 MOS Switch in S out Same size for P and N FETs ery sensitive to phase alignment between and _. Subject to threshold mismatch between PMOS and NMOS. Exact cancellation occurs only for one specific in.
Spring 04 S. Hoyos - EEN-60 30 Differential Signaling ip M op Sp Balanced diff. input in M on Sn Signal-independent errors will be cancelled. Even-order distortions will be cancelled.
Leakage Spring 04 S. Hoyos - EEN-60 3
Spring 04 S. Hoyos - EEN-60 3 Junction Leakage I o (t) S i o i leak 0 t Reverse-biased D/S leakage at summing node introduces charge loss. Leakage current sets the lower limit of the clock frequency. More problematic with high temperature (leakage doubles every 0º) or short-channel switches.
Spring 04 S. Hoyos - EEN-60 33 Gate Leakage I GS WL exp t exp ox GS Direct tunneling through the thin gate oxide. Short-channel MOSFET behaves increasingly like BJT s. iolates the high-impedance assumption of the summing node. Gate + D/S leakage sets the lower limit of the clock frequency.
Spring 04 S. Hoyos - EEN-60 34 Nonideal Effects of Op-Amps
Spring 04 S. Hoyos - EEN-60 35 Offset oltage i o Q i n onos os Q os on os o (t) o z z z i z os 0 t i = 0
Spring 04 S. Hoyos - EEN-60 36 Autozeroing Q i nos os Q os onos i o os H z o i z z Also eliminates low-frequency noise, e.g., /f noise. Also called the correlated double sampling (DS).
Spring 04 S. Hoyos - EEN-60 37 hopper Stabilization n A B i A A o - f Ref: K.. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, "A low-noise chopper-stabilized differential switched-capacitor filtering technique," IEEE Journal of Solid-State ircuits, vol. 6, pp. 708-75, issue 6, 98.
Spring 04 S. Hoyos - EEN-60 38 hopper Stabilization i i n A A B A o 0 S N (f) f f - f 0 A f f Also eliminates D offset voltage of A. 0 B 0 f f f f
Spring 04 S. Hoyos - EEN-60 39 Implementation i+ o+ o- i- hopper-stabilized two-stage differential operational amplifier. Integrators can be built using these amplifiers.
Thermal Noise vs. Quantization Noise
Spring 04 S. Hoyos - EEN-60 4 Quantization ref A/D... b n b Analog input Digital output N bits used to quantize input signal.
Spring 04 S. Hoyos - EEN-60 4 Quantization Error D out FS 0 3 4 5 6 7 FS in D out FS N in 0, D LSB in FS out FS N in ε -3Δ -Δ -Δ 0 Δ N = 3 Δ 3Δ Δ/ 0 -Δ/ -3Δ -Δ -Δ 0 Δ Δ 3Δ in Random quantization error is regarded as noise.
Spring 04 S. Hoyos - EEN-60 43 Quantization Noise Δ/ 0 -Δ/ ε Δ Δ 3Δ 4Δ 5Δ 6Δ 7Δ FS in Assumptions: N is large. 0 in FS and in >> Δ. in is active. P ε ε is Uniformly distributed. /Δ Spectrum of ε is white. -Δ/ 0 Δ/ ε / / d Ref: W. R. Bennett, Spectra of quantized signals, Bell Syst. Tech. J., vol. 7, pp. 446-47, July 948.
Spring 04 S. Hoyos - EEN-60 44 Signal-to-Quantization Noise Ratio (SQNR) Assume in is sinusoidal with p-p = FS, SQNR FS N / 8 N.5, / 8 SQNR 6.0N.76dB. N (bits) SQNR (db) 8 49.9 0 6.0 74.0 4 86.0 SQNR depicts the theoretical performance of an ideal AD. In reality, AD performance is limited by many other factors: Electronic noise (thermal, /f, coupling, and etc.) Distortion (measured by THD, SFDR)
Spring 04 S. Hoyos - EEN-60 45 Thermal Noise Limited ircuit bit 6dB 4 x SNR 4 x SNR 4 x ircuit bandwidth ~gm/ Keeping gs constant 4 x gm 4xI D, 4x W Each additional bit quadruples power dissipation
Analog ircuit Dynamic Range Assume an analog signal: max, rms DD The noise rms values is: n, rms n f kt B The dynamic range in db is: DR max, rms DD 8n k T n, rms f B DD <3 DR<0dB <nf (8 bits) DD <30 DR<40dB <00nF (3 bits) DRdB 0 log0 DD 75 db with in pf n f Spring 04 S. Hoyos - EEN-60 46