Package TO Symbol Parameter Value Unit Test Conditions Note V GS = 20 V, T C = 25 C A 6 V GS = 20 V, T C = 100 C.
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1 V DS 1 V CM1D Silicon Carbide Power MOSFET CM TM MOSFET Technology N-Channel Enhancement Mode Features Package I 5 C R DS(on) 1 A mω High Blocking Voltage with Low On-Resistance High Speed Switching with Low Capacitances Easy to Parallel and Simple to Drive Avalanche Ruggedness Resistant to Latch-Up Halogen Free, RoHS Compliant Benefits TO-7-3 Higher System Efficiency Reduced Cooling Requirements Increased Power Density Increased System Switching Frequency Applications LED Lighting Power Supplies High Voltage DC/DC Converters Industrial Power Supplies HVAC Part Number CM1D Package TO-7-3 Maximum Ratings (T C = 5 C unless otherwise specified) Symbol Parameter Value Unit Test Conditions Note V DSmax Drain - Source Voltage 1 V V GS = V, I D = 1 μa V GSmax Gate - Source Voltage -1/+5 V Absolute maximum values V GSop Gate - Source Voltage -5/+ V Recommended operational values I D Continuous Drain Current 1 V GS = V, T C = 5 C A V GS = V, T C = 1 C Fig. 19 I D(pulse) Pulsed Drain Current A Pulse width t P limited by T jmax Fig. P D Power Dissipation.5 W T C =5 C, T J = 15 C Fig. T J, T stg Operating Junction and Storage Temperature -55 to +15 C T L Solder Temperature C 1. mm (.3 ) from case for 1s M d Mounting Torque 1. Nm lbf-in M3 or -3 screw 1 CM1D Rev. B, 1-15
2 Electrical Characteristics (T C = 5 C unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Test Conditions Note V (BR)DSS Drain-Source Breakdown Voltage 1 V V GS = V, I D = 1 μa V GS(th).. V V DS = V GS, I D = 1.5mA Gate Threshold Voltage Fig V V DS = V GS, I D = 1.5mA, T J = 15 C I DSS Zero Gate Voltage Drain Current 1 1 μa V DS = 1 V, V GS = V I GSS Gate-Source Leakage Current 5 na V GS = V, V DS = V R DS(on) g fs Drain-Source On-State Resistance 37 V GS = V, I D = A mω 53 V GS = V, I D = A, T J = 15 C Fig.,5,. V DS= V, I DS= A Transconductance. S V DS= V, I DS= A, T J = 15 C Fig. 7 C iss Input Capacitance 59 V GS = V C oss Output Capacitance 3 pf V DS = 1 V Fig. 17,1 C rss Reverse Transfer Capacitance 3 f = 1 MHz E oss C oss Stored Energy 1.5 μj VAC = 5 mv Fig 1 E AS Avalanche Energy, Single Pluse mj I D = A, V DD = 5V Fig. 9 E ON Turn-On Switching Energy 3 E OFF Turn Off Switching Energy 37 μj V DS = V, V GS = -5/ V, I D = A, R G(ext) =.5Ω, L= 1 μh Fig. 5 t d(on) Turn-On Delay Time 5. t r Rise Time 7. t d(off) Turn-Off Delay Time 1. t f Fall Time 9.9 ns V DD = V, V GS = -5/ V I D = A, R G(ext) =.5 Ω, R L = 133 Ω Timing relative to V DS Per IEC77-- pg 3 Fig. 7 R G(int) Internal Gate Resistance 11. Ω f = 1 MHz, V AC = 5 mv, ESR of C ISS Q gs Gate to Source Charge 5. Q gd Gate to Drain Charge 7. Q g Gate Charge Total. nc V DS = V, V GS = -5/ V I D = A Per IEC77-- pg 1 Fig. 1 Reverse Diode Characteristics Symbol Parameter Typ. Max. Unit Test Conditions Note V SD Diode Forward Voltage 3.3 V V GS = - 5 V, I SD = 3 A 3.1 V V GS = - 5 V, I SD = 3 A, T J = 15 C Fig., 9, 1 I S Continuous Diode Forward Current 1 A T C = 5 C Note 1 t rr Reverse Recovery time ns Q rr Reverse Recovery Charge 7 nc V GS = - 5 V, I SD = A, V R = V dif/dt = 1 A/µs Note 1 I rrm Peak Reverse Recovery Current A Note (1): When using SiC Body Diode the maximum recommended V GS = -5V Thermal Characteristics Symbol Parameter Typ. Max. Unit Test Conditions Note R θjc Thermal Resistance from Junction to Case 1.. R θjc Thermal Resistance from Junction to Ambient C/W Fig. 1 CM1D Rev. B, 1-15
3 Typical Performance T J = -55 C tp < µs V GS = 1 V V GS = V V GS = 1 V V GS = 1 V V GS = 1 V V GS = 1 V tp < µs V GS = 1 V V GS = 1 V V GS = V V GS = 1 V V GS = 1 V V GS = 1 V Figure 1. Output Characteristics T J = -55 C Figure. Output Characteristics T J = 15 C tp < µs V GS = V V GS = 1 V V GS = 1 V V GS = 1 V V GS = 1 V V GS = 1 V On Resistance, R DS On (P.U.) I DS = A V GS = V t p < µs Junction Temperature, T J ( C) Figure 3. Output Characteristics T J = 15 C Figure. Normalized On-Resistance vs. Temperature 7 V GS = V t p < µs 7 I DS = A t p < µs On Resistance, R DS On (mohms) T J = 15 C T J = -55 C On Resistance, R DS On (mohms) V GS = V V GS = 1 V V GS = 1 V V GS = 1 V Figure 5. On-Resistance vs. Drain Current For Various Temperatures Junction Temperature, T J ( C) Figure. On-Resistance vs. Temperature For Various Gate Voltage 3 CM1D Rev. B, 1-15
4 Typical Performance V DS = V tp < µs T J = 15 C Gate-Source Voltage, V GS (V) T J = -55 C V GS = -5 V V GS = - V V GS = V Drain-Source Voltage, V DS (A) Condition: T J = -55 C t p < µs Figure 7. Transfer Characteristic For Various Junction Temperatures Figure. Body Diode Characteristic at -55 ºC V GS = -5 V V GS = V Condition: t p < µs V GS = -5 V V GS = V Condition: T J = 15 C t p < µs - V GS = - V V GS = - V Drain-Source Voltage, V DS (A) -1 Drain-Source Voltage, V DS (A) -1 Figure 9. Body Diode Characteristic at 5 ºC Figure 1. Body Diode Characteristic at 15 ºC Threshold Voltage, V th (V) Conditions VV DS DS = = V1 GS V I DS I DS = = ma Gate-Source Voltage, V GS (V) I DS = A I GS = 1 ma V DS = V Junction Temperature T J ( C) Gate Charge, Q G (nc) Figure 11. Threshold Voltage vs. Temperature Figure 1. Gate Charge Characteristics CM1D Rev. B, 1-15
5 Typical Performance T J = -55 C tp < µs V GS = V V GS = 5 V tp < µs V GS = V V GS = 5 V - V GS = V V GS = 1 V V GS = 15 V V GS = V V GS = 15 V V GS = 1 V Figure 13. 3rd Quadrant Characteristic at -55 ºC Figure 1. 3rd Quadrant Characteristic at 5 ºC T J = 15 C tp < µs V GS = 15 V V GS = V V GS = 1 V V GS = 5 V V GS = V Stored Energy, E OSS (µj) Drain to Source Voltage, V DS (V) Figure 15. 3rd Quadrant Characteristic at 15 ºC Figure 1. Output Capacitor Stored Energy 1 C iss V AC = 5 mv f = 1 MHz 1 C iss V AC = 5 mv f = 1 MHz Capacitance (pf) 1 1 C oss Capacitance (pf) 1 1 C oss C rss C rss Figure 17. Capacitances vs. Drain-Source Voltage (- V) Figure 1. Capacitances vs. Drain-Source Voltage (-1 V) 5 CM1D Rev. B, 1-15
6 Typical Performance Drain-Source Continous Current, I DS (DC) (A) 1 1 T J 15 C Maximum Dissipated Power, P tot (W) T J 15 C Case Temperature, T C ( C) Figure 19. Continuous Drain Current Derating vs. Case Temperature Case Temperature, T C ( C) Figure. Maximum Power Dissipation Derating vs. Case Temperature Junction To Case Impedance, Z thjc ( o C/W) 1 1E-3 1E SinglePulse 1E-3 1E- 1E- 1E- 1E-3 1E-3 1E-3 1 Time, t p (s) Figure 1. Transient Thermal Impedance (Junction - Case) Limited by R DS On 1 ms 1 µs T C = 5 C D =, Parameter: t p ms Figure. Safe Operating Area 1 µs Switching Energy (uj) V DD = V R G(ext) =.5 Ω V GS = -5/+ V FWD = CD1A L = 1 μh E Total E On E Off Switching Energy (uj) V DD = V R G(ext) =.5 Ω V GS = -5/+ V FWD = CD1A L = 1 μh E Total E On E Off Drain to Source Current, I DS (A) Drain to Source Current, I DS (A) Figure 3. Clamped Inductive Switching Energy vs. Drain Current (V DD = V) Figure. Clamped Inductive Switching Energy vs. Drain Current (V DD = V) CM1D Rev. B, 1-15
7 Typical Performance Switching Loss (uj) V DD = V I DS = A V GS = -5/+ V FWD = CD1A L = 1 μh E Total E On E Off Swithcing Loss (uj) 1 1 E Total E Off I DS = A V DD = V R G(ext) =.5 Ω V GS = -5/+ V FWD = CD1A L = 1 µh E On External Gate Resistor RG(ext) (Ohms) Junction Temperature, T J ( C) Figure 5. Clamped Inductive Switching Energy vs. R G(ext) Figure. Clamped Inductive Switching Energy vs. Temperature Time (ns) V DD = V R L = 133 Ω V GS = -5/+ V t d (off) t f t r t d (on) External Gate Resistor, R G(ext) (Ohms) Figure 7. Switching Times vs. R G(ext) Figure. Switching Time Definition 1 1 Conditons: V DD = 5 V Avalanche Current (A) Time in Avalanche T AV (us) Figure 9. Single Avalanche SOA curve 7 CM1D Rev. B, 1-15
8 Test Circuit Schematic L=1 uh D 1 CD1A A, 1V SiC Schottky V DC C DC =.3 uf Q 1 D.U.T CM1D Figure 3. Clamped Inductive Switching Waveform Test Circuit Q 1 V DC C DC =.3 uf L=1 uh V GS = - 5V R G D.U.T CM1D Q R G CM1D Figure 31. Body Diode Recovery Test Circuit ESD Ratings ESD Test Total Devices Sampled Resulting Classification ESD-HBM All Devices Passed 1V (>V) ESD-MM All Devices Passed V C (>V) ESD-CDM All Devices Passed 1V IV (>1V) CM1D Rev. B, 1-15
9 T V Package Dimensions Package TO-7-3 Recommended Solder Pad Layout U W Pinout Information: Pin 1 = Gate Pin, = Drain Pin 3 = Source Inches Millimeters POS Min Max Min Max A A A b b b b b c D D D E E E E E e.1 BSC 5. BSC N 3 3 L L ØP Q S T U V W Part Number Package Marking CM1D TO-7-3 CM1 TO CM1D Rev. B, 1-15
10 Notes RoHS Compliance The levels of RoHS restricted materials in this product are below the maximum concentration values (also referred to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive 11/5/ EC (RoHS), as implemented January, 13. RoHS Declarations for this product can be obtained from your Cree representative or from the Product Documentation sections of REACh Compliance REACh substances of high concern (SVHCs) information is available for this product. Since the European Chemical Agency (ECHA) has published notice of their intent to frequently revise the SVHC listing for the foreseeable future,please contact a Cree representative to insure you get the most up-to-date REACh SVHC Declaration. REACh banned substance information (REACh Article 7) is also available upon request. This product has not been designed or tested for use in, and is not intended for use in, applications implanted into the human body nor in applications in which failure of the product could lead to death, personal injury or property damage, including but not limited to equipment used in the operation of nuclear facilities, life-support machines, cardiac defibrillators or similar emergency medical equipment, aircraft navigation or communication or control systems, air traffic control systems. Related Links CM PSPICE Models: SiC MOSFET Isolated Gate Driver reference design: SiC MOSFET Evaluation Board: Copyright 1 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo, and Zero Recovery are registered trademarks of Cree, Inc. Cree, Inc. Silicon Drive Durham, NC 773 USA Tel: Fax: CM1D Rev. B, 1-15
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IPI2N15N3 G IPP2N15N3 G OptiMOS 3 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Product Summary V DS 15 V R DS(on),max 2 mw I D 5 A Very low on-resistance
More informationDistributed by: www.jameco.com 1-8-831-4242 The content and copyrights of the attached material are the property of its owner. BSC22N3S G OptiMOS 2 Power-Transistor Features Fast switching MOSFET for SMPS
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BSC32N3S G OptiMOS 2 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for notebook DC/DC converters Qualified according to JEDEC 1 for target applications Product Summary V
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Type IPD135N3L G OptiMOS 3 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for DC/DC converters Qualified according to JEDEC 1) for target applications Product Summary V DS
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BSC79N3S G OptiMOS 2 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for notebook DC/DC converters Qualified according to JEDEC 1) for target applications Product Summary
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Description United Silicon Carbide, Inc offers the high-performance G3 SiC normallyon JFET transistors. This series exhibits ultra-low on resistance (R DS(ON) ) and gate charge (Q G ) allowing for low
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BSC27N4LS G OptiMOS 3 Power-Transistor Features Fast switching MOSFET for SMPS Optimized technology for DC/DC converters Qualified according to JEDEC ) for target applications Product Summary V DS 4 V
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Type OptiMOS TM Power-Transistor Features Optimized for high performance SMPS, e.g. sync. rec. % avalanche tested Superior thermal resistance N-channel Qualified according to JEDEC ) for target applications
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