Efficient Built-In Self-Test Techniques for Sequential Fault Testing of Iterative Logic Arrays

Transcription

1 Prceedngs f he 6h WSES Inernanal Cnference n ppled Infrmacs and Cmmuncans, Elunda, Greece, ugus 8-0, 006 (pp53-57) Effcen Bul-In Self-Tes Technques fr Sequenal Faul Tesng f Ierave Lgc rrays SHYUE-KUNG LU and O-YNG DONG Deparmen f Elecrnc Engneerng Fu-Jen Cahlc Unversy, Tape, Tawan, R.O.C. sklu@ee.fju.edu.w bsrac:- In day s nanmeer echnlgy era, mre sphcaed defec mechansms mgh exs n he manufacured negraed crcus whch are n cvered by radnal faul mdels. In rder asceran he qualy f shpped chps, mre realsc faul mdels shuld be addressed. In hs paper, we prpse bul-n self-es (BIST) echnques fr erave lgc arrays (ILs) based n realsc sequenal cell faul mdel (RS-CF). ccrdng he prpsed esably cndns and he adped faul mdel, exhausve SIC (sngle npu change) pars fr a cell are appled each cell n he IL. The upus can be prpagaed he prmary upus and hen bserved. The SIC cmpnen generar and upu respnse analyzer are als desgned as he BIST crcury. Due he regulary f ILs, he hardware verhead f he BIST crcury s alms neglgble. In rder llusrae ur apprach, a ppelned array mulpler s used as an example. The number f es pars fr cmpleely esng f he array s nly 7. rever, he BIST verhead make delay faul esable s abu.67%. Inrducn Ierave lgc arrays are wdely used n desgnng applcan-specfc negraed crcus (SICs) due her regulary and mdulary. The ms ppular applcans nclude he daapah pars f dgal crcus and dgal sgnal prcessrs. I s well knwn ha he cmplexy f he general lgc esng prblem s NP-cmplee []. Frunaely, many nvel appraches [, 3] were prpsed ease he esng prblem fr ILs and he ms wdely adped faul mdel s he sngle cell faul mdel (SCF). Owng he rapd grwh n VLSI echnlgy, mre sphcaed falure mechansms mgh exs n he manufacured crcu. Ths makes he radnal SCF nsuffcen asceran he qualy f shpped prducs. Therefre, mre cmprehensve faul mdels shuld be esablshed. These nclude he ranssr suck-pen, he gae delay, and he pah delay faul mdels. These faul mdels are als defned as sequenal faul mdels [4]. T deec sequenal fauls, w-paern ess are usually requred. Several wrks have been prpsed fr es generan f sequenal fauls [5, 6]. Hwever, cmbnanal ILs are addressed. In [4], a nvel sequenal faul mdel, called Realsc Sequenal Cell Faul del (RS-CF) was prpsed. I s a mre cmprehensve, cell-level and mplemenan ndependen mdel suable fr IL esng. The prblem f rbus w-paern sequenal faul es generan s addressed. Therefre, he mpran prblem f es nvaldan n sequenal faul esng s slved. The adped RS-CF s defned as fllws [4]: ms ne IL cell can be fauly a a me. The es se f RS-CF cnans all he pssble Sngle Inpu Change (SIC) pars,.e., pars f vecr <v, v > wh Hammng dsance, ha generae a leas ne change a he cell upus. The es se descrbed abve mus be appled every IL cell (es applcan). faul may change he hrznal upus (and/r vercal upus) f he cell. Fauly cell upus mus be prpagaed prmary upus f he IL (faul prpagan). ccrdng hs faul mdel, SIC pars mus be appled every cell n he array. I s shwn ha SIC pars can acheve very hgh sequenal faul cverage and cnrbue rbusness [7]. The C-esably cndns fr ne-dmensnal and w-dmensnal ILs can be fund n ur prevus wrk [8]. Hwever, we sll lack f bul-n self-es echnques fr sequenal faul esng f such ILs. Therefre, BIST echnques are prpsed n hs paper. Bh he SIC cmpnen generar and upu respnse analyzer are desgned as he BIST crcury. The hardware verhead f he BIST crcury s alms neglgble. In rder llusrae ur apprach, a ppelned array mulpler s used as an example. The number f es pars fr cmpleely esng f he array s nly 7. rever, he hardware verhead make delay faul esable s abu.67%. The rganzan f hs paper s as fllws. Secn revews C-esably cndns fr -D ILs. Secn 3 prpses he BIST archecure. n array mulpler s used as an example n Secn 4. Fnally, sme cnclusns are gven n Secn 5.

2 Prceedngs f he 6h WSES Inernanal Cnference n ppled Infrmacs and Cmmuncans, Elunda, Greece, ugus 8-0, 006 (pp53-57) Revew f C-Tesably Cndns fr -D Ierave Lgc rrays In rder ease ur dscussn, sme defnns are defned frs. They are als used n [, 8]. Defnn: cell n an IL wh funcn f s a cmbnanal machne (Σ,, f), where f: Σ s he cell funcn, and Σ = = {0, } w, w denes he wrd lengh f a cell. n IL s an array f cells. Defnn: Sngle Inpu Change par s a par f vecrs <v, v >, where he Hammng dsance beween v and v s, v, v {,, 3,.. n }, n= w. Defnn: We say ha he funcn f f a cell s bjecve when θ θ, f(θ ) f(θ ), θ, θ Σ. Defnn: cmplee SIC sequence (SIC cm ) s a w-paern sequence ha cnans exhausve SIC pars f a cell. The cell behavrs f a ppelned IL can be vewed as a fne sae machne (FS). The sae ransn graph G (V, E) f he cell funcn f s a dreced graph, where V = Σ and E = {(v, f(v)) v V} [8]. Snce each sequenal faul requres a w-paern es, herefre, we shuld defne he sae ransn graph f f wh respec a -paern sequence. Ths ransn graph s dened as where V E G = ( V = { < v, v, E ), > v, v = {( v, f ( v)) v V Σ}, The characerscs f he ransn graph G deermne he cnrllably and bservably f he whle array. Three cndns are prpsed n [8]. Fr smplcy, we nly cnsder he case ha he cell funcn s bjecve. DFT echnques can be used make he cell funcn bjecve [8]. Fr hs case, G (Σ, E ) wll nly cnsss f cmpnens. If a cmpnen f G cnans a leas ne SIC par, hen hs cmpnen s called a SIC cmpnen (SIC cmp ). We assume ha here are n SIC cmpnens n G. Then, he es se S whch cnans all SIC pars f a basc cell s represened as S= { Υ SICcmp, n}. I s evden ha S s a cmplee SIC sequence. Le L dene he number f verces n SIC cmp, hen he lengh f he es se S can be expressed as: S = n L = Le j dene he h w-paern es n SIC cmpj, L j, j n. If we apply j a cell, we ban he upu sequence f( j ). Snce j s a verex f SIC cmpj n G, L j f ) =. We defne T j as ( j j. }. T j = { j, j,..., L j j Therem: mesh-cnneced IL as shwn n Fg. s C-esable under RS-CF f he cell funcn s bjecve. Prf: If we apply all w-paern ess T = (I, J ) cell, and desgn he adapve vercal and hrznal npu sequences as shwn n Fg.. cell rs and cell pq wll receve he same npu sequence f r + s = p + q (ndcaed by he dashed lnes n Fg. ). Faul prpagan n hs case s sraghfrward due he cmpnen prpery f G. Therefre, he esng prcess s a parallel ne. Smlarly, we can apply T j, j n, cell sequenally. Then, he cmplee SIC sequence S can be sen each cell n he array. Faul prpagan can be acheved due he bjecve cell funcn. Therefre, he whle array s sad be C-esable under RS-CF snce he number f ess s cnsan regardless f he array sze. I I J I Fg. : Tes essellan f a mesh-cnneced erave lgc array. 3 Bul-In Self-Tes Technques T dscuss he bul-n self-es schemes, we frs assume ha he cell funcn s bjecve such ha he herem descrbed abve can be appled drecly. The general BIST archecure cnsss f he fllwng:. he rgnal IL under es,. he SIC cmpnen generar, whch generaes all he w-paern es pars f he es se S, 3. he mechansm fr rung he generaed es se S each cell n he IL, 4. he mechansm fr rung he respnses he upu respnse analyzer, 5. he upu respnse analyzer, and 6. he es cnrller. The cnrl crcury s smply a swch, whch decdes he peran mde f he IL (es mde r nrmal mde). The remanng ems ()-(5) are he crcal pars fr cs-effecve mplemenan f he BIST archecures. Based n he es paern essellan shwn n Fg., a ypcal BIST srucure cnanng ems J }. 3 J

3 Prceedngs f he 6h WSES Inernanal Cnference n ppled Infrmacs and Cmmuncans, Elunda, Greece, ugus 8-0, 006 (pp53-57) ()-(5) s shwn n Fg.. In he fgure, exra crcu elemens and wres are hghlghed. The SIC cmpnen generar s marked SICCG, whch s smply a lgc crcu generang all he cmpnen paerns cnaned n G. Snce he SICCG s a b-level mplemenan, whch s very small as cmpared he whle IL. The mulplexers are marked, whch are cnrlled by a mde-selecn sgnal ha ndcaes wheher he crcu s n es mde r nrmal mde. Cnsder he IL shwn n Fg., f s n es mde, all mulplexers ake he npus whch are drawn n hck lne segmens. Therefre, f SICCG generaes he es se S fr cell, all her cells subsequenly receve her wn cmplee SIC sequences accrdng he herem descrbed abve. When s n nrmal mde, all mulplexers ake he npus whch are drawn n hn lne segmens,.e., he es pahs are dsabled, and he array reurns nrmal peran. The perfrmance penaly s alms neglgble snce he mulplexers can be mplemened wh smple pass ranssrs r ransmssn gaes. deermne wheher he upu b s fauly r n. We can als have her appraches perfrm upu respnse analyss, e.g., ransn deecrs and cmparars. Due he essellan prpery f he es paerns, all cells whse ndces sum he same number,.e., hse le n he same 45 lne generae he same upu sequence. Therefre, cmparars can be used cmpare he prmary upus wh he upus le n he same 45 lne. 4 Tesable Desgn f rray ulpler n array mulpler perfrms he peran x r. 4 3 array mulpler [8, 9] and s cell srucure s shwn n Fg. 3. The 4-b x mulplcand prpagaes dwnward. The 3-b mulpler r can be preladed and sred n he -reg s. The 7-b prduc can be receved frm he cells n he rghms clumn. Each cell perfrms he funcns gven as fllws: x = x r = r s = s c r x c = s c + c r x + s r x SICCG I I J J I 3 J 3 where x and r represen mulpler and mulplcand bs, s s he summand b, and c s he carry b. Ther respecve upu bs are dened as x, r, s, and c, whch are prpagaed he nex sage. When a cell cnans a number, s he ndex f an r b. These numbers hus range frm 0. The cell s regser hlds he r b ndcaed. cell ha has n ndex cnans a 0 b. Each cell s essenally a lached -b full adder Fg. : The prpsed BIST srucure, ncludng SIC cmpnen generar, upu respnse analyzer (), and rung mechansms. In Fg., he upu respnse analyzers are marked. ccrdng he specal feaures f he es paerns a cmplee SIC sequence fr each cell here are a varey f appraches fr upu respnse analyss. The frs apprach s he check-sum apprach. By usng hs apprach, each mdule n Fg. s replaced wh an accumular,.e., a bnary adder. Snce he cmplee SIC sequence s fxed, herefre, he accumulaed upu s als fxed. Judgng frm he accumulaed upu, we can denfy wheher he upu sequence s fauly r n. By usng hs apprach, he resuled faul cverage s hgh. lasng wll ccur fr mul-b errrs crrespndng dfferen permuans f he cmplee SIC sequence. Frm [8], we knw ha he cell funcn s n bjecve. Therefre, DFT echnques can be appled. The resuled SIC cmpnens n G fr = 0 are shwn n Fg. 5. Frm he SIC cmpnens we can see ha all SIC pars are ncluded n hese cmpnens. Therefre, he prevus herem can be appled drecly. rever, he BIST srucure shwn n Fg. s als suable fr he array mulpler. Our nex prblem s desgn he SIC cmpnen generar fr he array mulpler. The prpsed srucure s shwn n Fg. 6. We can als use pary checkers check he pary f each upu b. cmplee SIC sequence S ndcaes ha he pary fr each upu b psn mus be fxed. Therefre, we can check he pary f each upu b

4 Prceedngs f he 6h WSES Inernanal Cnference n ppled Infrmacs and Cmmuncans, Elunda, Greece, ugus 8-0, 006 (pp53-57) Fg. 3: 4 3 array mulpler. he upu f he cnrl mdule s. Therefre, he generar (a) Fg. 4: The mulpler cell. (b) Fg. 7: (a) Tes paerns f he SIC cmpnen generar durng Phase, and (b) Tes paerns durng Phase. eners n phase. The smulaed resuls f he generar are shwn n Fg. 7. Fg. 5: SIC Cmpnens fr = 0. 3-b Cuner Barrel Shfer C C C0 X X X0 n cnrl ux ux ux Bs_clk 5 Cnclusns Bul-n self-es (BIST) echnques fr erave lgc arrays (ILs) based n realsc sequenal cell faul mdel (RS-CF) are prpsed n hs paper. ransn graph mdel s used mdel he behavrs f a cell. Exhausve SIC (sngle npu change) pars fr a cell can be appled each cell n he IL. The SIC cmpnen generar s desgned and used as he es paen generar. Due he regulary f ILs, he hardware verhead f he BIST crcury s alms neglgble. In rder llusrae ur apprach, a ppelned array mulpler s used as an example. The number f es pars fr cmpleely esng f he array s nly 7. rever, he BIST verhead make delay faul esable s abu.67%. Fg. 6: The SIC Cmpnen generar fr array mulpler. In Fg. 6, he SIC cmpnen generar cnans a 3-b bnary cuner whch cun frm 000, a 3-b barrel shfer, and sme lgc gaes. The clck cycle f he cuner s sx mes ha f he barrel shfer. The cnen f he barrel shfer (X X X 0 ) s nalzed 00 and he upu f he cnrl mdule s 0. The barrel shfer s shfed rgh fr each BIST clck cycle. We have nce ha he BIST clck has he half frequency f he mulpler clck. The BIST mde ncludes w phases. Durng phase he generar prduces all SIC pars. lernavely, durng phase, wll prduce a sequence f w-paern ess wh Hammng dsance. The value f X durng phase can be cmpued as: BIST_X = (X Bs_clk) C, 0 Smlarly, X can be cmpued as fllws durng phase. BIST_X = X C, 0 n mplemenan f he cnrl mdule s presened n Fg. 6(b). Inally, he flp-flp s se 0. When he flp-flp s enabled by he n sgnal, ndcaes ha he cuner has reached he value and Reference [] H. Fujwara and S. Tda, The cmplexy f faul deecn prblems fr cmbnanal lgc crcus, IEEE Trans. Cmpuers, vl. C-3, n. 4, pp , June 98. [] C. W. Wu and P. R. Cappell, Easly Tesable Ierave Lgc rrays, IEEE Trans. Cmpu., vl. 39, n. 5, pp , ay 990. [3] C. Y. Su and C. W. Wu, Tesng erave lgc arrays fr sequenal fauls wh a cnsan number f paerns, IEEE Trans. Cmpu., vl. 43, n. 4, pp , pr [4]. Psaraks, D. Gzpuls,. Paschals, and Y. Zran, Sequenal faul mdelng and es paern generan fr COS erave lgc arrays, IEEE Trans. Cmpuers, vl. 49, n. 0, pp , Oc [5] D. Gzpuls, D. Nkls, and. Paschals, Tesng COS Cmbnanal Ierave Lgc rrays fr Realsc fauls, Inegran: The VLSI J., vl., pp. 09-8, 996. [6] P. Grard, C. Landraul, V. reda and S. Pravssudvch, n Opmzed BIST Tes Paern Genrar fr Delay Tesng, n Prc. VLSI Tes Symp., pp , prl 997. [7] G. L. Smh, del fr Delay Fauls Based upn Pah, n Prc. IEEE Inernanal Tes Cnf., pp , 985. [8] S. K. Lu, Delay Faul Tesng fr COS Ierave Lgc rrays wh a Cnsan Number f Paerns, IEICE Trans. Inf. and Sys., vl. E86-D, n., pp , Dec [9] J. V. ccanny and J. G. cwhrer, Cmpleely erave ppelned mulpler array suable fr VLSI desgn, IEE Prc., vl. 9, n., pp , pr. 98. [0]. Psaraks, D. Gzpuls and. Paschals, Bul-n sequenal faul self-esng f array mulplers, IEEE Trans. Cmpuer-ded

5 Prceedngs f he 6h WSES Inernanal Cnference n ppled Infrmacs and Cmmuncans, Elunda, Greece, ugus 8-0, 006 (pp53-57) Desgn f Inegraed Crcus and Sysems, vl. 4, n. 3, pp , ar.005. []. Psaraks, D. Gzpuls,. Paschals and Y. Zran, n Effecve BIST rchecure fr Sequenal Faul Tesng n rray ulplers, n Prc. 7h IEEE VLSI Tes Symp., 999, pp.5-58.