x 0x 1x 2 x 2 x 3 x 4 x 2 x 3 p q f g x 0x 1 x 2 x 3 Fig. 1: Optical gates x 4 x 0 x 1 x i Fig. 2: Optical circuit f xi=0 f xi=1

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1 OR-Inerter Graphs or the Synthesis o Optical Circuits Arighna Deb, Robert Wille, Rol Drechsler Computer Science & Engineering, Jadapur Uniersity, India Institute or Integrated Circuits, Johannes Kepler Uniersity, Linz, Austria Institute o Computer Science, Uniersity o Bremen, Bremen, Germany Cyber-Physical Systems, DFKI GmbH, Bremen, Germany arighna.deb@gmail.com, robert.wille@jku.at, drechsle@inormatik.uni-bremen.de Abstract The adances in silicon photonics motiate the consideration o optical circuits as a promising circuit technology. Recently, synthesis or this kind o circuits receied signiicant attention. Howeer, neither the corresponding unction descriptions nor the resulting synthesis approaches explicitly considered how optical circuits actually conduct computations eentually leading to circuits omproable quality. In this work, we present a synthesis low which has explicitly been deeloped or this technology. To this end, we introduce and exploit OR-Inerter graphs (OIGs) a data-structure which is particularly suited or the design o optical circuits. Experimental results conirm the eicacy o the OIG structure and the resulting synthesis approach. Compared to seeral alternatie solutions relying on conentional unction representations the number o gates can be reduced by hal or een signiicantly more than that. I. INTRODUCTION The post-cmos computing technology is gaining importance as the scaling o transistors is approaching its physical limits. Optical circuits emerge as an alternatie to current circuit technologies thanks to the adances in silicon photonics []. In electronic digital systems, optical technology is already in use as ultra-ast interconnects [2], [3]. This requires back and orth conersion rom the optical to the electrical domain at eery interconnect interace obiously a signiicant drawback. The conersion, howeer, can easily be aoided i the underlying systems are realized by optical technologies only. This motiates research in the area o designing ullscale optical circuits. The design automation is one o the key driing orces behind the reduction o the circuit design time and the optimization o the circuit quality. Thus ar, Electronic Design Automation (EDA) has played a crucial role in the deelopment o complex conentional circuits [4]. The major design step usually starts with a logic leel abstraction and, aterwards, moes down to the physical realization, where the desired circuit is reined with respect to the respectie technological constraints. Although physical constraints in optical technology are not entirely soled yet, initial models and corresponding gate libraries already exist or the purpose o logic synthesis and optimization. At this stage, considering logic synthesis and optimization is motiated by the act that EDA or conentional systems started with logic design automation beore physical design automation was actually deeloped [5]. The main goal o logic synthesis is to determine an eicient realization o a Boolean unction. Thus ar, Boolean unctions are represented by dierent data structures such as the two-leel descriptions Sum-o-Products (SoPs) and Exclusie-Sum-o-Products (ESoPs) [5], [6], Binary Decision Diagrams (BDDs) [7], or AND-Inerter graphs (AIGs) [8]. These representations employ either AND-OR, AND-EXOR, multiplexer (MUX), or Boolean conjunction (AND) as logic primities. Howeer, the eicacy o any representation heaily depends on the targeted circuit type i.e. on the richness o the applied gate library and on the capability o each library element (i.e. logic gate) to implement the desired Boolean unction. Initially, optical logic synthesis was limited to dedicated unctionality such as adders [9], [0], multiplexers [], diiders [2], etc. Recently, also the synthesis o arbitrary Boolean unctions has been considered leading to approaches, e.g. based on BDDs [3] [5] but also solutions based on SoPs, ESoPs, or AIGs hae been obsered [3], [6]. Although, this initiates the automatic synthesis o optical logic circuits or large Boolean unctions, oten, the synthesized circuits are expensie with respect to the number o required gates. This is mainly because o the act that, during synthesis, the respectie unctions representations are simply mapped to corresponding optical gates without explicitly exploiting the characteristics o optical circuits. In this paper, we propose a noel methodology to synthesize optical circuits. To this end, we introduce a data-structure called OR-Inerter Graphs (OIGs) a logic representation which is similar to AIGs but employ OR nodes rather than AND nodes in addition to the regular/complement edges. We motiate the utilization o OIGs by considerations that clearly show the suitability o the corresponding OR and NOT operations or the common optical library. In act, mapping an OIG into an optical circuit yields signiicantly smaller realizations compared to existing unction representations. Experimental ealuations conirm these indings. The proposed OIG-based synthesis is capable o realizing circuits which improe alternatie solutions, e.g., based on SoPs, ESoPs, BDDs, and AIGs by 98%, 89%, 54%, and 56%, respectiely (with respect to the number o required gates) In the ollowing, the proposed approach is introduced as ollows. Section II reiews the basics on optical circuits and the commonly applied gate library. Aterwards, Section III discusses the applicability o unction representations such as the aboe-mentioned SoPs, ESoPs, BDDs, and AIGs with respect to the considered optical domain. This proides the motiation o the approach which, aterwards, is described in detail in Section IV. Finally, Section V and Section VI summarize the obtained experimental results and conclude the paper, respectiely. II. OPTICAL CIRCUITS To keep the paper sel-contained, this section briely reiews the common logic model and gate library used in the domain o optical logic synthesis. Optical circuits are usually realized by means o a Mach- Zehnder Intererometer () switch which is based on Semiconductor Optical Ampliiers (SOAs). In the logic domain, the resulting structure is abstracted to a so-called gate. Each gate has two input ports and two output ports. The inputs can either be sourced by light (representing binary ) or darkness (representing binary 0). Logically, an gate is deined as ollows [7], [8]: Deinition : An gate realizes a Boolean unction B 2 B 2 composed o two optical inputs p and q as well as two optical outputs and g. In the presence o both input

2 x 0x x 2 x 4 x 0x p q g (a) gate (b) Splitter (c) Combiner Fig. : Optical gates x Fig. 2: Optical circuit signals, the outputs and g produce and 0, respectiely. The presence onput signal p and the absence onput signal q leads to the logic alue 0 and at the outputs and g, respectiely. Thereore, the unctions = p q and g = p q are realized. Fig (a) proides the graphical representation o an gate. In addition, splitters and combiners are used as optical logic elements in order to realize logic unctions. Deinition 2: A splitter diides an optical signal into two signals each with only hal o the incoming signal power. In contrast, a combiner merges two optical signals into a single one and, by this, inherently realizes the OR-unction. A splitter (combiner) may hae more than two outputs (inputs). Then, in case o a splitter, the strength o the signal is diided by the number o outputs. Fig. (b) and Fig. (c) proide the graphical representation o both elements. Together these logic elements orm a gate library that allows to realize any Boolean unction. The size o an optical circuit is determined in terms o number o gates. This is motiated by the act that each gate needs to be physically realized. Sometimes, also the number o splitters and the number o combiners are considered. Howeer, as they are signiicantly easier to realize than the gates, they are oten considered negligible. Besides that, the number o splitters has an eect to the inal strength o the applied optical signals. Example : Fig. 2 shows an optical circuit composed o two gates, two splitters, and one combiner. III. MOTIVATION Independent rom the respectie technology, synthesis is the task o generating a circuit structure which realizes a gien (Boolean) unction to be synthesized. Corresponding algorithms approach this task rom dierent angles i.e. they rely on dierent unction representations which are used as input including Boolean Algebra and twoleel representations such as Sum o Products (SoPs) and Exclusie Sum o Products (ESoPs) as well as Binary Decision Diagrams (BDDs, [7]) or AND-Inerter Graphs (AIGs, [8]) and realize circuits using dierent (uniersal) gate libraries allowing or the realization o all possible unctions such as {AND, OR, NOT}, {AND, XOR, NOT}, {MUX}, or {NAND}. Quite oten, an obious relation between the respectie unction representation and the used gate library exists. For F x x3 x 4 (a) SoP xi=0 xi=0 xi= xi= x x (b) ESOP (c) BDD (d) AIG Fig. 3: Mapping unction representations to con. circuits x example, Boolean algebra, SoPs, and ESoPs can directly be realized by circuits composed o {AND, OR, NOT} and {AND, XOR, NOT}, respectiely. The nodes o a BDD directly correspond to MUX gates, while the nodes o an AIG directly corresponds to NAND gates. Fig. 3 sketches the corresponding mappings. Moreoer, the respectie relations are oten exploited when technological constraints and/or physical realizations are to be considered. For example, it is known that, in current transistor technologies, a NAND gate is considered signiicantly cheaper than e.g. {AND, OR, NOT}-gates. Hence, when e.g. area or power are o signiicant importance, a synthesis based on AIGs (which can directly be mapped to a NAND-circuit) might be the preerred design scheme. For the domain o optical circuits, respectie considerations hae not been made yet. In act, almost all existing approaches or the synthesis o optical circuits ocused on inestigating whether and how established (conentional) unction representations can be utilized in order to create circuits composed o, splitter, and combiner gates. For example, synthesis based on Boolean Algebra, SoP, or ESoP as introduced in [3], [6] relies on so-called irtual gates i.e. sub-circuits realizing the respectie AND, OR, XOR, NOT operations. Synthesis using BDDs as introduced in [3] [5] relies on subcircuits realizing dierent BDD node conigurations. A synthesis approach based on AIGs has, to the best o our knowledge, not been proposed yet, but would rely on sub-circuits realizing NAND operations. Fig. 4 sketches the corresponding mappings. As can clearly be seen, or all unctions representations considered thus ar, no direct mapping to elementary optical gates exists in act, seeral gates are required to realize just a single building block. This obiously leads to optical circuits which are rather expensie. Motiated by these obserations and discussions, this work aims or deeloping an alternatie unction representation, and a corresponding synthesis approach, which is explicitly dedicated to the gate library reiewed in Section II. Considering the aailable elementary building blocks, we can see that the splitter and the combiner are the cheapest gates in this library. While the splitter only realizes a anout and, hence, not an actual Boolean unction, the combiner seres as a realization o an OR gate. Since the OR operation itsels not uniersal,

3 x 0x x 2 x 4 x x x 0x leel 2 leel 3 xi= x 4 (a) SoP xi=0 xi= xi=0 (b) ESOP (c) BDD (d) AIG Fig. 4: Mapping unction representations to optical circ. x x (a) OR (b) Inerter Fig. 5: Proposed library x 0 x x 0 we additionally consider gates in order to realize the NOT (Inerter) operation. OR and NOT constitute a uniersal gate library which allows or realizing all Boolean unctions. At the same time, both operations are already aailable as elementary building blocks (the ery cheap combiner and the single gate as shown in Fig. 5). In contrast to the preiously proposed synthesis approaches reiewed aboe, this may proide the basis or a signiicantly more eicient synthesis scheme. Hence, in the remainder o this work, we consider the question how to deelop a synthesis scheme which relies on OR and NOT only. IV. PROPOSED APPROACH In order to deelop a synthesis scheme or optical circuits which relies on OR and NOT operations only, we introduce the concept o an OR-Inerter Graph (OIG). OIGs are inspired by the AIGs rom conentional circuit design. In this section, we irst reiew and illustrate the background on AIGs. Based on that, OIGs are introduced and it is shown how OIGs can be deried rom AIGs. These considerations eentually lead to a synthesis scheme or optical circuits which is described in detail at the end o this section. A. AND-Inerter Graph An AND-Inerter Graph (AIG) is a directed acyclic graph G = (V, E) which is composed o three types o nodes. The irst type has no outgoing edges and represents a unique terminal node which seres as primary output. The second type has no incoming edges and represents primary inputs. The third type has two incoming edges and one outgoing edge and represents a Boolean AND operation. These AND nodes also hae two kinds o outgoing edges: a regular edge representing the actual unctionality and a complement edge representing the negation o this unctionality. More ormally, an AIG is deined as ollows: leel x3 x0 x x2 Fig. 6: AND-Inerter graph or unction Deinition 3: An AND-Inerter graph (AIG) oer the primary input ariables X = {x,,, x n } and with the primary output ariables Y = {y, y 2,, y m } is a directed acyclic graph G = (V (= {V X V g V Y }), E) with the ollowing properties: Each primary input (PI) node V X is labeled by X and has no incoming edges. Each primary output (PO) node V Y is a terminal labeled by y j Y and has no outgoing edges. Each non-terminal node V g represents a Boolean conjunction (AND) o the unctions represented by the two incoming edges. An edge e E connecting a source node u V to a target node V is either a regular or a complement edge i.e. e = {(u, ( p)) u, V, u V Y, V X } with p denoting whether the edge is a regular edge (p = ) or a complement edge (p = 0). The size o an AIG is measured in terms o the total number o AND nodes. Example 2: Consider the unction = (x 0 x ) (x x 2) ( x 3). Using DeMorgan s theorem, the unction can be written as = ((x 0 x ) (x x 2) ( x 3) ). The corresponding AIG is shown in Fig. 6, in which, an edge with a solid dot denotes a complement edge. B. OR-Inerter Graph An OR-Inerter Graph (OIG) is a directed acyclic graph H = (V, E) which is structurally identical to an AIG. Howeer, both dier with respect to the logic primitie. Instead o the AND operation, an OR operation is employed in the nonterminal nodes o an OIG. More ormally, an OIG is deined as ollows: Deinition 4: An OR-Inerter graph (OIG) oer the primary input ariables X = {x,,, x n } and with the primary output ariables Y = {y, y 2,, y m } is a directed acyclic graph H = (V, E) with a inite set o nodes V = V X V h V Y, where V x = { x, x2,, xn } are primary input nodes, V h = { h, h2,, hk } are non-terminal nodes representing the logical OR operations in the graph, and V y = { y, y2,, ym } are terminal nodes representing primary outputs. an edge e E between a source node u V and a target node V is either a regular or a complement edge i.e. e = {(u, ( p)) u, V, u V Y, V X } where, p denotes whether the edge is a regular edge (p = ) or a complement edge (p = 0). The size o an OIG is measured in terms o the total number o OR nodes.

4 leel 3 leel 2 leel 2 leel leel x3 x0 x x2 Fig. 7: OR-Inerter graph or unction x (a) First step Example 3: Re-consider the unction used in Example 2. The unction is expressed in terms o OR operators as ((x 0 ) ( x ) (x ) ). This can be represented as an OIG as shown in Fig. 7. leel 2 leel 3 leel 3 C. Transormation o AIG into OIG Here, we show that an AIG representing an arbitrary Boolean unction can easily be translated into a unctionally equialent OIG. This builds the basis o our proposed synthesis low. Gien an AIG, G = (V, E), an OIG, H = (V, E) is obtained by substituting each 2-input AND node with a unctionally equialent 2-input OR node applying DeMorgan s theorem. To this end, a total o eight substitutions (orming a substitution set S) hae to be considered: S ( i j ) ( j ) ( i j ) ( j ) ( i j) ( j ) ( i j) ( j ) ( j ) ( i j) ( j ) ( i j) ( j ) ( i j ) ( j ) ( i j ) Theorem : For any AIG, the substitution set S is complete. Proo: By deinition, any AND node in an AIG has two incoming edges i.e. takes 2-inputs and j. This means, any single node can realize the logical conjunction (AND) o one input combination out o 4 combinations { j, j, j, j }. In other words, all AND nodes realize at most 4 logical conjunctions. Further, the complement edge out o any AND node realizes the inersion o the respectie logical conjunction. Thereore, in total, there are 8 possible node combinations in any AIG. Hence, the proo. Lemma : Let be a Boolean unction deined oer {, }. This unction can always be conerted into an expression composed o {, } by applying S in a recursie manner. Proo: Without the loss o generality, assume that the Boolean unction s expressed as ollows: = ( j ) I and j are two primary inputs e.g. and x j, then we can substitute them by applying S as ollows: = ( x j ) = ( x j) (b) Second step (c) Third step Fig. 8: Transormation o AIG into OIG I at least one input e.g., represents a logical conjunction i.e. = (p q ), then we can substitute them by applying S as ollows: = ( j ) = ( i j) [applying substitution S] = ((p q ) j) = (( i p i q ) j) [applying substitution S] This shows that applying rules rom S in a recursie manner, an expression composed o {, } transorms into an expression composed o {, }. Hence, the proo. Theorem 2: Any AIG, G = (V, E) can be transormed into an OIG, H = (V, E) using the substitution set S. Proo: The proo ollows rom Lemma. Example 4: Consider the AIG shown in Fig. 6 to be translated into a unctionally equialent OIG. The translation begins with traersing the AIG in a breadth-irst manner and applying the substitution rules S. For the irst leel, this results in OR nodes as shown in the same leel in Fig. 8(a). In the next step, the substitution rules S are urther applied on the AND nodes at leel 2 leading to the graph as depicted in Fig. 8(b). In a similar ashion, the AND node at leel 3 is handled leading to the structure shown in Fig. 8(c). As a result o these transormations, an OIG is generated which is depicted in Fig. 7. D. Proposed Synthesis Flow Based on the discussions aboe, a synthesis low or the eicient realization o optical circuits can be ormulated, which is composed o three major steps: () the generation o an AIG, (2) the transormation o the AIG into an OIG, and (3) the mapping o the OIG into an optical circuit. In order to generate the AIG, existing methods as e.g. employed in tools such as ABC [9] can be applied. How to transorm the AIG to an OIG has been coered in the preious sub-section. Thereore, the mapping to an optical circuit remains let to be described. To this end, we consider the unctional behaior o all releant node conigurations which may occur in an OIG and or which a corresponding sub-circuits is required. This includes all OIG nodes representing an OR operation or a PI and hae

5 i i i Fig. 9: Substitution o OIG nodes to optical circuits one or more outgoing regular edges, i i i i i i i x i one or more outgoing complement edges, or both, one or more regular and complement edges. Fig. 9 shows the corresponding circuits realizing all the cases. In general, eery non-terminal node is mapped to a combiner and a complement edge is realized using an gate or the NOT operation. Wheneer a node has multiple outgoing edges i.e. multiple successors, a splitter is added to the respectie building blocks. Eentually, this leads to a synthesis low as ollows: ) Generate an OIG H = (V, E) representing a unction to be synthesized. 2) Traerse H in a depth-irst manner. 3) For each node, apply the corresponding sub-circuit as shown in Fig. 9. 4) Connect the inputs o the sub-circuit accordingly to the corresponding outputs o the sub-circuit representing the preiously traersed nodes o H. Example 5: Consider the OIG representing the unction as shown in Fig. 7. The mapping scheme traerses the OIG in a depth-irst manner. Applying the substitutions shown in Fig. 9 to each node o the OIG, the optical circuit depicted in Fig. 0 results. V. EXPERIMENTAL EVALUATION In this section, we summarize the results obtained by the proposed method. To this end, the synthesis low described in Section IV has been implemented in C++. First, an AIG o the unction to be synthesized is created using the tool ABC [9]. Then, we conert this data-structure to an OIG and apply the mapping method as described aboe. In order to compare the obtained results, we additionally synthesized circuits using the BDD-based approach proposed in [4] as We would like to thank the authors o [4] or making us their tool aailable. x Fig. 0: Resulting optical circuit or unction well as SoP-, ESoP-, and AIG-based approaches ollowing the concepts discussed in Section III. As benchmarks, unctions rom the LGSynth library hae been applied. All experiments hae been carried out on a Linux machine with a 2.8 GHz Intel Core i7 processor and 8 GB memory. All circuits hae been obtained in negligible run-time (i.e. not more than one CPU minute) which is why we omit a detailed run-time discussion in the ollowing. Table I shows the obtained results. The irst column proides the details o the considered benchmark, i.e. their names as well as number o primary inputs (PI) and primary outputs (PO). The next three columns report the number o gates (), the number o combiners (Combiner), as well as the number o splitters (Splitter) or the resulting circuits obtained by the SoP-, ESoP-, BDD-, AIG-, and OIG-based synthesis approaches. Note that the AIG-based approach always yields circuits with a total o zero combiners which is why we omit a dedicated column in this case. The ourth column ( ) reports the sum o all elements, i.e. gates, combiners and splitters or the respectie approaches. In the inal column, we hae reported the percentage reduction in number o gates compared to existing unction representations. The results conirm that, or the synthesis o optical circuits, OIGs are indeed more suitable than alternatie unction representations and methods. In act, OIG-based synthesis clearly outperorms all other synthesis approaches with respect to the number o gates sometimes circuits with orders o magnitudes less gate result. On aerage, improements o 98%, 89%, 54%, 56% with respect to the gate count can be achieed compared to the SoP-, ESoP-, BDD-, and AIGbased approaches, respectiely. As mentioned in Section II, the number o gates is most important metric as s contribute most to the chip size, while combiners/splitters are negligible. Howeer to ealuate their impact on oerall circuit size, the numbers o gates, combiners and splitters are summed up in columns denoted by. The results demonstrate that, een under this consideration, the aerage circuit size obtained rom OIGs is still 96%, 80%, and 26% smaller compared to SoP-, ESoP-, and BDD-based approaches. Only with respect to the AIG-based approach, roughly the same circuit size results. But note that this is basically only because o the act that AIGs need signiicantly ewer combiners. Howeer, since combiners are easier to realize than gates (rom which AIGs still require signiicantly more), OIG-based synthesis clearly positions itsel as a more promising design solution or the realization o eicient and compact optical circuits. Only in one aspect (namely the number o splitters) one synthesis approach (namely SoP-based synthesis) perorms better than the proposed OIG-based solution (except or a ew cases). This certainly helps to aoid splitting optical signals and keeping the signal strength. But signals applied to circuits obtained by SoP-based synthesis hae to pass through a tremendous amount o gates which also harms their

6 TABLE I: Experimental Ealuation Function Combiner Splitter % Reduc. in w.r.t. name PI/PO SoP ESoP BDD AIG OIG SoP ESoP BDD OIG SoP ESoP BDD AIG OIG SoP ESoP BDD AIG OIG SoP ESoP BDD AIG apex5 7/ % 9.2% 78.8% 49.9% cps 24/ % 87.5% 69.6% 54.8% ex4 28/ % 92.4% 68.3% 50.8% soar 83/ % 89.3% 79.0% 52.9% apex 45/ % 57.2% 48.0% 56.2% mish 94/ % 52.8% 55.3% 20.9% seq 4/ % 92.4% 59.7% 54.4% ti 47/ % 8.3% 64.4% 53.7% x2dn 82/ % 68.3% 69.% 52.6% x7dn 66/ % 93.6% 73.5% 52.9% xparc 4/ % 90.7% 52.4% 57.8% apex2 39/ % 99.3% 77.8% 54.% cordic 23/ % 99.6% 54.4% 58.8% pdc 6/ % 85.6% 44.9% 57.7% spla 6/ % 88.0% 50.% 62.0% / % 93.% 49.5% 52.3% 4mod5 4/ % 0.0% -37.5% 35.3% 4mod7 4/ % 38.7% 34.5% 5.3% 5xp 7/ % 5.9% -30.9% 52.7% add6 2/ % 94.7% 64.3% 47.9% adr4 8/ % 8.7% 5.8% 46.7% alu 5/ % 26.7% 8.3% 45.0% alu 2/ % 49.% 7.6% 52.5% alu2 0/ % 33.3% 25.% 55.8% alu3 0/ % 8.3% 69.5% 53.5% alu4 4/ % 79.5% 49.5% 55.% bw 5/ % 82.7% 7.4% 60.5% decod24-enable 3/ % 50.0% 2.5% 30.0% ex5p 8/ % 82.8% 24.4% 6.5% ham5 5/ % 32.9% -2.2% 54.3% ham3 3/ % 0.0% 3.3% 50.0% hwb4 4/ % 40.0% 42.9% 57.% hwb5 5/ % 47.6% 34.3% 56.4% hwb6 6/ % 47.8% 4.4% 55.5% hwb8 8/ % 66.5% -32.2% 56.3% mod5d2 5/ % 7.2% 0.0% 38.5% One-two-three 3/ % 52.4% 37.5% 52.4% plus27mod892 3/ % 40.2% -54.9% 62.7% plus63mod4096 2/ % 37.0% -56.3% 59.5% plus63mod892 3/ % 46.7% -37.7% 63.3% rd53 5/ % 32.8% 0.9% 53.4% rd73 7/ % 55.7% -2.3% 54.7% rd84 8/ % 6.4% -27.% 54.8% ur 9/ % 66.6% 25.3% 58.0% ur2 8/ % 59.8% 34.4% 57.5% ur5 9/ % 27.2% 23.2% 57.9% * proides sum o numbers o, combiner and splitter ** AIG always generates zero combiners strength. In contrast, signals hae to pass signiicantly less gates in total when the circuit is deried rom OIG-based synthesis. Additionally considering issues such as circuit size (which also is mainly aected by gates), OIG-based synthesis clearly positions itsel as a promising design solution or the realization o eicient and compact optical circuits. VI. CONCLUSION In this work, we presented a synthesis approach or optical circuits based on OR-Inerter graphs. In contrast to conentional unction descriptions such as SoPs, ESoPs, BDDs, or AIGs, this explicitly considers how optical circuits actually conduct computations: with combiners realizing OR operations and (larger) gates whose number can be kept moderate by using them or NOT operations only. Experimental results alidated the potential o OIGs in optical logic synthesis and yielded circuits which are reduced by hal or een signiicantly more than that with respect to gate count compared to preiously proposed methods. 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