Chapter 9 Pipeline and Parallel Recursive and Adaptive Filters

Transcription

1 Chpte 9 Ppele d Pllel Recusve d Adptve Fltes Y-Tsug Hwg VLSI DSP Y.T. Hwg 9- Itoducto Ay equed dgtl flte spectum c be eled usg FIR o IIR fltes IIR fltes eque lowe tp ode but hve potetl stblty poblem dptve fltes e used tme vyg systems coeffcets of the dptve dgtl fltes e dpted t ech teto ecusve d dptve fltes cot be esly ppeled o pocessed pllel due to the feedbck loops VLSI DSP Y.T. Hwg 9-

2 Itoducto Pllelg d ppelg ecusve dgtl fltes look hed computto cemetl block pocessg elxed look hed tsfom VLSI DSP Y.T. Hwg 9- Ppele Itelevg Dgtl Fltes Thee foms of ppele televg effcet sgle/mult-chel televg effcet sgle-chel televg effcet mult-chel televg effcet sgle/mult-chel televg cosde st ode LTI ecuso y*yb*u VLSI DSP Y.T. Hwg 9-4

3 Ppele Itelevg Dgtl Fltes smple st ode ecuso b setg - delys c 5-wy televg VLSI DSP Y.T. Hwg 9-5 Sgle/ult-Chel Itelevg Iteto peod s T m T -stge ppeled veso b, whee - ddtol ltches e dded clock peod c be educed by tmes smple peod must be cesed tmes fo coect opeto tmes esclg effectve tto tevl d computg ltecy ems uchged ovehed of - ddtol ltches VLSI DSP Y.T. Hwg 9-6

4 Sgle/ult-Chel Itelevg c, depedet tme sees e opeted o the sme hdwe my coespod to ech cscde stge of lge flte o depedet chels equg detcl flteg opetos lso kow s -slow ccut potetl dwbcks smple te s tmes slowe th the clock te effcet pocesso utlto f depedet computg sees e ot vlble VLSI DSP Y.T. Hwg 9-7 Effcet Sgle Chel Itelevg -step Look hed tsfomto y*yb*u y[*yb*u]b*u teto boud T m T / y *y*b*ub*u teto boud T m T / -step look hed tsfomto y y bu coeffcets c be pe-computed VLSI DSP Y.T. Hwg 9-8

5 Effcet Sgle Chel Itelevg equvlet elto of ufoldg st ode IIR flte tme b equvlet st ode ecuso fte look hed tsfom VLSI DSP Y.T. Hwg 9-9 Effcet Sgle Chel Itelevg -step look hed tsfomto llows sgle sel computto tsfomed to depedet cocuet computtos loop dely s computto s completed cycles teto boud s T m T / hdwe complexty d computg ltecy e lely cesed tmes hghe smplg te th th the ogl gph tl codtos y- - * y,,,., - VLSI DSP Y.T. Hwg 9-

6 Effcet Sgle Chel Itelevg 4 equvlet st ode ecuso fte - step look hed tsfom b ptl schedulg fo 5 VLSI DSP Y.T. Hwg 9- Effcet ult-chel Itelevg Look hed tsfom ppele televg ssume P depedet tme sees chels loop s -stge ppeled the ecuso must be teted Q - tmes, whee P*Q Exmple fo 6, P y y bu bu bu,, ptl schedule fo -chel wth 6 ppele stges obted usg -step LA VLSI DSP Y.T. Hwg 9-

7 Ppelg st Ode IIR Fltes Look hed tsfom toduces ccelg poles d eos f the toduced poles d eos do ot ccel ech othe exctly due to e.g. fte pecso HW lmtto the poles outsde ut ccle wll cuse stblty poblem ppeled elto fo st ode IIR flte s lwys stble povded the ogl s stble decomposto techque to mplemet the o-ecusve poto due to look hed tsfom to cheve logthmc HW complexty cese w..t. the No. of ppele stges VLSI DSP Y.T. Hwg 9- Look Ahed fo st ode IIR Fltes Cosde fst ode flte cots pole t, -stge ppeled veso flte cots dded poles d eos t H becuse the toduced poles hve mgtude lwys less th the flte s lwys stble eve the dded poles e ot exctly cceled out H e ± jπ / VLSI DSP Y.T. Hwg 9-4

8 Look Ahed Ppelg wth Powe of Decomposto No-ecusve pt of powe of -stge ppele s decomposed to log sets of tsfomto b cosde st ode ecusve flte H hs sgle pole t log fte look hed b H ddg - poles d eos t detcl loctos hs poles t loctos, e jπ /, e jπ /,, e j π / VLSI DSP Y.T. Hwg 9-5 Powe of Decomposto The decomposto of the ccelg eos the -th stge mplemets eos locted t e,,,, j π / eques sgle ppeled multplcto opeto depedet of the stge umbe. A totl of log multplcto s eeded VLSI DSP Y.T. Hwg 9-6

9 VLSI DSP Y.T. Hwg 9-7 Powe of Decomposto Powe of Decomposto pole epesetto of st ode ecusve flte b pole eo epesetto of st ode LTI ecusve system wth 8 loop ppelg stges c decomposto bsed ppele mplemetto fo 8 VLSI DSP Y.T. Hwg 9-8 Powe of Decomposto 4 Powe of Decomposto 4 Tme dom explto fo 8 exmple,whee u b y y u b y y f y f y f y u b y y f f f f f f u b f

10 Powe of Decomposto 5 I fte pecso mplemetto, the poles e locted t p Δ / whee Δ coespods to fte pecso eo epesetg the devto becomes sevee whe << ot poblem Δ exct pole-eo ccellto leds to phse d mgtude eo c be educed by cesg the wod legth VLSI DSP Y.T. Hwg 9-9 Iexct pole eo ccellto due to fte pecso mplemetto Powe of Decomposto 6 VLSI DSP Y.T. Hwg 9-

11 Geel Decomposto If p the o-ecusve stges mplemet -, -,, p - eos -stge ppele decomposto exmple H st stge mplemets the eo t - d stge mplemets 4 eos t e d stge mplemets 6 eos t VLSI DSP Y.T. Hwg 9-6, e ± jπ / ± jπ / ± j, e, e ± jπ / 6 ± j5π / 6 pole eo locto of - stge ppeled st ode ecusve flte b decomposto of the eos of the ppeled flte fo decomposto Geel Decomposto VLSI DSP Y.T. Hwg 9-

12 Geel Decomposto A ltetve ppele decomposto H st stge: - d stge: ±j d stge: A ltetve ppele decomposto H ± / st stge: e jπ d stge: d stge: e ± jπ / 6, e ± jπ / e, ±, j, e e ± jπ / 6 ± j5π / 6 ± jπ / 6, 8 e 6, e ± j5π / 6 ± jπ / VLSI DSP Y.T. Hwg 9- Ppelg Hgh Ode IIR Fltes Clusteed look hed tsfoms le hdwe complexty w..t. ppele stges but ot lwys guteed to be stble sctteed look hed tsfoms guteed to be stble hghe hdwe complexty,.e. N* both tsfoms educe to the sme fom the st ode IIR flte cse VLSI DSP Y.T. Hwg 9-4

13 Clusteed Look-Ahed Ppelg Cosde N-th ode dect fom IIR flte H y N N N N b y y b u the smple te s lmted by the thoughput of multplcto d ddto N VLSI DSP Y.T. Hwg 9-5 Clusteed Look-Ahed Ppelg ddg ccelg poles d eos such tht the coeffcets of -,, -- the deomto becomes eo look hed the cluste of pst N outputs by - steps y-, y-,, y-n y-, y--,, y--n the ctcl loop cots dely elemets d sgle multplcto smple te c be cesed by fcto -stge clusteed look-hed ppelg VLSI DSP Y.T. Hwg 9-6

14 Clusteed Look-Ahed Ppelg Cosde ll-pole d ode IIR wth poles t / d /4 ogl tsfe fucto H fo -stge ppelg, the coeffcet of - must be ullfed multply the umeto d deomto by 5/4 - I.e. ddg ccelg pole d eo t -5/4 the tsfomed tsfe fucto H VLSI DSP Y.T. Hwg Clusteed Look-Ahed Ppelg 4 -stge ppelg multply the umeto d deomto by 5/4-9/6-5 the tsfomed tsfe fucto H geel fom of multplyg fctos, whee, fo,,, N N k, k k fo > VLSI DSP Y.T. Hwg 9-8

15 Clusteed Look-Ahed Ppelg 5 Hdwe mplemetto complexty coeffcets of the fltes e pe-computed off-le umeto o-ecusve pt eques N PYs deomto ecusve pt eques N PYs totl N N multplctos le HW mplemetto complexty Flte stblty poblem ddg poles my le outsde the ut ccle exmple: ssume the d ode IIR hs poles t.5 d.75 -stge ppelg toduce ddtol pole t -.5 VLSI DSP Y.T. Hwg 9-9 Clusteed Look-Ahed Ppelg 6 pole eo epesetto of stble d ode ecusve flte b poles & eos fte - stge ppelg usg clusteed look hed c poles & eos fte - stge ppelg usg clusteed look hed VLSI DSP Y.T. Hwg 9-

16 Clusteed Look-Ahed Ppelg 7 Flte stblty poblem cot. -stge ppelg toduce two ddtol poles t.65 ± j.89 ote tht the ogl flte s stble! VLSI DSP Y.T. Hwg 9- Stble Clusteed Look hed Flte Desg Cosde stble ecusve dgtl flte H N H D N P N P D P Q P epesets supefluous poles eeded to cete the desed ppele dely fo > c some ctcl dely, the flte s lwys stble umecl sech methods e eeded to obt optml ppelg level d P Exmple: cosde H c 5 d fo 6, H VLSI DSP Y.T. Hwg 9-

17 Stble Clusteed Look hed Flte Desg ogl poles b poles & eos of 6-stge ppeled flte usg stble clusteed look hed whe the o. of deomto multples s lge, ppeled flte suffes fom lge oud-off ose the deomto cot be decomposed ode to mt level of ppelg VLSI DSP Y.T. Hwg 9- Sctteed Look Ahed Ppelg The deomto of H s tsfomed to cotg N tems, Z -, Z -,, Z -N equvletly, y s computed tems of N pst sctteed sttes y-, y-,, y-n fo ech pole, - ccelg poles d eos e toduced wth equl gul spcg sme dstce fom the og s tht of the ogl pole e.g. f the ogl pole s p jπk / dded poles d eos e pe, fo k,,, VLSI DSP Y.T. Hwg 9-4

18 VLSI DSP Y.T. Hwg 9-5 Sctteed Look Ahed Ppelg Sctteed Look Ahed Ppelg Assume the deomto of H c be fctoed s fte sctteed look-hed tsfom cosde the d ode flte, fo N p D ' ' / / N k k j N k k j Z D N p e p e N D N H π π 6 4 H H VLSI DSP Y.T. Hwg 9-6 Sctteed Look Ahed Ppelg Sctteed Look Ahed Ppelg Cosde the d-ode flte wth complex cojugte poles t fo -stge ppelg whe θπ/, oly pole & eo t e dded jθ e ± cos H θ cos cos cos cos H θ θ θ θ H

19 VLSI DSP Y.T. Hwg 9-7 Sctteed Look Ahed Ppelg 4 Sctteed Look Ahed Ppelg 4 Cosde the d-ode flte wth poles t, fo -stge ppelg ddg poles t H / /, π π j j e e ± ± 6 4 H VLSI DSP Y.T. Hwg 9-8 Sctteed Look Ahed Ppelg 5 Sctteed Look Ahed Ppelg 5 Pole eo epesetto of -stge ppeled equvlet stble flte usg sctteed look hed

20 Powe of Decomposto Sctteed Look Ahed Scheme The multplcto complexty sctteed look hed tsfom o-ecusve poto : N ecusve poto s : N much gete th tht clusteed look hed scheme cosde ecusve flte H ' N N b N D N by multplyg both umeto d deomto VLSI DSP Y.T. Hwg 9-9 Powe of Decomposto Fo -stge ppelg H N N b ' N N [ ][ ] N' D' the deomto cots tems of -, -4,, -N subsequet tsfoms c be ppled to obt 4,8 d 6 stge ppeled mplemettos log sets of tsfoms e eeded to cheve - stge ppelg ech tsfom double the speed but lso cese the hdwe complexty by N VLSI DSP Y.T. Hwg 9-4

21 Powe of Decomposto Applyg log - sets of tsfoms leds to -stge ppelg eques NN* log multplctos logthmc complexty w..t. speed up totl umbe of delys N*log N delys e used the o-ecusve poto N*log delys e equed to ppele ech N*log multples by stges VLSI DSP Y.T. Hwg 9-4 Powe of Decomposto 4 N- poles d eos e dded N- eos e decomposed d mplemeted log stges st stge eles N-th ode oecusve secto followg stges mplemets N, 4N,, N/- ode o-ecusve sectos ech secto eques N multplcto due to the symmety of coeffcets depedet of the ode of the secto VLSI DSP Y.T. Hwg 9-4

22 Powe of Decomposto 5 Cosde d-ode ecusve flte exmple H Y U b b b cosθ the poles e locted t the ppeled fucto H cos θ jθ e ± the poles e locted t b log cos θ e ± j θ π /,,,,, mplemetto complexty s log 5 multplctos VLSI DSP Y.T. Hwg 9-4 Powe of Decomposto 6 pole dgm of the d ode flte b poles & eos of the ppeled d ode flte wth 8 loop ppelg stges c decomposto of poles d eos of the ppeled flte VLSI DSP Y.T. Hwg 9-44

23 Powe of Decomposto 7 Implemetto of the ogl d the ppeled sctteed look-hed ecusve fltes VLSI DSP Y.T. Hwg 9-45 Sctteed LA Ppelg wth Geel decomposto Fo N-th ode flte wth levels of ppelg N- ccelg eos fo p decomposto the st stge mplemets N - eos the d stge mplemets N - eos the Pth stge mplemets N p- p - eos the o-ecusve poto eques N delys d N P multples geeto decomposto of hgh ode IIR flte decompose to cscde of st ode sectos pply geel decomposto to ech st ode secto VLSI DSP Y.T. Hwg 9-46

24 Pllel Pocessg fo IIR Fltes st ode IIR flte cse H whee y yu fo 4-pllel chtectue mplemetto y4 4 y u uuu by substtutg 4k y4k4 4 y4k u4k u4ku4ku4k pole of the ogl system s t pole of the pllel system s t 4 pole s moved towd the og mpoved obustess to the oud-off eo VLSI DSP Y.T. Hwg 9-47 Pllel Pocessg fo IIR Fltes Note tht ppeled pocessg cse, ccelg poles d eos e toduced substtutg wth 4k4, 4k5, 4k6, 4k7 ledg to 4 pllel pocessg blocks VLSI DSP Y.T. Hwg 9-48

25 Pllel Pocessg fo IIR Fltes eque L AC opetos oe dely elemet epesets L smple delys VLSI DSP Y.T. Hwg 9-49 Pllel Pocessg fo IIR Fltes 4 Icemetl block pocessg use y4k to compute y4k,.e. y4k y4k u4k d the use y4k to compute y4k, the y4k the hdwe complexty s educed fom L to L- cesed computto tme fo y4k, y4k, y4k VLSI DSP Y.T. Hwg 9-5

26 Pllel Pocessg fo IIR Fltes 5 Icemetl block flte stuctue wth L 4 VLSI DSP Y.T. Hwg 9-5 Pllel Pocessg fo IIR Fltes 6 A secod ode IIR exmple fo block pocessg H y y y f, 4 8 whee u u u -pllel system compute yk d yk4 usg yk d yk fo yk, yk yk -stge clusteed LA fo yk, yk yk4 -stge clusteed LA VLSI DSP Y.T. Hwg 9-5

27 Pllel Pocessg fo IIR Fltes 7 & -stge clusteed look hed 5 y y y f y y f y f y y 4 f y f f -loop updte equto yk yk yk f k yk 4 yk yk f k f k 5 4 f k f k 4 VLSI DSP Y.T. Hwg 9-5 Pllel Pocessg fo IIR Fltes 8 Pole eo plots of the tsfe fucto loop updte fo block se eltoshp of ecuso outputs VLSI DSP Y.T. Hwg 9-54

28 Pllel Pocessg fo IIR Fltes 9 yk c be obted cemetlly 5 y k yk yk f k 4 8 VLSI DSP Y.T. Hwg 9-55 Commets The ogl system hs poles t / d /4 tsfomed system 5 yk 57 yk the mtx hs egevlues / d /4 the pllel system s moe stble the pllel system hs the sme umbe of poles s the ogl system hdwe complexty yk yk fo d ode IIR flte N L [L- L-] 4 L- 7L - PY opetos f f VLSI DSP Y.T. Hwg 9-56

29 Combed Pllel & Ppelg Pocessg To cheve speed up L L s the block se d s the o. of ppelg stge fo H/- - wth 4 d L H s st ode loop updte equto s equed d the othe two c be computed cemetlly 4 loop cots 4 dely elemets L yk yk VLSI DSP Y.T. Hwg 9-57 Combed Pllel & Ppelg Pocessg -step look hed tsfom y y u y substtutg k yk 8 5 yk uk uk 4 uk 7 yk u uk uk 5 uk 8 k 6 u u uk uk 6 uk 9 uk uk uk 6 f f k 9 f k VLSI DSP Y.T. Hwg 9-58

30 Combed Pllel & Ppelg Pocessg Whee f k f k uk uk uk f k 9 f k VLSI DSP Y.T. Hwg 9-59 Commets Combed Pllel & Ppelg Pocessg 4 hs 4 poles, -, j, -j decomposto s used fo the o-ecusve poto multplcto complexty s L-log d ode flte exmple wth L d H loop updte opetos ogl poles /, /4 ew poles ±/, ±/4 VLSI DSP Y.T. Hwg 9-6

31 Commets Systemtc ppoch to compute pole loctos wte loop updte equtos usg L-level look hed wte the stte spce epesetto of the pllel ppeled flte, whee stte mtx A N N compute the eevlues λ of mtx A, I N N poles of the ew pllel ppeled system coespod to the -th oots of the egevlues of A, λ VLSI DSP Y.T. Hwg 9-6 Low Powe IIR Flte Desg Pllel d ppeled pocessg c be used fo low powe desg cosde 4-th ode Chebyshev low-pss flte 4.86 H ssume multple cpctce s domt ssume Vdd 5V d Vt v usg sctteed look hed wth powe of decomposto VLSI DSP Y.T. Hwg 9-6

32 Ppeled pocessg to educe powe 4-level ppelble tsfe fucto N/D N D ppeled desg set delys to the ecusve shote ctcl pth fte etmg smlle mout of chgg/dschgg cpctce ech ppele stge use lowe powe supply yet mt the ogl speed the ppeled suppled βv, wth β < 4 8 VLSI DSP Y.T. Hwg 9-6 Ppeled pocessg to educe powe popgto dely sequetl system s 4-level ppeled system β.476 d ew Vdd.8V powe dsspto T pd T pd C k V C ch g e dd ch g e Vdd Vt k5 Cch g e 5β 4 k5β 5 the smple peod s equl to T pd C sequetl system s P 4-level ppeled system P seq pp C seq totl T pd pp totl 5 m.8 T pd seq C m pp 5 C f s.8 f s VLSI DSP Y.T. Hwg 9-64

33 Ppeled pocessg to educe powe Powe to umbe of multplctos, m seq 5, m pp P Rto P pp seq Exmple: secod ode IIR flte 5 y y y u u u 4 8 VLSI DSP Y.T. Hwg 9-65 Pllel pocessg to educe the powe -pllel flte desg outputs pe clock cycle clock cycle c be thee tmes the smple cycle the ctcl pth of the sequetl flte s PY Add feedfowd pt of the ppeled flte desg s etmed VLSI DSP Y.T. Hwg 9-66

34 Pllel pocessg to educe the powe Popgto dely The ctcl pth of the pllel desg s PY Add ssume the chge/dschge cpctces d the delys e domted by the multples ssume the pllel flte suppled βv, wth β < d the theshold voltge V t.6v popgto dely clock cycle fo sequetl flte s CV Tseq k V V t popgto dely clock cycle fo pllel flte s T C βv p k βv Vt VLSI DSP Y.T. Hwg 9-67 Pllel pocessg to educe the powe V βv Choose T p T seq V V βv we get β.467 d βv.65v powe cosumpto P P seq p C C P Rto P commets p seq V f s βv 4β fs 4β C 9.6% t V t the pllel o ppeled desg c be used ethe to cheve hgh speed o low powe opetos VLSI DSP Y.T. Hwg 9-68 V f s

35 Ppeled Adptve Dgtl Fltes Adptve dgtl fltes e dffcult becuse pesece of log feedbck loop look hed tsfom leds to pohbtvely lge hdwe ovehed ote tht look hed tsfom mts exct putoutput mppg sce coeffcets of the dptve fltes cotue to chge exct put-output mppg s ot ecessy dptve flte mesuemet dexes ms-djustmet eo dptto tme costt VLSI DSP Y.T. Hwg 9-69 Ppeled Adptve Dgtl Fltes Relxed look-hed tsfom ms to ppele dptve flte wth lttle hdwe ovehed d t the expese of mgl degdto of dptto behvo poduct elxto sum elxto dely elxto the dptto behvo of the ppeled dptve fltes should be lyed usg stochstc techques VLSI DSP Y.T. Hwg 9-7

36 VLSI DSP Y.T. Hwg 9-7 Relxed Look Ahed Relxed Look Ahed Cosde the st ode tme vyg ecuso yyu, whee coeffcet s tme vyg usg look hed tsfom fo 4, the teto peod s lmted to T m T /4 ude cet ccumstces, we c substtute ppoxmto expessos to smplfy the tems the RHS [ ] u u j y y j VLSI DSP Y.T. Hwg 9-7 Relxed Look hed Tsfom Relxed Look hed Tsfom A 4-level look hed ppeled st ode

37 VLSI DSP Y.T. Hwg 9-7 Poduct Relxto Poduct Relxto Assumptos s close to d -ε, whee ε s close to eo f u s close to eo, the N ε ε [ ] j u y y u u j VLSI DSP Y.T. Hwg 9-74 Poduct Relxto Poduct Relxto A 4-level poduct elxed lookhed ppeled st ode ecuso

38 VLSI DSP Y.T. Hwg 9-75 Poduct Relxto Poduct Relxto Aothe ppoxmto s ssumed to be close to j u y y j VLSI DSP Y.T. Hwg 9-76 Sum Relxto Sum Relxto If the put u ves slowly ove cycles f u s close to eo, the u u [ ] u y u u j y y j u y y

39 Sum Relxto A 4-level sum-elxed look-hed ppeled stode ecuso VLSI DSP Y.T. Hwg 9-77 Dely Relxto Cosde the ecuso yy-u -level look-hed ppeled veso y y u dely elxto volves the use of delyed put u- d delyed coeffcet - ssume the poduct u s moe o less costt ove smples esoble ssumpto fo sttoy o slowly vyg poduct u y y ' u ' VLSI DSP Y.T. Hwg 9-78

40 VLSI DSP Y.T. Hwg 9-79 Commets of elxto techques Commets of elxto techques Thee elxto techques c be ppled dvdully o dffeet combtos to deve ch vety of chtectues ech deved chtectue hs dffeet covegece chctestcs the elxed look-hed s tsfom the stochstc sese VLSI DSP Y.T. Hwg 9-8 Ppeled LS Adptve Flte Ppeled LS Adptve Flte LS lgothm ecusve loops the LS chtectue weght updte loop eo feedbck loop dect look hed s the dely the weght updte loop ˆ U e W W U W d d d e T μ U e W U e W W μ μ

41 VLSI DSP Y.T. Hwg 9-8 Ppeled LS Adptve Flte Ppeled LS Adptve Flte By dely elxto ssume the gdet estmte eu ves slowly the hdwe complexty s N - ACs futhe sum elxto tkg oly the fst sum tems, whee U e W U e W W μ μ ] [ ' U U e W d U W d e T T μ VLSI DSP Y.T. Hwg 9-8 Ppeled LS Adptve Flte Ppeled LS Adptve Flte Assume μ s suffcetly smll d eplcg W- - by W- U W d e T