Integrating Reliability into the Design of Power Electronics Systems

Transcription

1 Integrating Reliability into the Design of Power Electronics Systems Alejandro D. Domínguez-García Grainger Center for Electric Machinery and Electromechanics Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign IEEE Rock River Valley Section Meeting Rockford, IL January 29, / 24

2 Outline Introduction Simulation-Based Reliability Analysis A Set-Membership Framework for Reliability Analysis Concluding Remarks 2 / 24

3 The Impact of New Technologies Figure: Static VAR compensator. Figure: Photovoltaic cells. Figure: Off-shore wind farm. The grid is experimenting a big transformation as new energy processing technologies are being integrated. This integration poses new challenges for ensuring system reliability Management of renewable energy resource intermittency. Impact of individual component reliability. 3 / 24

4 The Role of Power Electronics scheduled maintenance fault occurrence AC Fault DC DC AC system is UP system is DOWN time period the system is out of commission, unless unscheduled maintenance action is taken Figure: Single-string power architecture for wind applications. scheduled maintenance fault occurrence Figure: Off-shore wind farm. Fault AC AC DC DC DC DC AC AC system is UP system is UP time if appropriately designed, the system will remain operational until next scheduled maintenance Figure: Power architecture with added redundancy for reliability and fault-tolerance. Power electronics is common to all these technologies. Reliable Power electronics is key to ensure reliability of these new technologies and understand their impact on the grid. Current power electronics analysis and design techniques do not integrate reliability considerations. 4 / 24

5 Outline Introduction Simulation-Based Reliability Analysis A Set-Membership Framework for Reliability Analysis Concluding Remarks 5 / 24

6 Overview Different fields, different names Computer engineering: fault injection experiment Nuclear engineering: event sequence simulation Power systems: adequacy assessment simulation Conducted through statistically processing observations collected in a simulation-based experiment A model of the system (including component failure behavior) is implemented in a computer. The sample space of the experiment is composed by all possible combinations of component faults and system inputs. The experiment consists of observing the system response to each fault/input pair. 6 / 24

7 Envelope of Performance i in i out v out power converter v max v in load v out v min Figure: Generic power converter. Uncontrolled inputs reflect operational uncertainty: v min in v in v max in, i min out i out i max out. (1) Performance requirements: i min i in i max, v min v out v max. (2) i min i max i in Figure: Envelope of all steady-state limit cycles before any fault occurrence. The performance envelope can be mapped out through exhaustive time-domain simulation. By pickingµ 1 values of the input voltage v in andµ 2 values of the load current i out, the number of simulations needed isµ 1 µ 2. 7 / 24

8 Fault Coverage i in Fault i out v out v max power converter v in load v out v min Figure: Faulty generic power converter. i min i max Figure: Envelope of all steady-state limit cycles after a fault. i in For each fault, we need to check if the performance requirements are met. Fault coverage is a probabilistic measure of the ability of a system to meet performance requirements after a fault. Fault coverage can be obtained through exhaustive simulation of the converter response for all possible combinations of inputs v in and i out. For simplicity, if we assume all combinations of v in and i out are equally probable, then fault coverage for a particular fault i is obtained as: n f c i =, (3) µ 1 µ 2 where n f is the number of combinations of v in and i out that result in the converter still meeting performance requirements. 8 / 24

9 Overall Reliability In order to obtain overall converter reliability, the fault coverage c i for each fault i is included in a Markov reliability model. Converter reliability R can be obtained by covered fault uncovered fault different outcomes for same fault Figure: Markov reliability model. R= n p g i, (4) i=1 where p g 1, pg 2, pg n are the probabilities of the green states in the Markov reliability model. It is clear that the number of simulations needed to obtain the overall converter reliability is ρ µ 1 µ 2, (5) whereρis the number of possible faults,µ 1 is the number of possible input voltage values andµ 2 is the number of load current values. This method is computationally very expensive and not analytically tractable. 9 / 24

10 Outline Introduction Simulation-Based Reliability Analysis A Set-Membership Framework for Reliability Analysis Concluding Remarks 10 / 24

11 Objectives Introduce a unified reliability and dynamic performance analysis framework for power electronics systems design: 1. Analytically tractable. 2. Less computationally expensive that simulation-based methods. 3. Dynamic performance analysis based on linear-time-invariant systems reachability techniques. 4. Reliability analysis based on Markov modeling. 11 / 24

12 Design Specifications Output voltage tolerance ( V): v out V out 0.025V out, (6) i out where V out = 1.2 V. Load range (0 40 A): v in power converter architecture? load v out i load I m I m, (7) where I m = 20 A. Input voltage variation (4 6 V): v in V in 0.2V in, (8) Figure: Generic power converter. where V in = 5 V. The converter must tolerate any first component fault. The switch ratings will impose additional requirements. 12 / 24

13 Dual-Redundant Architecture SW 1 L 1 i 1 Si 1 i out SW 2 L 2 i 2 Si 2 S v1 S v2 v in D 1 D 2 C 1 v C out 2 load controller The single fault-tolerance requirement imposes the need for redundancy. Two buck converters with load-sharing are arranged in parallel. Full-state feedback control is implemented: [d 1, d 2 ] = K[i 1, i 2, v out ], (9) where K is a 2-by-3 constant matrix and d 1 and d 2 are the duty ratios of switches SW 1 and SW 2. The current measurement devices denoted by S i1 and S i2 are abstractions of possible current measurement techniques used in dc-dc conversion. The controller will use the average of both voltage sensor measurements. 13 / 24

14 Small-Signal Model V in d 1 D 1 V in V in d 2 D 2 V in R L R L L L K i 1 i 2 Si 2 Si 1 Sv 1 C Sv 2 C i out v out Figure: Small-signal equivalent circuit. load State-space representation: where: d x dt = A c x+b d w, w Ω w ={ w : wq 1 w 1}, (10) x=[ĩ 1, ĩ 2, ṽ out ] : small variations around the nominal point, w=[ṽ in, ĩ out ] : small variations of uncontrolled inputs, R L L + k 11 V in L k 12 V in L 1 L + k 13 V in L D 1 L 0 A c = k 21 V in L 1 2C R L L + k 22 V in L 1 L + k 23 V in L 1 2C 0 [ 4 10 Q= 2 Vin Im 2 ]., B d = D 2 L C, 14 / 24

15 Performance Requirements By picking a switch rating of 50%, and by considering the output voltage tolerance specification (1.17 V 1.23 V), the values of ĩ 1, ĩ 2 and ṽ out are constrained to the region of the state spaceφdefined by Φ=[ 22 A, 22 A] [ 22 A, 22 A] [ 1.17 V,+1.17 V], (11) We need to choose appropriate values for the converter design parameters such that (11) is satisfied. V in d 1 D 1 V in V in d 2 D 2 V in R L R L L L K i 1 i 2 Si 2 Si 1 Sv 1 C Sv 2 C i out v out Figure: Small-signal equivalent circuit. load Table: Dual-redundant converter parameters (50% switch rating). R L [Ω] L [H] C [F] 10 4 k 11 = k 21 [A 1 ] 200 k 12 = k 22 [A 1 ] 200 k 13 = k 23 [V 1 ] D 1 = D / 24

16 Non-Faulty Behavior V out [V] Envelope of all steady state limit cycles i 1 +i 2 [A] Figure: Ellipsoid bounding the set of reachable states. The values of the state variables x are contained in the so-called reachability setr. The shape ofris usually not easy to compute, but it is possible to compute an ellipsoidal outer bound of the form Ω x ={ x : x Ψ 1 x 1}. (12) Ψ can be analytically obtained by solving A c Ψ+ΨA c +βψ+ 1 β B dqb d = 0, (13) withβ>0, andψpositive definite. The choice ofβis not unique and it will determine how tight is the ellipsoid. 16 / 24

17 Optimality Criteria to Choose β Minimum Volume Ellipsoid: Minimum Trace Ellipsoid: β= β= 1 n tr[ψ 1 BQB ] (14) tr[bqb ] tr[ψ] (15) Ellipsoid of Minimum Projection in a Given Direction v: v β= BQB v v ψv Tight Ellipsoid in a Given Direction v: v β= e At Qe A t v v e At ψv (16) (17) 17 / 24

18 Behavior After a First Fault After a fault in one of the converter components occur, one or both matrices A c, B d might be altered, resulting in a new pair  c, ˆB d. The ellipsoid that contains the values of the state variables will now be defined by ˆΩ x ={ x : x ˆΨ 1 x 1} where ˆΨ is obtained by solving with ˆβ>0and ˆΨ positive definite.  c ˆΨ+ ˆΨ c+ ˆβ ˆΨ+ 1ˆβ ˆB d Q ˆB d = 0, (18) 1.24 Envelope of all steady state limit cycles 1.24 Envelope of all steady state limit cycles V out [V] 1.2 V out [V] i 2 [A] i +i [A] 1 2 Figure: Ellipsoid bounding the set of reachable states after a fault in a switch (50% Switch Rating). Figure: Ellipsoid bounding the set of reachable states after a fault in a capacitor. 18 / 24

19 Fault Coverage After each fault, it is necessary to assess the extent to which the new ellipsoid ˆΩ x is contained in the regionφdefined by the requirements. This will define a probability measure of the reliability of the converter for a particular fault commonly referred to as fault coverage. Loosely speaking, fault coverage is the probability that, given a fault has occurred, the converter state variables are contained in the region Φ: c=pr{ X Φ X ˆΩ x }, (19) where ˆX is a random variable associated with the converter small-signal model state variables x=[ĩ 1, ĩ 2, ṽ out ]. x 2 x 1 Figure: Graphical interpretation of fault coverage. 19 / 24

20 Fault Coverage i out, i 1 +i 2 t Figure: A realization of the load current i out and the sum of the corresponding currents through the inductors i 1 + i 2. The uncertainty model we assumed for the uncontrolled variables allows us to assume the state variables are uniformly distributed over ˆΩ x. The fault coverage is then defined as: c= area( ˆΩ x Φ). (20) area( ˆΩ x ) Table: Fault coverage results for dual-redundant converter with 50% switch rating. Fault event Coverage L 1, L 2, D 1, D 2, SW 1, SW 2, S i1, or S i2 c 1 = 0.63 C 1 or C 2 c 2 = 0.99 {L 1, L 2, D 1, D 2, SW 1, SW 2, S i1, or S i2 } and c 3 = 0.93 {C 1 or C 2 } {C 1 or C 2 } and c 4 = 0.63 {L 1, L 2, D 1, D 2, SW 1, SW 2, S i1, or S i2 } 20 / 24

21 Markov Reliability Model In order to obtain the overall converter reliability, the fault coverage for each fault must be included in a Markov reliability model. Converter reliability R can be obtained by covered fault uncovered fault different outcomes for same fault Figure: Markov reliability model. R= n p g i, (21) i=1 where p g 1, pg 2, pg n are the probabilities of the green states in the Markov reliability model. Converter reliability: R= (22) Converter unreliability: Q= (23) 21 / 24

22 Improved Dual Architecture The design presented did not achieve the single fault-tolerance goal as the coverage of certain first faults is not complete. It is possible to make slightly modifications in the design to achieve fault coverage in all first faults: By increasing the capacitance of the output filter by 20%, i.e., C= F, the coverage of any fault involving a capacitor increases to 1. By increasing the switch rating to 95%, the coverage of any fault involving a switch, a diode, an inductor, or a current measuring devices also increases to 1. With this new fault coverage parameters, the converter reliability and unreliability estimates results in: R= , Q= (24) The improved design not only meets the single fault-tolerance requirement, but it is three orders of magnitude more reliable than the original design. 22 / 24

23 Triple-Redundant Architecture The single fault-tolerance requirement can be also achieved by adding a third buck converter, with a switch rating of only 50%. The reliability and unreliability estimates of this architecture are: R= , Q= , (25) which is slightly worse but in the same order of magnitude that the reliability of the dual architecture with 95% switch rating. The triple architecture is only 50% oversized (in terms of current rating), whereas the dual architecture is 100% oversized, which might make the cost of the dual architecture higher than the cost of the triple architecture. Under these circumstances, it is possible to set up an optimization problem which would help to determine which architecture is optimal when the cost function includes reliability and cost. 23 / 24

24 Outline Introduction Simulation-Based Reliability Analysis A Set-Membership Framework for Reliability Analysis Concluding Remarks 24 / 24

25 Summary We proposed an analytically tractable methodology for analyzing reliability of power electronics systems. The proposed methodology alleviates the computational burden of other techniques based on time-domain simulations. The analytical tractability of the solutions gives insight on the influence of design parameters on the overall system reliability and performance. In future work, we will explore the formulation of the methodology using a large-signal model of the system. 25 / 24