High power IGBT-based DC/DC converter with DC fault tolerance

Transcription

1 High power IGBT-based D/D converter with D fault tolerance D. Jovcic, Senior Member, IEEE, and J. Zhang Abstract--This paper studies a D/D converter based on IGBT-bridges which is suitable for connection to HVD (High Voltage D) and for building high power D grids. The D faults are of highest concern for D grids, and the primary converter design aims are to achieve inherent current regulation under D faults in addition to minimizing converter losses. Design studies show that a range of converter parameters exist which will give fault D current magnitudes close to rated currents. It is shown that it is possible to have controllable operation even for worst case D faults at either of the D terminals. The results are confirmed using detailed PSAD simulation on a 500MW 00kV/600kV D/D test converter. Index Terms-- D-D power conversion, IGBT converter, High Voltage D transmission. I. INTRODUTION In recent years, there has been significant interest for advancing HVD technology to multiterminal connections and to meshed D grids []. The development of D grids will require further progress in two key high power components: D circuit breaker (B) and D transformer. A D B can isolate a faulted line. A D transformer can transform D voltage levels to achieve optimum costs and losses. The D fault isolation is the most serious challenge in developing D grids [-4]. The fault protection is much more difficult with D grids than A grids for the following reasons: ) there is no zero crossings of D fault current, ) the series impedance (with VS-based converters) is very small causing a sharp rise of fault current, 3) interrupting large D current causes severe overvoltages, and 4) the equipment is usually more sensitive to overvoltages and overcurrents. The D grids will require a D B on each side of each D cable [3]. However, it is very challenging to develop D B that can interrupt extreme currents in very fast time. Some semiconductor-based D Bs have been developed [4] but their cost is high, and the performance is limited. The market demand for high-power D-D connection has been significantly increased considering the proliferation of D power sources. The number and rating of D power sources, like fuel cells, photovoltaics, wind farms and energy storage elements are increasing significantly in recent years [5]. These D power sources would ideally be connected to This project is funded by European Research ouncil under the Ideas program in FP7; grant no 5938, 00. The authors are with the School of Engineering, University of Aberdeen, Aberdeen, AB4 3UE, U.K.(d.jovcic@abdn.ac.uk, jianxi.zhang@abdn.ac.uk). D grids at medium and high voltage. Furthermore, highpower D/D conversion will be required to provide connection between medium voltage and high-voltage D grids and to match D voltage levels in various countries (with different standards) and to connect equipment from different manufacturers. The D/D converters in high-power applications should have good D fault responses. If properly developed they will also be operating as D circuit breakers, capable of isolating the two D grids or cables. However it is difficult to retain controllable converter operation under high-voltage D faults. The HVD VS converters are normally tripped in case of D faults in order to prevent IGBT switch overcurrent [3]. The inherent properties of some D/D converters under D faults have been studied recently [6,7]. It is demonstrated that a carefully designed LL circuit can regulate the power flow automatically: a voltage depression on one side leads to current reduction on the opposite side [7]. This method has some significant benefits: ) inherent power reduction which does not depend on protection circuits, ) considerably lower cost of LL components compared with semiconductors, 3) the capability to maintain converter control even during the worst case faults. However the topologies in [6,7] are based on thyristors and suffer a range of limitations like low switching frequency a and variable frequency control. This paper studies a D/D converter topology which includes a passive LL circuit between two IGBT-based bridges. The objective is to develop a high power VS D/D converter which inherently limits the fault current and maintains full control under faults on either of the D terminals. The article discussed the converter design principles, compares it with a traditional D/D converter and confirms the results using detailed PSAD simulation. II. LL D/D ONVERTER DESIGN A. onverter topology The proposed IGBT-based D/D converter topology is shown in Figure a). The converter comprises of a passive LL circuit and two square-wave controlled VS converters. Figure b) shows the simplified model for the inner A system. It is known that an IGBT bridge is uncontrollable (becomes a diode bridge) under D faults. We therefore aim to develop the inner A circuit that will prevent fault propagation from one bridge to another. More specifically, if an inner A voltage falls to zero, the currents should be maintained close to rated values.

2 S S 3 S 5 S 7 in figure. We can position the coordinate frame arbitrarily and without loss of generality V ac is located on d-axis (α 0): V I Idc g g I ac L V ac Vc I ac L V ac I dc I V V ac V acd V acm, V acq 0 (9) The basic LL circuit equations are: V g g L L V j I ac V ac V c (0) jωv c I ac + I ac () j I ac V ac V c () S 4 V ac (a) L L (b) Figure. (a) IGBT-based D/D converter. (b) A simplified model of the inner A system. B. LL ircuit Equations and ontrollability The LL circuit is viewed as a power network with input connection (V ac and I ac ) and output connection (V ac and I ac ). The A voltage vectors V ac and V ac are expressed as: V ac V acm α V acd + jv acq () V ac V acm α V acd + jv acq () where V ac, V ac are the phasors, V acm, V acm are the magnitudes and α, α are phase angles of respective voltages. The subscripts d and q denote corresponding phasor components. In this topology, both the converter voltages V ac and V ac are controllable. The converter line-neutral RMS voltage V ac is: V acd 4V π 4V π m cos α 4V π d (3) V acq 4V π 4V π m sin α 4V π q (4) M m M d + M q sin γ similarly for voltage V ac : V acd 4V sin γ cos α π 4V M π m cos α 4V M π d (6) V acq 4V sin γ sin α π 4V M π m sin α 4V M π q (7) M m M d + M q sin γ S I ac L where M d, M q, M d, M q are D-Q components of control signal, γ is pulse width, and V, V are D voltages as defined Vc I ac L S 8 V ac S 6 (5) (8) where ω πf, and f is the switching frequency. From (0)- () we can express the converter currents and capacitor voltage: I ac V acm ω L V ac jω (L +L ω L L ) I ac V ac ω L V acm jω (L +L ω L L ) V c L V acm +L V acd +j L V acq L +L ω L L We will conveniently rewrite equations (3)-(4) as: (3) (4) (5) I ac V acm k V ac jω k 3 (6) I ac V ac k V acm jω k 3 (7) where: k ω L (8) k ω L (9) k 3 L + L ω L L (0) The above variables k, k and k 3 are conveniently introduced to study converter behavior. Ultimately, we need to determine the three parameters: L, L and, which can be obtained from the three equations (8)-(0). The coefficient k 3 is a positive non-zero constant that is fully determined by the power transfer level. oefficients k and k are manipulated in the design stage, as it is discussed in section D below. Since ω > 0, L > 0, L > 0, > 0, from (8)-(0) we have: k <, k <, k 3 < L + L (). Designing converter for zero reactive power at both terminals Using (6) the A current is: I ac V acq j V acm k V acd () From the above equation, the active power is controlled using M q which manipulates V acq. The condition for zero reactive power at terminal is I acq 0. Therefore from (), we

3 3 operate the converter in such way that: V acm k V acd (3) Replacing (9), (3) and (6) in (3), the control law for zero reactive power at low-voltage bridge is obtained as: M d V M d V k (4) On the high voltage side, using (7): I ac V acq k + j V acm V acd k (5) Using () and (5) we can obtain the condition for zero reactive power at terminal as: V acd V acm V acd k V acq k 0 (6) Replacing (9), (3), (6), (7) and (3) in (6): M q V k M d V k M d V k (7) The control law for zero reactive power at high-voltage bridge is obtained as: where p is the number of phases (p in Figure ). Replacing (), () in (33), we obtain active and reactive power: V P ac pv acq acm (34) V Q ac pv acm k V acd acm (35) For assumed k and given P ac, Q ac, V and V (rated values), we can obtain k 3 from (34) and (35). F. Design for D Fault on Low Voltage Side We assume that the converter is operating at full power just prior to the fault. We study inherent converter response and assume that the controller is inactive during faults. We are interested in D faults, which in extreme conditions imply V V ac 0. In order to simplify study, and without loss of generality, we assume that the converter is designed for Q 0. From (3) we know rated d component of converter voltage V acrd V acrm k, where subscript r denotes rated values. The converter currents under extreme fault on V ac can be obtained from (6) and (7) by replacing V acm 0. Therefore the magnitude of low voltage side fault current I acf m is: I acf m V acm (36) M d M q (8) kk The magnitude of fault current relative to the rated current can be obtained by dividing (36) with (5): From the above equation we obtain the angle of voltage V ac : α tan M q M d tan k k (9) I acf m I acrm V acm V acm Vacm k s k This equation poses the maximum limit on k : (37) D. Selecting k The parameter k is selected to provide maximum M m and M m at maximum power transfer: M m M m (30) Using (4) and (7): s < k < s (38) With controllable IGBT bridges, it is normally allowed to have the transient fault current within two times the rated current, considering that the controller will ultimately reduce the A-side currents. Equating (37) with, we obtain more practical limit on k : M q V k M d V k M d V k (3) Replacing (30) in (3): 3 < k s < 3 s The magnitude of fault current I acf m is from (6): (39) k k V /V k s (3) where s is the stepping ratio s V V <. E. alculating k 3 In general case the complex power can be calculated as: S ac pv ac I ac pvac ( V ac k V ac jω k 3 ) (33) I acf m V acm k (40) Dividing (40) with (6) and using (3) the magnitude of fault current relative to the rated current will be: I acf m I acrm /(s k ) (4)

4 Vcfm/Vcrm Iacfm/Iacrm Iacfm/Iacrm K 4 Equating (4) with, we obtain one additional limit on k : 5s < k < 5s (4) Maximum values Minimum values onsidering (0), (38), (39) and (4), we should select k in the limit: 3 < k s < min ( 3, ) (43) s Figure shows the maximum and minimum values for k versus a range of stepping ratios s (0.5 < s < ). In the special case s, which is unlikely in practice, the range for k is most limited (-0.866< k <0.866). The magnitude of fault voltage on capacitor relative to the rated value can also be obtained in same way using (5): V cf m V crm +(τ +k τ)s (44) where τ L L k k. Figure 3 shows the above relative fault current and capacitor voltage magnitudes in equations (37), (4) and (44) for a range of stepping ratios s ( 0.5 < s < ). The curves for three different k are shown in each figure. It is seen from figure 3b) that the high voltage side converter current I acf m under V fault will be close to or below the rated value for all k values in the limit. If k is positive, the worst case happens with stepping ratio close to and large k. In such case the fault current can approach times the rated value of current, but this fault current can be readily controlled by the converter. The fault current I acf m also stays close the rated value for V fault. The capacitor voltage V cfm will be below the rated value for positive k. If k is negative, the fault currents and capacitor voltage are still close to the rated value. G. Fault on High Voltage Side The converter currents under extreme fault on V ac can be obtained from (5) and (6) by replacing V ac 0. The magnitude of fault current I acf m is: I acf m V acm k (44) Dividing (44) with (5), the magnitude of fault current relative to the rated current will be: I acf m I acrm /(s k ) (45) Figure. The recommended range for k versus stepping ratio s (a) (b) k0.86 k0.05 k k0.86 k0.05 k -0.8 k0.86 k0.05 k (c) Figure 3. Ratio of fault currents over rated values: (a) I acfm/i acrm. (b) I acfm/i acrm and ratio of capacitor voltage over rated values: (c) V cfm/v crm versus stepping ratio s after V fault. The magnitude of fault current I acf m is from (6): I acf m I acrm s k (47) I acf m V acm (46) Dividing (46) with (6), the magnitude of fault current relative to the rated current will be: Equations (45) and (47) are identical to (4) and (37), but terminal labels are reversed. This is expected result considering that the converter is symmetrical. The magnitude of fault capacitor voltage relative to the rated value is obtained from (5):

5 Vcfm/Vcrm 5 V cf m V crm τs +(τ +k τ)s (48) Figure 4 shows that the capacitor voltage V cfm under V fault will also be below the rated value for positive k. If k is negative, the capacitor voltage is still below or close to the rated value. onsidering the faults, we conclude that best responses are obtained for k close to zero, however there is still very broad range of k which gives acceptable fault currents, i.e. magnitudes comparable with rated values. A high magnitude negative value for k gives L >L which might be desired in some cases in order to reduce current harmonics on I. A high positive value of k will give LL resonant frequency away from the switching frequency which might be desired for good dynamic properties. In order to simplify study, we assume that the converter is designed for zero reactive power at terminal I aclq 0. So we operate the converter to minimize reactive power flow: V aclm V acld (50) Using (49) and (50), the power control equation is obtained: I acm V aclq (5) The converter current under extreme fault on V ac can be obtained from (49) by replacing V aclm 0. Therefore the magnitude of fault current I aclf m is very large: I aclf m V aclm (5).6.4. k0.86 k0.05 k-0.8 The magnitude of fault current relative to the rated current can be obtained by dividing (5) with (5): I aclf m I aclrm V aclm V aclq (53) The converter current under extreme fault on V ac can be obtained from (49) by replacing V acl 0. The magnitude of fault current I aclf m is therefore very large, limited only by L: Figure 4. Ratio of fault capacitor voltage over rated values V cfm/v crm versus stepping ratio s after V fault. III. OMPARISON WITH L-VS ONVERTER The conventional dual active bridge D/D converter with an internal A-transformer is shown in Figure 5. Without loss of generality we assume that stepping ratio is. The basic circuit equation is: I acl V aclm V acl jωl V V I Idc g g g S V aclq g S 3 Vac j V aclm V acld Vac S 5 S 7 I dc I (49) V V I aclf m V aclm (54) Dividing (54) with (5), the magnitude of fault current relative to the rated current will be: I aclf m I aclrm V aclm V aclq (55) According to (50), V aclq is very small and V aclm is similar to V acm. Therefore the ratios (53) and (55) are typically very large and cannot be readily reduced. By increasing L the fault current can be somewhat reduced but with a range of other negative consequences. With conventional dual active bridge the fault scenario becomes major design restriction. Although each bridge can control steady-state A fault current, in first few milliseconds after a fault the current will be large and component overrating is required. Furthermore, converter in Figure is much simpler to expand into a multiterminal topology compared with converter in Figure 5. S 4 S S 8 S 6 V ac (b) Figure 5. (a) onventional D/D converter with a transformer. simplified L-circuit model (a) I acl L V ac (b) A IV. PSAD SIMULATION The results shown in Figures -4 are generic and apply for all converters from this family. A 500MW test system is developed and parameters are given in table in the Appendix. Figure 6 shows the detailed PSAD simulation of worst case fault on V. In agreement with theoretical study in Figure 3a), the magnitude of steady fault current I ac is very close to the rated value. There is some transient increase of I ac, which is caused by D fault component, but this can be tolerated by the diodes. The steady fault magnitudes of I ac and V c reduce

6 6 to around 8% and 55% of the rated values respectively which are also matching the theoretical results in Figure 3b) and 3c). V. ONLUSIONS This article presents a D fault tolerant high power D/D converter suitable for connection with HVD systems. The theoretical analysis develops the control laws that provide zero reactive power at each of the two IGBT bridges. A further study considers the converter design under extreme fault conditions. It is concluded that there exists a wide range of converter parameters that give fault current magnitudes close to rated currents even for most severe faults at either of the terminals. The PSAD simulation on detailed models confirms the theoretical design study. VI. APPENDIX Table. Test system data Given parameters Value Active Power P ac 500 MW D voltage V 00 KV D voltage V 300 KV Switching frequency f 500 Hz alculated parameters Value (for k -0.8, k ) Phase angle α degree Inductance L 0.07 H Inductance L H apacitance.053 µf VII. REFERENES [] D. Van Hertem, M. Ghandhari, J.B. uris, O. Despouys, A. Marzin, " Protection requirements for a multi-terminal meshed D grid", Proc, IGRE 0 Bologna Symposium, Bologna, Italy, paper 8. [] Baran, M.E., Mahajan, N.R.: Overcurrent protection on voltagesource converter-based multiterminal D distribution systems, IEEE Trans. Power Deliv., 007,, (), pp [3] L. Tang, B. Ooi, Locating and Isolating D Faults in Multi-Terminal D Systems, IEEE Transactions on Power Delivery, Vol., Issue 3, Jul. 007, pp [4] J. Hafner, B, Jacobson, Proactive Hybrid HVD Breakers - A key innovation for reliable HVD grids, Proc, IGRE 0 Bologna Symposium, Bologna, Italy, paper 64. [5] Jovcic, D. "Off shore wind farm with a series multiterminal SI HVD", Electric Power Systems Research, 008, 78, (4), pp [6] D. Jovcic, Bidirectional, High-Power D Transformer, IEEE Transactions on Power Delivery Vol. 4, Iss. 4, Oct. 009, pp [7] D. Jovcic, B. T. Ooi Theoretical aspects of fault isolation on highpower D lines using resonant D/D converters IET Generation, Transmission and Distribution, Vol. 5, issue, Feb. 0, pp Figure 6. PSAD simulation of converter response after a D fault on V (k 0.8) VIII. BIOGRAPHIES Dragan Jovcic (S 97, M 00, SM 06) obtained a Diploma Engineer degree in ontrol Engineering from the University of Belgrade, Yugoslavia in 993 and a Ph.D. degree in Electrical Engineering from the University of Auckland, New Zealand in 999. He is currently a Reader with the University of Aberdeen, Scotland where he has been since 004. He also worked as a lecturer with University of Ulster, in the period and as a design Engineer in the New Zealand power industry in the period His research interests lie in FATS, HVD, integration of renewable sources and control systems. Jianxi Zhang obtained a Bachelor s degree in Automation from Huazhong University of Science and Technology, Wuhan, hina in 008 and a Master s degree in ontrol Systems from University of Sheffield, UK in 009. He is currently studying towards his Ph.D. degree at the University of Aberdeen, Scotland. His research interests are in power electronics and control systems engineering.