Interconnect Design for Deep Submicron ICs

Transcription

1 ! Intrconnct Dsign for Dp Submicron ICs Jason Cong, Zhigang Pan, Li H, Chng-Kok Koh and Ki-Yong Khoo Computr Scinc Dpartmnt Univrsity of California, Los Angls, CA 005 Abstract Intrconnct has bcom th dominating factor in dtrmining circuit prformanc and rliability in dp submicron dsigns. In this mbddd tutorial, w first discuss th trnds and challngs of intrconnct dsign as th tchnology fatur siz rapidly dcrass towards blow 0.1 micron. Thn, w prsnt commonly usd intrconnct modls and a st of intrconnct dsign and optimization tchniqus for improving intrconnct prformanc and rliability. Finally, w prsnt comparisons of diffrnt optimization tchniqus in trms of thir fficincy and optimization rsults, and show th impact of ths optimization tchniqus on intrconnct prformanc in ach tchnology gnration from th 0.35 to 0.07 projctd in th National Tchnology Roadmap for Smiconductors. I. INTERCONNECT TRENDS AND CHALLENGES Th driving forc bhind th imprssiv advancmnt of th VLSI circuit tchnology has bn th rapid scaling of th fatur siz, i.., th minimum dimnsion of th transistor. It dcrasd from m in 185 to m in 16. According to th National Tchnology Roadmap for Smiconductors (NTRS) [1], it will furthr dcras at th rat of 0.7 pr gnration (consistnt with Moor s Law) to rach m by Tabl I lists th main charactristics of ach tchnology gnration in th NTRS. Such rapid scaling has two profound impacts. First, it nabls much highr dgr of on-chip intgration. Th numbr of transistors pr chip will incras by mor than 2 pr gnration to rach 800 millions in th m tchnology. Scond, it implis that th circuit prformanc will b incrasingly dtrmind by th intrconnct prformanc. Th intrconnct dsign will play th most critical rol in achiving th projctd clock frquncis in th NTRS. This papr prsnts th trnds and challngs of intrconnct dsign in currnt and futur tchnologis and discusss th availabl solutions. In ordr to bttr undrstand th significanc of intrconnct dsign in th futur tchnology gnrations, w prformd a numbr of xprimnts basd on th intrconnct paramtrs providd in th NTRS as shown in th bold fac in Tabl II. Sinc th NTRS paramtrs ar for th first mtal (M1) layr only, which is usually not suitabl for Tch. ( m) Yar # transistors 12M 28M 64M 150M 350M 800M (MHz) Ara (mm ) Wiring lvls TABLE I Summary of NTRS [1] cong@cs.ucla.du This work is partially supportd by th NSF Young Invstigator Award MIP and a grant from Intl undr th California MICRO Program. Tch Mtal 1 Intrconnct " # $ % $'& % 1.5:1 2:1 2.5:1 3:1 3.5:1 4:1 $)( 2.5:1 3:1 3.5:1 4.2:1 5.2:1 6.2:1 Mtal 4 Intrconnct " # $ Mtal 4 with min. spacing and width +* -, / Mtal 4 with 01 min. spacing and 01 min. width * , / " # TABLE II Intrconnct paramtrs. and ar th minimum width and spacing in $ m, rspctivly. and ar th unit-lngth rsistanc and total capacitanc in 2435 m and % $ & m, rspctivly. +*, % $)( and /. ar th aspct ratios of th mtal and via, rspctivly., and ar th ara, fring and coupling capacitancs pr unit lngth in ff/ m, rspctivly. ): ; = Tch : $ TABLE III Dvic paramtrs. and ar th input capacitanc in ff and output rsistanc in k2 of an unit-sizd gat, rspctivly. >. is th intrinsic dlay of a gat in ns. global intrconncts, w also drivd th intrconnct paramtrs for th M4 layr,? which ar also shown in Tabl II. Furthrmor, w drivd a st of dvic paramtrs as shown in Tabl III basd on th data on procsss and dvic in th NTRS. Using ths sts of paramtrs, w carrid out xtnsiv simulations using HSPICE to quantitativly masur th intrconnct prformanc and rliability in futur tchnology gnrations and obtaind th following rsults: (1) Intrconnct dlay is clarly th dominating factor in dtrmin-? W assum that th minimum width and spacing of M4 is 2.5 tims thos of M1. Th aspct ratios % $ & and % $)( ar usd to dtrmin th mtal thicknss and th dilctric thicknss for all layrs. For M1, w assum that th substrat and M2 ar th ground plans; and for M4, w assum that M3 and M5 ar th ground plans. Th total capacitanc, including th ara capacitanc, fringing capacitanc, and coupling capacitanc componnts, ar obtaind using th 3D fild solvr FastCap [2]. Basd on ths assumptions, our capacitanc valus for M1 closly match thos givn in th NTRS.

2 W Z \ Dlay (ns) mm lin 2cm lin Intrinsic gat dlay Lmax (um) % Vdd 1x 15% Vdd 1x 10% Vdd 2x 15% Vdd 2x Tchnology (um) Fig. 1 Global and local intrconnct dlays vrsus gat dlays. Cx/Ctot x 1x Tchnology (um) Fig. 2. Ratio of coupling capacitanc to total capacitanc of M4 intrconnct with th minimum width and spacing (B1 ) and two tims th minimum width and spacing (01 ). ing th circuit prformanc. As shown in Fig. 1, as w advanc from th 0.35 m tchnology to th 0.07 m tchnology, th intrinsic gat dlay dcrass from ovr 100 ps to around 10 ps, th dlay of a local intrconnct (1 mm) dcrass from ovr 150 ps to around 50 ps, whil th dlay of a global intrconnct (2 cm) incrass from around 1 ns to ovr 6 ns. Clarly, aggrssiv intrconnct optimization is ndd in ordr to achiv th clock frquncis projctd in Tabl I. In Sction IV, w shall show how various xisting intrconnct optimization tchniqus will limit th growth of intrconnct dlays. (2) Th coupling capacitanc btwn adjacnt lins will b a major componnt in th total capacitanc du to th incras of wir aspct ratio and th dcras of th lin spacing. But its valu is vry snsitiv to spacing. As shown in Fig. 2, th ratio of th coupling capacitanc to th total capacitanc for a wir on M4 with th minimum spacing to its two nighbors incrass from around 40% to around 70% whn th tchnology progrsss from 0.35 m to 0.07 m. Whn w incras th spacing to two tims th minimum, th sam ratio bcoms from around 15% to around 40% for diffrnt tchnology gnrations. Thrfor, propr spacing is vry important in dp submicron intrconnct dsigns. (3) Th coupling nois btwn adjacnt wirs will bcom a important factor in dp submicron dsigns du to th incras of coupling capacitanc. Our xprimntal rsults in Fig. 3 shows that if w rstrict th pak nois valu to b CDFE GIH8H, th maximum allowabl lngth on M4 using th minimum spacing dcrass from ovr 4000 m to almost 500 m whn th tchnology progrsss from 0.35 m to 0.07 m. Th sam figur also shows th wir lngth Both sts of intrconnct dlays ar basd on th assumption of th minimum wir width and two tims minimum spacing on M4 with optimal drivr sizing Tchnology (um) Fig. 3. Maximum allowabl lngth (in log scal) for paralll M4 lins with th minimum width and spacing (1 1 ) and two tims th minimum width and spacing (21 ) whn th pak coupld nois is limitd to 10% and 15% of th supply voltag. limits undr two tims th minimum spacing and with CJ E GKH8H pak nois tolranc. Sinc most xisting works hav bn on intrconnct prformanc optimization, this tutorial covrs only th modling and optimization tchniqus for intrconnct dlay minimization. Th rmaindr of this papr is organizd as follows: Sction II discusss commonly usd intrconnct and gat dlay modls for layout optimization. Sctions III prsnts th tchniqus for intrconnct layout dsign and optimization. Sction IV compars a numbr of intrconnct optimization tchniqus in trms of thir fficincy and solution quality and shows thir impact on intrconnct dlay rduction in ach tchnology gnration projctd in th NTRS. Du to th pag limitation, th authors ar abl to prsnt only a small subst of rsults on th topics covrd in this papr. A mor comprhnsiv survy and bibliography is availabl in [3]. A. Intrconnct Modling II. DELAY MODELING In ordr to considr both wir rsistanc and capacitanc and modl th distributiv natur of th intrconncts, a routing tr is usually modld as an RC tr by dividing ach long wir into a squnc of wir sgmnts and modling ach wir sgmnt as an L- typ or L -typ of RC circuit. Th numbr of R, C lmnts can b larg whn th lngth of ach sgmnt is chosn to b small for a bttr approximation of th distributd natur of th intrconncts or a gratr dgr of flxibility in wirsizing optimization. Thrfor, a rducd-ordr RC modl is oftn computd to approximat th larg RC tr using th momnt matching tchniqu. Lt M+NPORQ b th impuls rspons at a nod of a RC tr. Th transfr function STNVUDQ of th circuit, which is th Laplac transform of M+NPORQ, can b rprsntd as STNVUDQXW Y[Z \ M+NPORQ^]_a`^bVHOcW Z dgf N^hiCDQ jrklu Y[Z \ O M+NPORQmHO5 (1) j Th -momnt of th transfr j function is dfind to b th unsignd cofficint of th -th powr of U in Eqn. (1) jrk C Y[Z \ O M+NPORQmHO5 (2) Momnts of an RC tr can b computd fficintly using rcursiv mthods (s [3] for dtails). Th first momnt? Won \ O4pJM+NPOQmHO, also calld th Elmor dlay modl [4], is most commonly usd for dlay stimation in an RC tr. In ssnc, th Elmor dlay modl uss th man of th impuls

3 j ˆ?? O W rspons M+NPORQ to approximat th 50% dlay of th stp rspons (undr th stp input), which corrsponds to th mdian of th impuls rspons. It was shown that th Elmor dlay from sourc U \ to nod in an RC tr can b computd by th following simpl quation [5]: ONVU \Fq j d ~} QrW ; s sut8v * p D Nƒ Q q (3) bxwyz`m{d whr O^M+NVU ; \uq j Q is th uniqu path from sourc U \ j to nod in an RC tr, s is th rsistanc at nod u, and Nƒ Q is th total capacitanc of th subtr rootd at nod. In gnral, th Elmor dlay of a sink in an RC tr givs an uppr bound on th actual 50% dlay of th sink undr th stp input [6]. Th Elmor dlay allows us to xplicitly xprss th signal dlay as a simpl algbraic function of th gomtric paramtrs of th intrconnct (th lngths and widths of wirs), so that it can b asily usd for intrconnct optimization. It was shown that th Elmor dlay modl offrs rasonably good fidlity for intrconnct layout optimization, i.., an optimal or nar-optimal solution obtaind undr th Elmor dlay modl is also clos to optimal according to actual (SPICE-computd) dlays (s [3] for dtails). But th absolut valu of Elmor dlay may not b vry accurat. So, it is not suitabl to b usd dirctly for accurat circuit timing analysis. Highr ordr momnts can b usd for mor accurat rducdordr RC modls. Th Asymptotic Wavform Evaluation (AWE) mthod [7] basd on Padé approximation uss highr ordr momnts to constructs a -pol transfr function S NVUDQ ˆ, calld th rducd-ordr -pol modl, q (4) d~f S NVUDQrW Š ˆ UŒh to approximat th actual transfr function STNVUDQ, whr ar pols and ar rsidus, all of which can b dtrmind uniquly by matching th initial boundary conditions and th first u -hxc momnts of STNVUDQ to thos of S NVUDQ ˆ [7]. Th rspons wavform in th tim domain undr th stp input is givn by d~f M/NPOQrW Š ˆ ]5Ž Vb (5) Th choic of ordr dpnds on th accuracy rquird but is usually much lss than th ordr of th circuit. In practic, is oftn usd. It is difficult, howvr, to rprsnt th pols and rsidus in STNVUDQ xplicitly in trms of dsign paramtrs of th intrconnct in a closd-form xprssion, which maks th momnt-matching mthod difficult to us for intrconnct optimization dirctly. Som dlay mtrics basd on highr ordr momnts, such as th cntral momnts and th xplicit RC dlay using th first thr momnts, ar summarizd in [3]. Not that xcpt for th Elmor dlay modl, which is dfind for a monotonic rspons only, th tchniqus prsntd abov still holds whn intrconncts ar modld as RLC trs. Rcnt progrsss on rducd-ordr modls includ th us of th PVL (Padé Via Lanczos) mthod for Padé approximation without dirct momnt computation [8, ], th congrunc transformations to crat rducd RC ntworks which ar guarantd to b stabl and passiv [10], and th coordinat-transformd Arnoldi algorithm that can b applid to gnral RLC ntwork [11]. Th objctiv of ths algorithms is to ovrcom th numrical instability of th AWE mthod. Snsitivity-basd mthods hav bn proposd to us highr ordr momnts for fast timing analysis to grdily guid th optimization procss to a local optima. t t (a) t t t t (b) (c) C2 Ctotal Fig. 4. (a) An invrtr driving an RC intrconnct. (b) Th sam invrtr driving th total capacitanc of th nt in (a). (c) A -modl of th driving point admittanc for th nt in (a). (d) Th sam invrtr driving th ffctiv capacitanc of th nt in (a). Th input signal has a transition tim of b. B. Drivr Modling In this subsction, w collctivly rfr to gats, buffrs, or transistors as drivrs. W prsnt two commonly usd approachs to modl th drivrs for dlay computation with intrconncts. Th first approach is a switch-rsistor modl comprisd of an ffctiv linar rsistor drivn by a voltag sourc (usually assuming a stp input or rampd input). Th ffctiv rsistanc of a drivr usually dpnds on th transition tim of th input signal, th loading capacitanc, and th siz ; of,d, th drivr. For xampl, on can us a rsistor of fixd valu to modl a drivr by slcting an appropriat capacitanc load and matching th 50% dlay of th drivr driving th load with that of th quivalnt RC circuit ( ;,D, ) undr th stp-input. A mor accurat modl, calld th slop modl, uss a on-dimnsional tabl to comput th ffctiv drivr rsistanc basd on th concpt of ris-tim ratio [12]. It first uss th output load and transistor siz to comput th intrinsic ris-tim of th drivr, which is th ris-tim at th output undr th stp input. Th input ris-tim of th drivr is thn dividd by th intrinsic ris-tim of th drivr to produc th ris-tim ratio of th drivr. Th ffctiv rsistanc is rprsntd as a pic-wis linar function of th ris-tim ratio and stord in a ondimnsional tabl. Givn a drivr, on first computs ;,D, its ris-tim ratio and thn calculats its ffctiv rsistanc by intrpolation according to its ris-tim ratio from th on-dimnsional tabl. Multi-dimnsional tabls can also b usd for computing and storing th ffctiv drivr rsistanc as a function of th input slop, output load, tc. Th switch-rsistor modl has th advantag that th coupling with th intrconnct can b asily modld by including th ffctiv drivr rsistanc in th intrconnct RC tr for dlay and/or wavform computation. But it may b difficult to modl th non-linar bhavior of th drivr. Th scond approach for drivr modling charactrizs th bhavior of a drivr (such as th drivr dlay and th output transition tim) using all rlvant paramtrs of th input signal(s) and th output load. This allows for vry accurat modling, but th gat dlay and th intrconnct dlay must b computd sparatly. For xampl, on can pr-charactriz, th dlay (O ) and output transition tims (O, and OR ) of a drivr in š trms of th input transition tim O and th total b load capacitanc using accurat circuit simulation such as SPICE. Th charactrizd rsults can thn b stord in a look-up tabl whr ach ntry is in th form: JO q q b NPO q O, q O^ DQœ. Such a modl can b vry accurat if on can afford th tim and spac to gnrat a dtaild multi-dimnsional tabl for ach gat. Altrnativly, on can stor th charactrization data much mor compactly in th form of -factor quations [13,14], such as: Nƒ?+ p Q/pO b p O, W Nƒ? p Q/pO b p R t t C1 8žšp ž p (d) Cff Ÿ (6) Ÿ (7) whr?r Ÿ and?r Ÿ ar dtrmind basd on linar rgrssion or last squar fits on th charactrization data.

4 N ; p ; p? C. Dlay Computation In gnral, w ar intrstd to comput th total dlay from th input of a drivr to on of th sinks (an input to a gat in th nxt stag) in its output nt, calld th stag dlay. Whn th intrconnct is modld as a lump capacitanc (Fig. 4(b)) with no intrconnct rsistanc, th computation of th stag dlay is straightforward. Using th switchd-rsistor drivr modl, th stag dlay is simply ; p8n Q (for a stp voltag sourc) whr and ar th load capacitanc and intrconnct capacitanc, rspctivly. Using a pr-charactrizd drivr modl, th stag dlay can b obtaind by tabl look-up and intrpolation or computd from th -factor quations dirctly. Whn a distributd RC intrconnct modl is usd in junction with a switch-rsistor drivr modl, th stag dlay can b asily computd by first constructing a nw RC ntwork that combins th intrconnct modl with th drivr s ffctiv rsistanc and thn comput th dlay through an RC ntwork using th mthods discussd in Sction II.A. This shows th advantag of th switch-rsistor drivr modl whr th intraction btwn th drivr and th intrconnct can b asily modld. Whn a distributd RC intrconnct modl is usd in junction with a pr-charactrizd drivr modl, th drivr dlay and th intrconnct dlay nd to b computd sparatly and addd up togthr to obtain th stag dlay. Morovr, th intraction btwn th drivr and th intrconnct modl should b considrd during th drivr prcharactrization. Sinc a distributd RC intrconnct has many paramtrs, th information usually nd to b comprssd for drivr pr-charactrization. For xampl, th L -modl [15] was proposd to approximat th driving point (i., th output of th drivr) admittanc as shown in Fig. 4(c). Th valus of,? ; and in a L -modl (s Fig. 4(c)) can b computd by? W F q W? ḧ Nx u Q q ; WohINx Q (8) whr,? and ar th first thr momnts of th driving point admittanc, which can b computd rcursivly in a bottom-up fashion, starting from th sinks of th intrconnct tr. In this cas, th drivr can b charactrizd using,? ; and in addition to th input transition tim, tc. for drivr dlay computation. Sinc a vry larg look-up tabl or complx -factor quations and vry xtnsiv simulations ar ndd to account for all possibl combinations of,? ; and in a L -modl, th ffctiv capacitanc modl [14] was proposd to allow drivrs to b still pr-charactrizd in trms of a singl load capacitanc, vn whn usd to driv distributd RC intrconncts. Th ffctiv capacitanc modl first computs a L -modl to approximat th driving point admittanc,,u, and thn comput itrativly an ffctiv capacitanc, dnotd as in Fig. 4(d), using th following xprssion:,d, W? p)ª^cšh O«Th O.? Q O. NPO «h O. Q pj]/ ± P² P³ µ ¹ p8n^cšh ] µ ¹ ³ Q»º () whr OR«¼Ẅ O O b and O. Ẅ O«½hIO,, and O and O, ar obtaind from th -factor quations in trms of th ffctiv capacitanc and th input transition O. Th itration starts with using th total intrconnct and sink capacitanc as th loading capacitanc to gt an b stimat of OR«and O. through th -factor quations. A nw valu of th ffctiv capacitanc is computd using Eqn. () and it is usd as th loading capacitanc for th nxt,u, itration of computation. Th procss stops whn th valu of dos not chang in two succssiv itrations. At th nd of th itrativ procss, w also obtain O and O, at th gat output. Th ffctiv capacitanc, which is smallr than *JÀ in Fig. 4(b), capturs th fact that not all th capacitanc of th bg¾ b routing tr and th sinks is sn by th drivr du to th ffct of intrconnct rsistanc shilding, spcially in dp submicron dsign with fast logic gats of lowr drivr rsistanc. A so-calld rsistanc modl (R-modl) was also proposd in [14] to bttr approximat th slow dcaying tail portion of th rspons wavform whn th drivr is bhaving lik a rsistanc to ground. Th modl can b usd to furthr account for th intraction btwn th RC intrconnct and th drivr whn computing th intrconnct dlay [16]. Ths mthods illustrat th complication of th intraction btwn th drivr modl and th intrconnct modl in th dp submicron dsign. III. INTERCONNECT LAYOUT OPTIMIZATION Givn th growing importanc of intrconncts, intrconnct optimization nds to b considrd in vry stp of th layout dsign procss. W propos a prformanc-drivn layout dsign flow as shown in Fig. 5, in which planning and optimization for global intrconncts ar carrid out during th floorplan stag and furthr intrconnct optimization is prformd during global routing. In this sction, w discuss various optimization tchniqus that can b applid in this flow for intrconnct dlay minimization, including wirlngth minimization, dvic sizing, intrconnct topology optimization, buffr insrtion, optimal wirsizing, and simultanous dvic and intrconnct optimization. Floorplanning Global Int. Planning & Opitimization Timing Drivn Placmnt Dlay Budgting Prformanc Drivn Global Routing Intrconnct Optimization Dtaild Routing with Variabl Width and Spacing Topology Optimization Buffr Insrtion Dvic sizing Wirsizing Intrconnct Optimizations Library Fig. 5 Layout dsign flow for dp submicron ICs. A. Wirlngth Minimization A vry ffctiv way to rduc th intrconnct dlay is to minimiz th wirlngth of timing-critical nts, so that thir total capacitancs ar rducd. Placmnt has th biggst impact on th wirlngth. Timing-drivn placmnt mthods can b classifid into th nt-basd approachs and path-basd approachs. For nt-basd approachs, a dlay budgting algorithm is first applid on th ntlist to comput th timing slack for ach nt (or two-trminal subnt) (.g. [17]). Ths slacks ar thn translatd into wirlngth uppr bound constraints (.g. [18]) or th nt wights in th optimization objctiv function usd by th placmnt ngin. Path-basd approachs usually us mathmatical programming tchniqus and considr th path-basd timing constraints dirctly in th problm formulation (.g. [1]). In both cass, th stimatd wirlngths of th timing critical nts (oftn masurd in trms of th half primtr of th nt bounding box) ar minimizd during th placmnt, possibly at th xpns of th wirlngths of non-timing critical nts. Wirlngth minimization can also b carrid out during global routing by constructing an optimal (or nar-optimal) Stinr tr (OST)

5 },, Å for ach timing-critical nt. Th commonly usd mthods includ itrativ addition of Stinr points, optimal mrging of dgs of a minimum spanning tr (MST), or itrativ rfinmnt of an MST. Ths mthods ar survyd in [3]. Howvr, whn th intrconnct rsistanc nds to b considrd as wll, wirlngth minimization alon during global routing may not lad to th minimum intrconnct dlay. Intrconnct topology optimization nds to b considrd. B. Intrconnct Topology Optimization It was shown in [20] that whn th rsistanc ratio, dfind to b th drivr ffctiv rsistanc ovr th unit wir rsistanc, is small nough, both th total wirlngth (i.. th total intrconnct capacitanc) and intrconnct topology will impact th intrconnct dlay. Th first stp in intrconnct topology optimization is to minimiz or control th path-lngths from th drivr to th timing-critical sinks to rduc th intrconnct RC dlays. A numbr of algorithms hav bn dvlopd to minimiz both th path-lngths and th total wirlngth in a routing tr. For xampl, th boundd-radius bounddcost (BRBC) algorithm [21] bounds th radius (i.. th maximum path-lngth btwn th drivr and a sink) in th routing tr whil minimizing its total wir-lngth. It first constructs an MST, thn liminats th long paths by adding short-cuts into th MST and computing a shortst path tr of th rsulting graph. Othr algorithms in this class includ th AHHK tr construction and th prformanc orintd spanning tr construction, which ar discussd in [22] and [3]. In particular, it was shown in [20] that a minimal lngth shortst path tr in th Manhattan plan (calld th A-tr) can b constructd vry fficintly using a bottom-up mrging huristic with sizabl dlay rduction yt only a small wir-lngth ovrhad compard to th OST. Th A-tr construction mthod has bn xtndd to signal nts with multipl drivrs (as in signal busss) [23]. Furthr optimization of intrconnct topology involvs using mor accurat dlay modls during routing tr topology construction. For xampl, th Elmor dlay modl was usd in [24] and th 2-pol dlay modl was usd in [25] to valuat which nod or dg to b addd to th routing tr during itrativ tr construction. Othr mthods, such as th alphabtical tr and P-tr construction ar also summarizd in [3]. C. Dvic Sizing Whn w hav a good stimat of th intrconnct capacitiv load of a nt, th siz of its driving gat can b optimizd for dlay minimization. For a havy capacitiv load, a chain of cascadd drivrs is usually usd. Th drivr sizing problm is to dtrmin both th numbr of drivr stags and th siz for ach drivr. Using th simpl switch-rsistor RC modl and ignoring th capacitanc of th drivr output and th wir conncting to conscutiv drivrs, on can show that if th loading capacitanc is š and th stag numbr is Á, th ratio of two conscutiv drivrs (calld th stag ratio) should b a constant NuÂÄà  { Q?»Å^Æ in ordr to achiv th minimum dlay. Whn N is not fixd, th optimal stag ratio Ç WÈ] and th stag numbr is ÁÉWËÊ~Ì4Nu à ÂÄÍ Q. Whn th mor accurat drivr dlay modl is usd with considration of th drivr input transition tim and output capacitanc, th rsult in [26] shows that th optimal stag ratio Ç sat- whr Ñ is th ratio btwn th intrinsic output isfis ÇÎWo] y±ïð capacitanc and th input gat capacitanc of th invrtr. For th tchnology usd in [26], Ñ is about 1.35 and th optimal stag ratio is in th rang of 3 5 instad of ]. In gnral, transistor sizing can b usd to dtrmin th optimal width for ach transistor to optimiz th ovrall circuit prformanc. This tchniqu is oftn usd in cll gnration and full-custom layout. It is usually assumd that th transistor can b assignd a continuous width. Th arly work TILOS [27] usd th simpl switch-rsistor modl for transistors, formulatd th transistor sizing problm as a posynomial program, and applid a grdy snsitivity basd mthod. Th snsitivity of a transistor is dfind to b th dlay rduction du to a unit incrmnt of its siz. Th algorithm starts with a minimumsizd solution, and timing analysis is applid. Th transistor with th largst snsitivity is incrasd by a usr dfind factor and thn timing analysis is applid again. This procdur trminats whn th timing spcification is satisfid or all snsitivitis ar zro or ngativ. Rcnt advancs in transistor sizing includ th us of mor accurat transistor dlay modl with considration of th input wavform slop, and th us of linar programming, convx programming, or othr nonlinar programming tchniqus for computing a global optimal solution. Similar tchniqus hav also bn usd for discrt gat sizing (also calld cll sizing) in ASIC dsigns, which assums that ach gat has a discrt st of pr-dsignd implmntations (clls) from a givn cll library. Th gat sizing algorithm chooss an appropriat cll for ach gat for prformanc optimization. Ths tchniqus ar summarizd in [3]. D. Buffr Insrtion Buffr insrtion (also calld rpatr insrtion) is anothr common and ffctiv tchniqu to us activ dvic aras to trad for rduction of intrconnct dlays. Sinc th Elmor dlay of a long wir grows quadratically in trms of th wirlngth, buffr insrtion can rduc intrconnct dlay significantly. A polynomial-tim dynamic programming algorithm was prsntd in [28] to find th optimal buffr placmnt and sizing for RC trs undr th Elmor dlay modl. Th formulation assums that th possibl buffr positions (calld lgal positions), possibl buffr sizs, and th rquird arrival tims at sinks ar givn, and maximizs th rquird arrival tim at th sourc. Th algorithm includs both bottom-up synthsis of possibl buffr assignmnt solutions at ach nod and top-down slction of th optimal solution. j In th bottomup synthsis procdur, for ach lgal position for buffr insrtion, = a st of possibl j buffr assignmnts, calld options, in th subtr rootd at = is computd. = Ò For a nod which is th parnt of two subtrs and =, th = Ò = list of options for s is gnratd from th option lists of and basd on a mrging rul and a pruning rul, so that th numbr of options = = for = Ò s is no mor than th sum of th numbrs of options for and plus th numbr of possibl buffr assignmnts in th dg coming to. As a rsult, if th total numbr of lgal positions is Á and thr is on typ of buffr, th total numbr of options at th root of th ntir routing tr is no largr than Á C vn though th numbr of possibl buffr assignmnts is Æ. Aftr th bottom-up synthsis procdur, th optimal option which maximizs th rquird arrival tim at th sourc is slctd. Thn, a top-down back-tracing procdur is carrid out to slct th buffr assignmnt solution that ld to th optimal option at th sourc. E. Wirsizing Optimization It was first shown in [20, 2] that whn wir rsistanc bcoms significant, as in th dp submicron dsign, propr wir-sizing can ffctivly rduc th intrconnct dlay. Assuming ach wir has a st of discrt wir widths, thir work prsntd an optimal wirsizing algorithm for a singl-sourc RC intrconnct tr to minimiz th sum of wightd dlays from th sourc to timing-critical sinks undr th Elmor dlay modl. Thy showd that an optimal wirsizing solution satisfis th monoton proprty, th sparability, and th dominanc proprty. Basd on th dominanc proprty, th lowr (or uppr) bounds of th optimal wir widths can b computd fficintly by itrativ local rfinmnt, starting from a minimum-width solution (or maximum-width solution for computing uppr bounds). Each local rfinmnt opration rfins th width of an dg in th routing

6 @ tr assuming all othr dg widths ar fixd. Th lowr and uppr bounds usually mt, which lads to an optimal wirsizing solution. Othrwis, a dynamic programming basd mthod is usd to comput th optimal solution within th lowr and uppr bounds. This mthod is vry fficint, capabl of handling larg intrconnct structurs, and lads to substantial dlay rduction. It has bn xtndd to optimiz th routing trs with multipl drivrs, routing trs without a priori sgmntation of long wirs, and to mt th targt dlays using Lagrangian rlaxation. Th radr may rfr to [3] for mor dtails. An altrnativ approach to wirsizing optimization computs an optimal wirsizing solution using bottom-up mrging and top-down slction [30] in a vry similar way as th buffr insrtion algorithm prsntd in th prcding subsction. At ach nod Ó, a st of irrdundant wirsizing solutions of th subtr rootd at Ó is gnratd by mrging and pruning th irrdundant wirsizing solutions of th subtrs rootd at th childrn nods of Ó. Evntually, a st of irrdundant wirsizing solutions is formd at th drivr for th ntir routing tr, and an optimal wirsizing solution is chosn by a top-down slction procss. Th approach has th advantags that th optimization is targtd at mting th rquird signal arrival tims at sinks dirctly, and it can b asily xtndd to b combind with routing tr construction and buffr insrtion as shown in th nxt sction. Furthr studis on wirsizing optimization includ using mor accurat dlay modls, such as highr-ordr RC dlay modls [31] and lossy transmission lin modls [32], and undrstanding th optimal wir shap undr th assumption that non-uniform continuous wirsizing is allowd to ach wir sgmnt [33]. Ths rsults ar discussd in mor dtails in [3]. All ths algorithms, howvr, optimiz th wir widths of a singl nt and ignor th coupling capacitanc btwn adjacnt nts, which can b significant in dp submicron dsigns. Rcntly, an fficint algorithm namd GISS (global intrconnct sizing and spacing) was dvlopd to optimiz th widths and spacings for multipl nts simultanously with considration coupling capacitanc for dlay minimization [34]. It rportd substantial furthr dlay rduction compard to th singl nt wir sizing algorithms. F. Simultanous Dvic and Intrconnct Optimization Th most ffctiv approach to prformanc optimization is to considr th intraction btwn dvics and intrconncts, and optimiz both of thm at th sam tim. Two approachs ar discussd in this subsction. F.1. Simultanous Dvic and Wir Sizing Th simultanous drivr and wir sizing (SDWS) problm was studid in [35] and latr gnralizd to simultanous buffr and wir sizing (SBWS) in a buffrd routing tr [36]. In both cass, th switch-rsistor modl is usd for th drivr and th Elmor dlay modl is usd for th intrconncts modld as RC trs. Th objctiv function is to minimiz th sum of wightd dlays from th first stag of th cascadd drivrs through th buffrd routing tr to timing-critical sinks. It was shown that th dominanc proprty still holds for SDWS and SBWS problms and th local rfinmnt opration, as usd for wirsizing, can b usd itrativly to comput tight lowr and uppr bounds of th optimal widths of th drivr, buffrs, and wirs fficintly, which oftn lads to an optimal solution. Dynamic programming or boundd numration can b usd to comput th optimal solution within th lowr and uppr bounds whn thy do not mt. This approach has bn shown to b vry ffctiv for optimizing vry larg buffrd trs, yilding substantial rduction on both dlay and powr dissipation compard to manual dsigns. In fact, it was rcntly shown in [37] that th dominanc proprty holds for a larg class of objctiv functions calld gnral CHposynomials. Basd on this gnral rsult, th work in [37] is abl Dlay (ns) Tchnology (um) DS 1mm BIS 1mm BISWS 1mm DS 2cm BIS 2cm BISWS 2cm Fig. 6. Dlays of 1 mm and 2 cm M4 lins undr drivr sizing only (DS), buffr insrtion and sizing (BIS) and buffr insrtion and sizing and wirsizing (BISWS). to prform simultanous transistor and wir sizing fficintly givn a gnral ntlist (not limitd to buffrd trs). A significant advantag of th CH-posynomial formulation is that it can handl mor accurat transistor modls, including both simpl analytical modls or mor accurat tabl-lookup basd modls obtaind from dtaild simulation to considr th ffct of th wavform slop, which lads to bttr optimization rsults. Othr studis on simultanous dvic and wir sizing includ using highr ordr RC dlay modls for th intrconnct by ithr matching to th targt momnts or using a q- pol transfr function for snsitivity analysis. Th radr may rfr to [3] for mor dtails. F.2. Simultanous Topology Construction with Buffr and Wir Sizing Th wirsizd buffrd A-tr (WBA-tr) algorithm was proposd [38] for simultanous routing tr topology construction, buffr insrtion and wirsizing. It naturally combins th A-tr construction algorithm [20] and th simultanous buffr insrtion and wirsizing algorithm [30], as both us bottom-up construction tchniqus. Th WBA algorithm includs a bottom-up synthsis procdur and a topdown slction procdur. During th bottom-up synthsis procdur, it slcts two subtrs for mrging with considration of both minimization of wirlngth and maximization of th stimatd arrival tim at th sourc. As a rsult, it is abl to achiv both critical path isolation and a balancd load dcomposition, as oftn usd for fanout optimization in logic synthsis. Th WBA algorithm has bn xtndd rcntly to xplor multipl intrconnct topologis at ach subtr and us high-ordr RLC dlay modls basd on fficint incrmntal momnt computation in partially constructd routing trs [3]. Othr mthods hav also bn proposd for simultanous topology construction and wir sizing, including a grdy dynamic wir sizing during itrativ routing tr construction and us of link insrtion with dynamic wir sizing to crat non-tr topologis. Ths algorithms ar summarizd in [3]. IV. OPTIMIZATION RESULTS AND COMPARATIVE STUDIES A. Impact of Intrconnct Optimization on Futur Tchnology Gnrations W applid thr intrconnct optimization tchniqus for intrconnct dlay minimization of a 2 cm global intrconnct and a 1 mm local intrconnct for ach tchnology gnration in NTRS. Th thr optimization algorithms includ (i) optimal drivr sizing (DS), (ii) optimal buffr insrtion and sizing (BIS), and (iii) optimal buffr insrtion, sizing and wirsizing (BISWS). Th dlays of th optimizd intrconnct structurs in ach tchnology gnration ar shown in Fig. 6, and dtaild dscription of th optimization rsults by BISWS

7 Ö Ö Ö 2 cm lin 1 mm lin TABLE IV Tch ÔÕ (ns) % ÕŒ# % " # " ( # m) ÔÕ (ns) % ÕŒ# % " # ( m) " # Rsults of Buffr Insrtion and Sizing and Wirsizing. ÔÕ is % Õ# th numbr of buffrs insrtd. % " # is th avrag buffr siz normalizd to " # minimum fatur siz. is th avrag wir siz. is th prcntag of wir sgmnts with sizing largr than minimum width. ar shown in Tabl IV. W hav svral obsrvations from this st of rsults. 1. Th impact of buffr insrtion and buffr/wir sizing for local intrconncts is minimal aftr propr drivr sizing, vn for th tchnologis blow zc) m. 2. Buffr insrtion/sizing and wir sizing hav vry significant impact for global intrconncts, spcially as th tchnology progrsss to vry dp submicron dsigns. In th K m tchnology, BIS rducs th intrconnct dlay by almost a factor of 10. Whn wirsizing is allowd, BISWS furthr rducs th intrconnct dlay by 40% to 50%. 3. Intrconnct dsign will b highly complx in dp submicron tchnologis. For xampl, th optimization rsult of th 2 cm global intrconnct by BISWS contains 11 buffrs with.8% wirs bing sizd abov th minimum width. Clarly, a global intrconnct is no longr a simpl mtal lin. It bcoms a complx circuitry with optimizd dvics and wirs in dp submicron dsigns! Considring th fact that thr will b ovr 800 million transistors and 7-8 routing layrs, with an stimatd total wir lngth ovr 10 kilomtrs pr chip in th Œ m tchnology, w nd highly fficint and scalabl layout systms to support th various intrconnct optimization tchniqus discussd in this papr. 4. Although th bst intrconnct optimization tchniqu (BISWS) is abl to rduc th global intrconnct dlay by up to 20 compard with th un-optimizd dsigns in th sam tchnology gnration, if w compar th dlays of bst optimizd global intrconncts in diffrnt tchnology gnrations, it only dcrass slightly by about 40% from m to m. This clarly indicats that such optimization alon will not achiv ovr 3 prformanc incras from th m to m tchnologis as xpctd in Tabl I. Thrfor, innovations in systm architcturs, intrconnct architcturs, and intrconnct tchnologis ar ndd to achiv th prdictd prformanc targts in NTRS. B. Comparisons of Various Intrconnct Optimization Algorithms In this subsction, w provid a comparativ study of a numbr of intrconnct optimization algorithms prsntd in Sction III in trms of thir fficincy and optimality, so that on can mak propr choics for his or hr optimization nds in practic. W us th intrconnct optimization packag dvlopd in our group at UCLA in th past fiv yars, namd TRIO (Tr, Rpatr, and Intrconnct Optimization) for this st of xprimnts. Th TRIO packag includs many intrconnct optimization algorithms prsntd in Sction III and also offrs th capability to combin thm in diffrnt ways to provid a wid spctrum of intrconnct optimization solutions. In particular, w shall compar th following four optimization stratgis: Ø T+B+W: A-tr construction (Sction III.F.2), followd by optimal buffr insrtion and sizing (Sction III.F.1) with B=10 buffr sizs, thn followd by optimal wirsizing using bundld local rfinmnt [40] basd on th dominanc proprty (Sction III.E) with W=18 wir widths. Ø TB+SBWS: simultanous topology and buffr optimization (Sction III.F.2) with B=3 followd by simultanous buffr and wirsizing (Sction III.F.1) with B=40 and W=18. Ø Tbw+SBWS: simultanous topology, buffr insrtion and sizing, and wirsiz optimization (Sction III.F.2) with vry limitd choics of buffr sizs and wir widths (B=3 and W=3), followd by simultanous buffr and wir sizing (SBWS in Sction III.F.1) with B=40 and W=18. Ø TBW: simultanous topology construction, buffr insrtion and sizing, and wirsiz optimization (Sction III.F.2) with B=10 and W=8. Ths algorithms ar applid to thr sts of randomly gnratd multi-trminal nts of 5, 10 and 20 pins, rspctivly, with pins uniformly distributd within a 10 mm by 10 mm ara. Each st contains thr instancs. Th optimization rsults ar shown in Tabl V basd on th 0.18 m tchnology. W hav svral obsrvations: 1. Simultanous dvic and intrconnct optimization by TBW usually producs th bttr rsults compard to othr sparat optimizations, with up to 20% additional dlay rduction compard to T+B+W. 2. Th bottom-up dynamic programming tchniqu usd in TBW can b vry timing consuming (vn run in polynomial tim) with larg numbr of choics of buffr sizs and wir widths (up to 6 minuts on th avrag for 20-pin nts). 3. For buffr or/and wir sizing, local rfinmnt basd optimization (SBWS) using th dominanc proprty is much mor fficint than th bottom-up dynamic programming tchniqu usd in TBW. SBWS can handl a larg numbr of buffr sizs and wir widths in a fraction of a scond. Thrfor, propr combination of TBW and SBWS provids a good trad-off of fficincy and optimality. Our rsults show that Tbw+SBWS has lss than 1% diffrnc compard to TBW in trms of solution quality, but runs mor than 10 tims fastr. Thrfor, Tbw+SBWS is our rcommndd solution for most intrconnct optimization applications. Th UCLA TRIO packag also includs a numbr of othr intrconnct optimization routins, such simultanous transistor and wir sizing (STIS), global intrconnct sizing and spacing (GISS), tc. whos rsults ar not abl to b includd hr du to th spac limitation. Th TRIO packag can accommodat a numbr of layout constraints, such as th uppr and lowr bounds of ach wir sgmnts, allowd buffr locations, tc. It also intrfacs with a 2.5D capacitanc xtractor and can produc th optimization rsults dirctly into th HSPICE ntlist format for dtaild timing simulation. All th dlay rsults rportd in this papr ar obtaind by HSPICE simulations. V. CONCLUSIONS In this tutorial, w hav shown th trnds and challngs of intrconnct dsign as th tchnology fatur siz dcrass to blow zc m basd on th data in NTRS. W prsntd a st of commonly

8 5 pins 10 pins 20 pins Algorithms T+B+W TB+SBWS Tbw+SBWS TBW ÙÚ (ns) (s) (ns) ÙÚ (s) (ns) ÙÚ (s) TABLE V ÙÚ nt (ach row is on nt) and is th avrag running tim on a Sun Ultra2 workstation with 256 Mbyts of mmory. Comparison of Algorithms. is th avrag dlay tim for ach usd intrconnct and drivr modls and prsntd a st of intrconnct dsign and optimization tchniqus which hav provn to b vry ffctiv for improving intrconnct prformanc and rliability. Our xprimntal rsults show that ths optimization tchniqus hav a vry significant impact on th prformanc of th global intrconncts, with diffrnt dgr of fficincy and optimality. Th rsarch on intrconnct modling and optimization hav bn focusd mainly on intrconnct dlay minimization in th past svral yars. Givn th growing importanc of coupling nois as discussd in Sction 1 and othr concrns on signal rliability, w xpct to s much mor rsarch on modling and optimization on signal rliability of intrconncts in th nar futur. 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