74HC4514; 74HCT to-16 line decoder/demultiplexer with input latches
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- Evelyn Carroll
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1 Rev. 3 0 February 0 Product data sheet General description Features and benefits 3 pplications The is a 4-to-6 line decoder/demultiplexer having four binary weighted address inputs (0 to 3), with latches, a latch enable input (LE), an enable input (E) and 6 outputs (0 to 5). When LE is HIGH, the selected output is determined by the data on n. When LE goes LOW, the last data present at n are stored in the latches and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the latch, is HIGH. t E HIGH, all outputs are LOW. The enable input E does not affect the state of the latch. When the device is used as a demultiplexer, E is the data input and 0 to 3 are the address inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V CC. The 74HCT454 features reduced input threshold levels to allow interfacing to TTL logic levels. Input levels: For 74HC454: CMOS level For 74HCT454: TTL level 6-line demultiplexing capability Decodes 4 binary-coded inputs into 6 mutually-exclusive outputs Complies with JEDEC standard no. 7 ESD protection: HBM JESD-4F exceeds 000 V MM JESD-5- exceeds 00 V Multiple package options Specified from -40 C to +5 C and -40 C to +5 C Digital multiplexing ddress decoding Hexadecimal/BCD decoding
2 4 Ordering information Table. Ordering information Type number 74HC454D 74HCT454D Package Temperature range Name Description Version 40 C to +5 C SO4 plastic small outline package; 4 leads; body width 7.5 mm 74HC454DB 40 C to +5 C SSOP4 plastic shrink small outline package; 4 leads; body width 5.3 mm 74HC454PW 74HCT454PW 5 Functional diagram 40 C to +5 C TSSOP4 plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT37- SOT340- SOT355-0 DX 0 X/Y LE C C D, G D, 9D, 9D, D, EN 9 3 E aaa-06 aaa-06 Figure. Logic symbol Figure. IEC logic symbol LE LTCHES 3 E DECODER aaa-063 Figure 3. Functional diagram / 9
3 0 0 SD latch RD 3 4 SD latch RD SD latch 3 RD LE SD latch 4 RD 3 4 Figure 4. Logic diagram E 5 aaa / 9
4 6 Pinning information 6. Pinning LE GND HC454 74HCT454 aaa-065 V CC E Figure 5. Pin configuration for SO4 (SOT37-) LE GND HC454 74HCT454 aaa V CC E Figure 6. Pin configuration for SSOP4 (SOT340-) and TSSOP4 (SOT355-) Table. Pin description 6. Pin description Symbol Pin Description LE latch enable input (active HIGH) E 3 enable input (active LOW) 0,,, 3, 4, 5, 6, 7,, 9, 0,,, 3, 4, 5, 9, 0,, 7, 6, 5, 4,, 7, 0, 9, 4, 3, 6, 5 0,,, 3, 3,, address inputs GND ground (0 V) V CC 4 supply voltage multiplexer outputs (active HIGH) 4 / 9
5 7 Functional description Table 3. Function table [] Inputs [] Outputs E H X X X X L L L L L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L H L L L L H L L L L L L L L L L L L L L L L H L L L L H L L L L L L L L L L L L L L H H L L L L L H L L L L L L L L L L L L L L L H L L L L L H L L L L L L L L L L L L H L H L L L L L L H L L L L L L L L L L L L H H L L L L L L L H L L L L L L L L L L H H H L L L L L L L L H L L L L L L L L L L L L H L L L L L L L L H L L L L L L L L H L L H L L L L L L L L L H L L L L L L L L H L H L L L L L L L L L L H L L L L L L H H L H L L L L L L L L L L L H L L L L L L L H H L L L L L L L L L L L L H L L L L H L H H L L L L L L L L L L L L L H L L L L H H H L L L L L L L L L L L L L L H L L H H H H L L L L L L L L L L L L L L L H [] H = HIGH voltage level; L = LOW voltage level; X = don t care. [] LE = HIGH Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < -0.5 V or V I > V CC V - ±0 m I OK output clamping current V O < -0.5 V or V O > V CC V - ±0 m I O output current -0.5 V < V O < V CC V - ±5 m I CC supply current - 50 m I GND ground current m T stg storage temperature C P tot total power dissipation SO4, SSOP4 and TSSOP4 [] mw [] For SO4 packages: P tot derates linearly with mw/k above 70 C. For SSOP4 and TSSOP4 packages: P tot derates linearly with 5.5 mw/k above 60 C. 5 / 9
6 9 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions 74HC454 74HCT454 Unit Min Typ Max Min Typ Max V CC supply voltage V V I input voltage 0 - V CC 0 - V CC V V O output voltage 0 - V CC 0 - V CC V Δt/ΔV input transition rise and fall rate V CC =.0 V ns/v V CC = 4.5 V ns/v V CC = 6.0 V ns/v T amb ambient temperature C 0 Static characteristics Table 6. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC454 V IH V IL V OH V OL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage T amb ( C) to to +5 Min Typ Max Min Max Min Max V CC =.0 V V V CC = 4.5 V V V CC = 6.0 V V V CC =.0 V V V CC = 4.5 V V V CC = 6.0 V V V I = V IH or V IL I O = -0 μ; V CC =.0 V V I O = -0 μ; V CC = 4.5 V V I O = -0 μ; V CC = 6.0 V V I O = -4.0 m; V CC = 4.5 V V I O = -5. m; V CC = 6.0 V V V I = V IH or V IL I O = 0 μ; V CC =.0 V V I O = 0 μ; V CC = 4.5 V V I O = 0 μ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5. m; V CC = 6.0 V V Unit 6 / 9
7 Symbol Parameter Conditions I I input leakage current I CC supply current V I = V CC or GND; I O = 0 ; V CC = 6.0 V T amb ( C) to to +5 Min Typ Max Min Max Min Max V I = V CC or GND; V CC = 6.0 V - - ±0. - ±.0 - ±.0 μ Unit μ C I input capacitance pf 74HCT454 V IH V IL V OH V OL I I HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current V CC = 4.5 V to 5.5 V V V CC = 4.5 V to 5.5 V V V I = V IH or V IL ; V CC = 4.5 V I O = -0 μ V I O = -4 m V V I = V IH or V IL ; V CC = 4.5 V I CC supply current V I = V CC or GND; V CC = 5.5 V; I O = 0 ΔI CC additional supply current I O = 0 μ V I O = 4.0 m V V I = V CC or GND; V CC = 5.5 V - - ±0. - ±.0 - ±.0 μ per input pin; V CC = 4.5 V to 5.5 V; V I = V CC -. V; other inputs at V CC or GND; I O = μ n μ LE μ E μ C I input capacitance pf 7 / 9
8 Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit, see Figure 9. Symbol Parameter Conditions 74HC454 t pd t t t W t su t h C PD propagation delay transition time pulse witdh set-up time hold time power dissipation capacitance n to n; see Figure 7 [] T amb ( C) to to +5 Min Typ Max Min Max Min Max V CC =.0 V ns V CC = 4.5 V ns V CC = 5 V; C L = 5 pf ns V CC = 6.0 V ns LE to n; see Figure 7 V CC =.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns E to n; see Figure 7 V CC =.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns n; see Figure 7 [] V CC =.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns LE HIGH; see Figure V CC =.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns n to LE; see Figure V CC =.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns n to LE; see Figure V CC =.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns per package; V I = GND to V CC [3] Unit pf / 9
9 Symbol Parameter Conditions 74HCT454 t pd propagation delay n to n; see Figure 7 [] T amb ( C) to to +5 Min Typ Max Min Max Min Max V CC = 4.5 V ns V CC = 5 V; C L = 5 pf ns LE to n; V CC = 4.5 V; see Figure 7 E to n; V CC = 4.5 V; see Figure 7 t t transition time n; V CC = 4.5 V; see Figure 7 t W pulse witdh LE HIGH; V CC = 4.5 V; see Figure t su set-up time n to LE; V CC = 4.5 V; see Figure t h hold time n to LE; V CC = 4.5 V; see Figure C PD power dissipation capacitance per package; V I = GND to V CC -.5 V [] [3] ns ns ns ns ns ns Unit pf [] t pd is the same as t PLH and t PHL [] t t is the same as t TLH and t THL [3] C PD is used to determine the dynamic power dissipation (P D in μw). P D = C PD x V CC x fi x N + Σ(C L x V CC x fo ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of load switching outputs; Σ(C L x V CC x fo ) = sum of the outputs. 9 / 9
10 . Waveforms and test circuit V I n, LE, E input GND t PHL t PLH V OH 90 % 90 % n output V OL 0 % 0 % t THL t TLH aaa-067 Measurement points are given in Table. V OL and V OH are typical output voltage levels that occur with the output load. Figure 7. The inputs (n, LE, E) to output (n) propagation delays and the output transition times V I n input GND t h t h t su t su LE input V I transparant latched transparant latched GND aaa-06 Measurement points are given in Table. The shaded areas indicate when the input is permitted to change for predictable output performance. Figure. Data set-up and hold times for n input to LE input and LE input pulse width t W Table. Measurement points Type Input Output V I 74HC454 GND to V CC 0.5V CC 0.5V CC 74HCT454 GND to 3 V.3 V.3 V 0 / 9
11 V I negative pulse GND 90 % 0 % t f t W t r t r t f V I positive pulse GND 0 % 90 % t W V CC G VI DUT VO RT CL 00aah76 Test data is given in Table 9. Definitions for test circuit: R T = Termination resistance; should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. Figure 9. Test circuit for measuring switching times Table 9. Test data Type Input Load V I t r, t f C L 74HC454 GND to V CC 6 ns 5 pf, 50 pf 74HCT454 GND to 3 V 6 ns 5 pf, 50 pf / 9
12 pplication information V CC all diodes are general purpose Germanium LE 9 0 E 3 4 R = kω R = kω 45 0 R = 0 kω aaa-0074 Figure 0. Code-to-code conversion; hexadecimal to BCD / 9
13 3 Package outline SO4: plastic small outline package; 4 leads; body width 7.5 mm SOT37- D E X c y H E v M Z 4 3 ( ) 3 pin index L L p θ e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note max b p c D () E () e H () E L L p v w y Z Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included θ o o OUTLINE VERSION SOT37- REFERENCES IEC JEDEC JEIT 075E05 MS-03 EUROPEN PROJECTION ISSUE DTE Figure. Package outline SOT37- (SO4) 3 / 9
14 SSOP4: plastic shrink small outline package; 4 leads; body width 5.3 mm SOT340- D E X c y H E v M Z 4 3 pin index ( ) 3 θ L L p detail X e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT 3 b p c D () E () e H () E L L p v w y Z max. mm θ o o 0 Note. Plastic or metal protrusions of 0. mm maximum per side are not included. OUTLINE VERSION SOT340- REFERENCES IEC JEDEC JEIT MO-50 EUROPEN PROJECTION ISSUE DTE Figure. Package outline SOT340- (SSOP4) 4 / 9
15 TSSOP4: plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT355- D E X c y H E v M Z 4 3 pin index ( ) 3 θ w M e b p L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT 3 b p c D () E () e H () E L L p v w y Z max. mm θ o o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included.. Plastic interlead protrusions of 0.5 mm maximum per side are not included. OUTLINE VERSION SOT355- REFERENCES IEC JEDEC JEIT MO-53 EUROPEN PROJECTION ISSUE DTE Figure 3. Package outline SOT355- (TSSOP4) 5 / 9
16 4 bbreviations Table 0. bbreviations cronym CMOS DUT ESD HBM MM TTL Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 5 Revision history Table. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT454 v Product data sheet - 74HC_HCT454 v. Modifications: The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 74HC_HCT454 v Product specification - 74HC_HCT454 v. 6 / 9
17 6 Legal information 6. Data sheet status Document status [][] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet ualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL 6. Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6034) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 7 / 9
18 Non-automotive qualified products Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 6.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. / 9
19 Contents General description... Features and benefits... 3 pplications... 4 Ordering information... 5 Functional diagram... 6 Pinning information Pinning Pin description Functional description...5 Limiting values Recommended operating conditions Static characteristics...6 Dynamic characteristics.... Waveforms and test circuit... 0 pplication information... 3 Package outline bbreviations Revision history Legal information...7 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. Nexperia B.V. 0. ll rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Date of release: 0 February 0 Document identifier: 74HC_HCT454
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Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current
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Rev. 6 3 ugust 0 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC standard
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Rev. 5 26 November 2018 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package 74HC3G04DP 74HCT3G04DP 74HC3G04DC 74HCT3G04DC
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Rev. 03 9 November 2007 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32.
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Rev. 6 26 July 2018 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package 74HC2G02DP 74HCT2G02DP 74HC2G02DC 74HCT2G02DC
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Rev. 1 8 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G32-Q100 and 74HCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input
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Rev. 3 28 March 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes two binary weighted address inputs (n0, n1) to four mutually exclusive outputs
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Rev. 4 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0
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Rev. 2 12 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH
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Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
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Rev. 12 5 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH
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Rev. 03 September 200 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible
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Rev. 6 6 September 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number 74HC1G125GW 74HCT1G125GW 74HC1G125GV 74HCT1G125GV
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Rev. 6 2 September 20 Product data sheet. General description 2. Features and benefits 3. Ordering information Table. Ordering information Type number Package The provides four 2-input OR gates. Inputs
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Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This
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Rev. 1 22 November 2017 Product data sheet 1 General description 2 Features and benefits 3 pplications The is a single, level translating buffer/line driver with 3-state output. The low threshold inputs
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Rev. 4 4 September 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
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Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output
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Rev. 3 5 October 207 Product data sheet General description 2 Features and benefits 3 Ordering information Table. Ordering information Type number Package The is a high-performance, low-power, low-voltage,
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Quad 2-input NND gate Rev. 5 25 November 200 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard
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Rev. 12 2 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).
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