ENG2410 Digital Design Sequencing and Control

Transcription

1 ENG24 igital esign equencing and ntrl atapath cnsists f: Parts f PU Registers, Multiplers, dders, ubtractrs and lgic t perfrm peratins n data (mb Lgic) ntrl unit Generates signals t cntrl data-path ccepts status signals t perfrm sequencing Fall 27. reibi chl f Engineering University f Guelph ntrl ata Path 4 Week # Tpics The ntrl Unit lgrithmic tate Machines M Elements Hardwired ntrl I. One Flip-Flp Per tate II. equence Register and ecder VHL Representatin The ntrl Unit The binary infrmatin stred in a digital cmputer can be classified as either data r cntrl infrmatin.. ata is manipulated in a data-path T perfrm arithmetic, lgic, shifting, and ther dataprcessing tasks. These peratins are implemented with LUs, registers, multipleers, and busses. 2. The cntrl unit Prvides signals that activate the varius micrperatins in the data-path t perfrm the specified data prcessing tasks. The cntrl unit als determines the sequencein which the varius actins are perfrmed (i.e. when they are t be perfrmed) 2 5 Resurces hapter #8, Man ectins 8. The ntrl Unit 8.2 lgrithmic tate Machines 8.3 M Eamples 8.4 Hardwired ntrl ntrl Unit Types Tw distinct classes: Prgrammable Nn-prgrammable. prgrammable cntrl unit has: n eternal ROM r RM array fr string instructins and cntrl infrmatin prgram cunter (P) r ther sequencing register with cntents that pints t the net instructin t be eecuted ecisin lgic fr determining the sequence f peratins and lgic t interpret the instructins nn-prgrammable cntrl unit (hardwired ntrl) des nt fetch instructins frm a memry but just determines the peratins t be perfrmed and the sequence f thse peratins based nly n inputs and status bits. 3 We will nly cver nn-prgrammable cntrl unit 6 chl f Engineering

2 tate M rectangle with: The symblic name fr the state marked utside the upper left tp ntaining register transfer peratins and utputs activated within r while leaving the state n ptinal state cde, if assigned, utside the upper right tp (ymblic Name) ILE (Optinal state cde) (Register transfers r utputs) R 0 RUN 7 lgrithmic tate Machines (M) The functin f a state machine (r sequential circuit) can be represented by a state table r a state diagram. What is wrng with state diagrams? Gets messy as states grw ecisins t mve t different states is nt present. lutin? flwchart is a way f shwing actins and cntrl flw in an algrithm. n lgrithmic tate Machine (M) is simply a flwchart-like way t specify state diagrams fr sequential lgic and, ptinally, actins perfrmed in a datapath. While flwcharts typically d nt specify time, an M eplicitly specifies a sequence f actins and their timing relatinships. calar ecisin diamnd with: One input path (entry pint). One input cnditin, placed in the center f the b, that is tested. TRUE eit path taken if the cnditin is true (lgic ). FLE eit path taken if the cnditin is false (lgic 0). (False nditin) (True nditin) 0 (Input) TRT 8. tate (a rectangle) 2. calar ecisin (a diamnd) (Input) TRT 3. Vectr ecisin (a heagn), Q0 M Primitives The tate is a rectangle, marked with the symblic state name, cntaining register transfers and utput signals activated when the cntrl unit is in the state. The calar ecisin is a diamnd that describes the effects f a specific input cnditin n the cntrl. It has ne input path and tw eit paths, ne fr TRUE () and ne fr FLE (0). The Vectr ecisin is a heagn that describes the effects f a specific n-bit (n > 2) vectr f input cnditins n the cntrl. It has ne input path and up t 2 n eit paths, each crrespnding t a binary vectr value. Frm ecisin (es) The nditinal Output is an val with entry frm a 4. nditinal Output decisin blck and utputs activated fr the decisin cnditins (val). being satisfied. (Register transfers Vectr ecisin heagn with: One Input Path (entry pint). vectr f input cnditins, placed in the center f the b, that is tested. Up t 2 n utput paths. The path taken has a binary vectr value that matches the vectr input cnditin (inary Vectr Values) (Vectr f Input nditins), Q0 (inary Vectr Values) R chl f Engineering 2

3 nditinal Output n val with: One input path frm a decisin b r decisin bes. One utput path Register transfers r utputs that ccur nly if the cnditinal path t the b is taken. Transfers and utputs in a state b are Mre type - dependent nly n state Transfers and utputs in a cnditinal utput b are Mealy type - dependent n bth state and inputs Frm ecisin (es) (Register transfers r utputs) R 0 RUN tate iagram M 3 6 nnecting es Tgether Frm tate iagram t M y cnnecting bes tgether, we begin t see the pwer f epressin. What are the: I. tates? II. Inputs? III. Outputs? IV. nditinal Outputs? V. Transfers? VI. nditinal Transfers? ILE R 0 VIL TRT = 0 = = = 0 P 0 INIT 4 7 M lcks Frm tate iagram t M = 0 = = = 0 One state b alng with all decisin and cnditinal utput bes cnnected t it is called an M lck. The M lck includes all items n the path frm the current state t the same r ther states. ILE VIL TRT R R + R 0 M LOK MUL0 Q0 MUL 5 8 chl f Engineering 3

4 Eample () Hardwired ntrl Find the M chart crrespnding t the fllwing descriptin. There are tw states, 2. If in state and input X is `0 then the net state is 3. If in state and input X is ` then the net state is 4. If in state and input Y is ` then the net state is 5. If in state and input Y is `0 then the net state is 6. Output is equal t ` while the circuit is in state lutin:. Ttal tates 2 2. Tw Inputs X, Y 3. One Output esigning the ntrl Unit: I. One Flip-flp per tate flip-flp is assigned t each f the states and at any time, nly ne f the flip flps cntains a, with all the rest cntaining 0. II. equence Register and ecder Uses a sequence register fr the cntrl states and a decder t prvide an utput signal crrespnding t each f the states M fr Eample () 0 X One Flip Flp per tate = Y I. One Flip-Flp per tate Hardwired ntrl s the name implies the methd uses ne flip-flp per stateand a simple set f transfrmatin rules t implement the circuit. The design starts with the M chart, Then all yu d is replace:. tate with a flip-flp, 2. calar ecisin with a demultipleer with 2 utputs, 3. Vectr ecisin with a (partial) demultipleer 4. ny Junctin with an OR gate, and 5. ny nditinal Output with an N gate (fr a Mealy Machine!!) 2 24 chl f Engineering 4

5 tate Transfrmatin Rules Junctin Transfrmatin Rules Each state b transfrms t a Flip-Flp pint is cnnected t FF input. pint is cnnected t the FF `Q utput. Where tw r mre entry pints jin, cnnect the entry variables t an OR gate The is the utput f the OR gate TTE TTE Q calar ecisin Transfrmatin Rules Each ecisin b transfrms t a emultipleer pints are "Enable" inputs. The nditin is the "elect" input. ecded Outputs are the pints. 0 X X nditinal Output Rules If each branch takes yu t a different state r directin then use a emu with tw utputs. pint is Enable input. The nditin is the "elect" input. emu Outputs are the pints. The ntrl OUTPUT is the same signal as the eit value. If bth branches take yu t the same state then use a single N gate instead f a emu. The FF utput will be directly cnnected t the net FF. X X OUTPUT OUTPUT 29 Vectr ecisin Transfrmatin Rules Implement using Flip Flp Per tate Each vectr decisin b transfrms t a emultipleer pint is Enable inputs. The nditins are the elect inputs. emultipleer Outputs are the pints. Nte: One FF is assigned t each f the states, and at any time, nly ne f the FFs cntains a, with all the rest cntaining 0. (inary Vectr Values) (Vectr f Input nditins) X, X 0 (inary Vectr Values) EMUX EN 0 0 X X When a is in the FF assigned t a particular state, the sequential circuit is in that same state. The single prpagates frm ne FF t anther under the cntrl f decisin lgic chl f Engineering 5

6 One Flip Flp Per tate Implement equence Register/ecder OR OR emu emu Hw many Flip Flps? ecder ize? 3 34 Implement equence Register/ecder equence Register ecder equence Register & ecder M 0 M X equence Register and ecder tate Table: This methd uses a decder and a set f flip flps (r a register) t implement the circuit. I. The design starts with the M chart, Present tate Inputs Net tate ecder Outputs II. ccrding t the number f states 2 n, we will use n flip flps (lg 2 # state) III. nstruct tate Table (directly frm M) IV. Use an n-t-2 n decder has 2 n utputs Name M M M M X chl f Engineering 6

7 equence Register and ecder M0 =. M = +. Present tate Inputs Net tate ecder Outputs Name M M 0 M M VHL Implementatin X Implement equence Register/ecder VHL de M0 =. M = +. 0 ecder P Prcess that will depend n clck event t reset system t Idle tate and implement state_register based n LK imilar t equencer P2 Prcess that will cntrl yur data path (If yu have a data path!) Prcess that will act as a sequencer that will dictate the state yu are in given the input P One FF per tate vs. eq/reg/ec Implement Using VHL t first glance, it may seem that the ne FF per state methd wuld increase the cst f the system, since mre flip-flps are used. ut the methd ffers sme cst advantages that may nt be apparent: One advantage is the simplicitywith which the lgic can be designed merely by inspectin f the M chart r state diagram. N state r ecitatin tables are needed if flip-flps are emplyed. This ffers a savings in design effrt, an increase in lgic simplicity. What are the Inputs? Remember that this is a state machine and we have t start smewhere at pwer up! ILE X G LO Y chl f Engineering 7

8 VHL de VHL de: Net-tate Prcess -- VHL de entity declaratin library ieee; use ieee.std_lgic_64.all; use ieee.std_lgic_unsigned.all; entity sequential_machine is prt (LK, REET, G, : in std_lgic; X,Y, : ut std_lgic); end sequential_machine; -- VHL de fr net_state_func net_state_func: prcess (G,,state) begin case state is when ILE => if G = then net_state <= LO; else net_state <= ILE; end if; when LO => net_state <= ; when => if = then net_state <= ILE; else net_state <= ; end if; end case end prcess; ILE X G LO Y VHL de: rchitecture VHL de: datapath Prcess -- VHL de rchitecture architecture behavir f sequential_machine is type state_type is (ILE, LO, ); signal state, net_state : state_type; begin tate_register: prcess (LK)... Net_state_func: prcess (G,,state)... atapath_func: prcess (LK)... end behavir; -- VHL de fr datapath_func Output_func: prcess (state) begin case state is when ILE => X <= ; when LO => Y <= ; when => < = end case end prcess; ILE X G LO Y VHL de: tate-register Prcess -- VHL de tate Register Prcess tate_register: prcess (LK, REET) begin if (REET = ) then state <= ILE; elsif (LK'event and (LK = '')) then state <= net_state; end if; end prcess; ummary ntrl units are an essential part f any PU. ntrl units can either be prgrammable r nn-prgrammable. Nn-prgrammable U: One FF per state equence Register and ecder. Obtaining the M is the key t designing any cntrl unit. Use the prcess statement t implement any sequential circuit, state diagrams and algrithmic state machines chl f Engineering 8

9 chl f Engineering 9