TURN-ON SIMULATION OF FIELD-CONTROLLED THYRISTOR

Transcription

1 SIMULATION OF SEMICONDUCTOR DEVICES AND PROCESSES Vl. 4 Edited by W. Fichtner, D. Aetnmer - Zurich (Switzerland) September 12-14, Hartung-Grre TURN-ON SIMULATION OF FIELD-CONTROLLED THYRISTOR Adrian Zuckerberger,Hrst Griining,Kenneth Jhanssn ASEA BROWN BOVERI,Crprate Research,CH-5405 Baden, Switzerland ABSTRACT The turn-n prcess f a field-cntrlled thyristr (FCTh) and the turn-ff f its clamping dide in a real circuit (snubberless clamped inductive lad including stray inductrs) was analyzed thrugh simultaneus 2D-device simulatin (ABBPISCES) f bth devices. Full understanding f FCTh turn-n transient behavir, the dide's turn-ff and the drive requirements has been achieved. Expnential current grwth under cnstant clamping vltage, a turn-n time cnstant less than 100 ns and high vercurrent capability f the FCTh have been bserved. The simulated results are in gd accrdance with experiments. Fr the first time a cmplete descriptin f the interactin between pwer devices (FCTh and dide) and external circuit thus is presented. The desire t better understand and utilize pwer electrnic devices and circuits has required imprved simulatin tls which are capable t deal widi the system dwn t the level f the silicn structure. The ABBPISCES sftware package [1] based n the device simulatr PISCES [2,3] has such capabilities; it is able t carry ut simulatins f electrical circuits cmprising silicn devices 2D (tw dimensinal) mdelled. Thrugh these simulatins the researcher/engineer can analyze the device behavir during transient and steady-state peratin. Its interactins with the different cmpnents f the circuit can be fully understd, and the circuit can be designed and ptimized till its perfrmances better fit t the required specificatins. Extended labratry activities thus will shrink t a minimum necessary fr a validatin f the prpsed device structures and circuitry. The present cntributin deals with the turn-n transient behavir f a fieldcntrlled thyristr (FCTh) [4,5,6] perating in a real circuit cnfiguratin shwn in Fig.l The cmpnents f the circuit are: the FCTh (SD-Switching Device), the clamping dide (Dclamp)> the pure inductive lad represented by means f a cnstant current surce (Ind. Lad), a clamping vltage surce and a gate unit cmprising a resistr (Rgate) an d a vltage surce (Vgate) ramped frm -15V (blcking cnditin) t 5V in 200ns. Als shwn in the figure are the parasitic cmpnents Lpara and Rpara- Such a cnfiguratin, equipped with different switching devices (GTO, IGBT, BJT, Pwer Fet) can be encuntered in many pwer electrnic applicatins, e.g. pwer supplies, industrial electric drives, tractin systems and thers, cvering a pwer range frm few watts t megawatts.

2 360 Lpara. Rpara Vclamp Rgate A v Dclamp SD e Ind.Lad Vgate Fig. 1 Simulated and tested circuit The whle circuit was simulated by means f ABBPISCES with bth switching devices mdelled 2D in silicn. 1.Simulatin Different turn-n simulatins f a 3.5kV blcking FCTh were carried ut at Vclamp=1000V. Figure 2 shws the ande current, ande vltage, gate current and gate vltage with an initial dide current density f 15 A/cm2. 5 I.IK-II -11 «.S1 > a.sa 1.1* 1.5" a (unci Z.ia I.sa «.5«-»l S 5_ a.iae-ai a " f.hc-tl 'I 1 f j l.uc-il a a.aacaa -a.iac-ai -a.sa i.sa si in 1.1» I.sa luaacl 2.1a z.sa 2.a.ilf-n (- 2-.( f><3 3.» < 2.» 1.a!.., C-«J a.iac- a.aaf-aar -a.sa a.aa a.sa l.ia 1.3a 2.ia a.a ta :::r IO- a.sa a.ja a.sa 1 U«a. a i.sa 2.1a 2.5a Fig.2 Current and vltage transients during FCTh turn-n prcess.

3 Based n Figure 2 ne may bserve the fllwing phases during the FCTh turn-n prcess : *Phase 1-At t=0.0m-s a cnstant current flws thrugh the dide, and the FCTh blcks the clamping vltage Vclamp=1000V. The vltage surce Vgate is ramped up t 5V in 200 ns. A capacitive current flws int the gate-cathde junctin f the sftdriven FCTh and the gate vltage increases almst linearly up t the pinch-ff vltage f -2V.The time cnstant f the gate circuit is jxs (with Rgate=15 kq. and a gate-cathde junctin capacitance f 100 pf). In ne time cnstant the gate vltage will reach the pinch-ff vltage. During this perid the ptential barrier in the fingers decreases (see Fig.3a), and electrns are allwed t leave the cathde (see Fig. 3b). ABBP1SCES Pt»n. t=1320 ns t=1180 ns t=691 ns t=286 ns ABBP1SCES K.. 2iL (_ C 8 t u c O 7 C 53 B "8 u t=1320 ns t=l 180 ns S.BB IS s tanca (um) IS D 1 s tnc!um) Fig.3 Ptential and electrn cncentratin in the middle f FCTh's cell. *Phase 2-At t=1.5(is, the FCTh behaves like a uniplar device, nly its JFET part is in peratin. Hles are injected by the ande, and due t the gate's lw ptential,they are cllected first by it (the gate). Cnsequently, its vltage increases mre rapidly and after the saturatin f gate-cathde dide the biplar peratin f the FCTh begins. *Phase 3-At t=1.6(is with saturated gate vltage the FCTh is behaving like a P-i-N dide fed by a vltage surce f 1000V. The current f the FCTh increases expnentially accrding t the law: I(t)=I(t=1.6 is) exp [(t-1.6ns) / x] (1)

4 362 In Figure 4 the ande current f the FCTh is presented. The calculated % was =80ns I I time (usee) Fig.4 Lgarithmic plt f ande current during turn-n(simulatin). *Phase 4-At t= 1.74ns the whle surce current flws int the FCTh (10A/cm 2 ). The dide current is zer, but still a lt f carriers are present in the pwer dide. Cnsequendy the current reverses: the dide enters the reverse recvery state. *Phase 5- Due t its high reverse current the excess carriers in the dide are swept ut at t=1.9jis and its vltage increases rapidly. Sme ringing is bserved between the parasitic inductance and the dide's variable capacitance ( due t the space charge regin). Depending n the value f Lpara. current and vltage scillatins will ccur and in many cases vervltages are expected. Only careful lay-ut design f such a circuit can avid the vervltages and a pssible device destructin. Simulated results are presented in Fig.5 fr tw different final current densities in the FCTh : J lf =10A/cm 2 and J 2f =135A/cm E*03 Current Dens. FCTh (A/cm 2 ) a.i 2E -e«r Ande vltage FCTh (V) a.sae-as J.SBE* E» E*33 3.2BE*03 a.tbe*83 H 3.33E*30; l.sa 1.73 l.aa i.aa a.sa 2.ia z time (usee) S time (usee) Fig.5 Simulated results at Jif=10A/cm 2 and J2f=135A/cm 2

5 As seen in Fig.5 the turn-n prcess is almst identical fr the tw cases with a time cnstant f T=80ns. High vercurrent due t the reverse recvery f the clamping dide and high dv/dt ver the FCTh because f the snappy behavir f the dide are als bserved. With a maximum current density f 660 A/cm 2 sme scillatins are present in the FCTh's vltage. 2.Experimental 10A and 200A, 2.5kV FCTh were fabricated and tested in ne and multi-pulse peratin. Fr bth devices the measured turn-n time cnstant was in the range ns [5]. In Figure 6 the turn-n current f a 10A device is shwn (with current n lgarithmic scale) and % was 105 ns. CE +-> C QJ _ i_ 3 U OJ "D O C I ime Cns ] Fig.6 Lgarithmic plt f ande current during tum-n(experiment). In Figure 7, the vltage and current f the FCTh perated in a circuit cnfiguratin as per Figure 1, are presented.the steady state current density was 60 A/cm 2 and the clamping vltage was 1000 V. The stray inductance was very lw (n vltage scillatins present) but sme parasitic capacitance caused by the windings f the "inductive lad" was bserved.

6 ns/dlv 30A/cm 2 /dh/ Fig.7 Experimental results - ande vltage and current at turn-n. 3.Cnclusins Fr the first time such a study, cmprising bth 2D simulatin f a cntrlled switching device at turn-n and a pwer dide has been carried ut. It seems wrth nting that the silicn devices are perated in a real circuit cnfiguratin and the simulatins were dne by means f ABBPISCES sftware package. The main cnclusins frm this wrk are: *At turn-n the FCTh current grws expnentially with a time cnstant f t=80ns. This time cnstant is independent f the gate-unit vltage/current wavefrms (this is nt the case with GTO's). *Due t the gate vltage saturatin a stable and unifrm turn-n will ccur even at current density gradients >2kA/(cm 2 *jis). *Sme disagreements between simulated and experimental results were bserved: ** Jmax/Jf(sini)=4.88 and J max /Jf(ex)=2.35. **V an d e wavefrm at high current density (J2f=135A/cm 2 ) differs frm the measured ne. **The experimental set-up cmprises a higher stray inductance and sme additinal parasitic capacitance than the simulated ne.

7 *Mre care thus wuld have been necessary in rder t adjust the dide's carrier lifetime (and lifetime prfiles), in particular.and, f curse, a number f different cases have t be studied in the future, and perhaps then even sme fine-tuning f Si-parameters may becme mandatry. 4.References [l]abbpisces-prgram reference manual,abb-internal Publ. [2]M. R. Pint et. al. " Pisces-2 Pissn and cntinuity equatin slver " Tech. Rep. Stanfrd Univ [3]M. R. Pint et. al. "Pisces-2 supplementary reprt" Tech.Rep.Stanfrd Univ [4]H. Griming et. al. " Prperties f a high-pwer field cntrlled thyristr " Prc. IEDM [5]H. Griining et. al." Snubberless superfast high pwer mdule.."ieee PESC [6]K. Jhanssn et. al" System simulatin and realizatin f a resnant inverter with a FCTh " Trans, n Pwer Electrnics,Vl.6, N.2, April 1991.