Predictive Direct Torque Control Application-Specific Integrated Circuit of an Induction Motor Drive with a Fuzzy Controller

Transcription

1 Journl Low Power Electronic Appliction Article Predictive Direct Torque Control Appliction-Specific Integrted Circuit n Induction Mor Drive Fuzzy Controller Guo-Ming Sung *, Wei-Yu Wng, Wen-Sheng Lin Chih-Ping Yu Deprtment Electricl Engineering, Ntionl Tipei Univerity Technology, Tipei 0608, Tiwn; w26ng@gmil.com (W.-Y.W.); wenheng.0@gmil.com (W.-S.L.); cpyu@ntut.edu.tw (C.-P.Y.) * Correpondence: gmung@ntut.edu.tw; Tel.: (ext. 22); Fx: Acdemic Edir: Alexer Fih Received: 8 Jnury 207; Accepted: 7 June 207; Publihed: 0 June 207 Abtrct: Thi pper propoe modified predictive direct control (PDTC) ppliction-pecific integrted circuit (ASIC) mor drive controller for eliminting mpling clculting dely time in hyterei controller. e dely time degrde control qulity incree both flux ripple in mor drive. PDTC ASIC clculte tr mgnetic flux by detecting three-phe, three-phe voltge, ror peed, eliminte ripple in flux by uing controller predictive cheme. Verilog hrdwre decription lnguge w ued implement hrdwre rchitecture, ASIC w fbricted by Tiwn Semiconducr Mnufcturing Compny through 0.8-µm P6M CMOS proce tht involved cell-bed deign method. meurement reveled tht PDTC ASIC three-phe induction mor yielded tet coverge 96.03%, fult coverge 95.06%, chip re.8.8 mm 2, power conumption 296 mw, t n operting frequency 50 MHz upply voltge.8 V. Keyword: predictive direct control; ASIC; induction mor; hrdwre decription lnguge; control. Introduction direct control (DTC) lgorithm i bed on between reference etimted vlue flux. Inverter tte cn be directly controlled by reducing flux in b limit []. conventionl proportionl integrl derivtive (PID) control i till widely ued peed regulr in DTC ytem [2]. However, induction mor (IM) h multivrible, trong coupling, nonliner, time-vrying chrcteritic. A PID mor peed regulr i ued for djuting nonliner control vrible for enhncing peed,, tbility DTC ytem [3]. Furrmore, model predictive direct control (MPDTC) lgorithm i ued mintin mor, tr flux, inverter neutrl point potentil in given hyterei bound by reducing verge witching frequency inverter, unlike proce in conventionl DTC method. Studie hve reported tht MPDTC lgorithm cn chieve n verge inverter witching frequency reduction 6.5% [4,5]. In IM drive ytem, quick- cheme i bed on limit cycle control both flux [6]. A low witching frequency i ued in n inverter chieve rpid dynmic. Thi i chieved by rpidly equling flux reference vlue. witching technique minly contribute lrge flux, which generte dditionl flux ripple in mor control ytem [7]. To chieve high IM control performnce, decree vrition in flux by pplying ory, lower verge inverter witching ; doi:0.3390/jlpe

2 2 6 frequency repect conventionl DTC lgorithm, combintion control predictive direct control (PDTC) lgorithm h been. model predictive control (MPC) lgorithm h been ued in vriou brnche umotive reerch. Borhn Vhidi n online optimiztion-bed predictive controller control power-plit hybrid electric vehicle [8]. Suzuki et l. implemented n individul ir-fuel etimtion control by uing n MPC controller [9]. Bgehwr et l. computed pcing-control lw for trnitionl mneuver vehicle by uing MPC lgorithm [0]. Seren et l. preented ppliction MPC in control conventionl powertrin inted hybrid powertrin []. He et l. illutrted n MPC-bed dem control pproch for -bed control prllel hybrid powertrin, which compried ditribur, nonliner MPC controller, liner MPC controller permnent-mgnet ynchronou mor, lod oberver [2]. According forementioned review, liner MPC lgorithm i deigned feedbck. In or word, MPC lgorithm i implemented cloed-loop control, which reult in low controller. In PDTC lgorithm, modified predictive compention circuit open-loop control i ued peed up controller. Furrmore, ubtrcting previou flux φ [k ] preent flux φ [k] gretly reduce ripple flux or. Okumu control trtegy in which b i controlled by controller through n pplied voltge vecr lope mintin contnt witching frequency in ll operting condition. Through technique, witching frequency inverter cn be kept nerly contnt [3]. Siv et l. preented direct -controlled IM drive ytem vrible tructure controller (FVSC) tte feedbck controller (FSFC). FVSC exhibited low noticeble overhoot. ripple in tr flux were lower in FSFC compred PID FVSC. controller improved performnce robutne drive ytem [4]. In ddition, PI control (PIC) IM exhibited more ripple, high flux dirtion, poor trnient performnce due udden diturbnce, poor enitivity control gin. To improve performnce IM, PIC w replced by type-2 logic control (TP2FLC), which reulted in n excellent dynmic performnce IM le hrmonic dirtion in,, flux [5]. Dybkowki Szbt preented n dptive control tructure while working online tuned neuro- peed compenr. In control ytem, controller vecr election tble were ued etblih n pproprite voltge vecr for chieving high operting peed tbility [6,7]. In PDTC lgorithm, vertile flexible control lgorithm were developed for relizing electric mor drive fvorble performnce chrcteritic [5]. conventionl direct control (CDTC) n IM w improved uing rtificil intelligence control mor peed field-progrmmble gte rry (FPGA). Fuzzy logic w ued improve effectivene conventionl PI controller when it chnged time operting condition. In ddition, digitl implementtion CDTC peed controller w bed on FPGA, which w ued overcome limittion twre olution (e.g., digitl ignl proceor microcontroller) [8]. In thi pper, we preent n ppliction-pecific integrted circuit (ASIC) cpble control PDTC for IM drive. In thi tudy, PDTC w fbricted uing 0.8-µm P6M CMOS technology. Simulted reult were recorded t n operting frequency 50 MHz upply voltge.8 V. reminder thi pper i orgnized follow. Section 2 detil pology PDTC ASIC, implemented 0 block. Section 3 imulted reult. Section 4 our concluion. 2. Propoed Topology Fuzzy PDTC ASIC block digrm modified PDTC for n IM drive, which comprie Hll enor, n nlog--digitl converter, n bc dq trnformtion unit, flux clculr, voltge

3 clculr, voltge clculr, clculr, peed clculr, n ngle elecr, predictive clculr, controller, clculr, peed voltge clculr, vecr n elecr, ngle elecr, hort-circuit predictive preventer. clculr, All block were controller, deigned uing voltge Verilog vecr elecr, hrdwre decription hort-circuit lnguge preventer. (HDL) All block verified wereuing deigned n FPGA uing bord. Verilog After hrdwre digitl decription chip w lnguge implemented (HDL) uing verified yni uingol, n FPGA u plce, bord. routed After ol, digitl verifiction chip w implemented ol, n ASIC uing w fbricted yniuing ol, u 0.8-μm plce, P6M routedcmos ol, proce verifiction for three-phe ol, n ASIC IM w control fbricted ytem. uing 0.8-µm P6M CMOS proce for three-phe IM control ytem. A hown in in,, PDTC PDTC ASIC ASIC (red (red rectngle) rectngle) comprie comprie 0 block. 0 block. In In deign deign e e block, block, we we focued focued on on voltge voltge clcultion, flux flux clcultion, clcultion, ngle election, modified predictive clcultion, control, voltge vecr election, hort-circuit prevention. * ω r * λ + ω r - Speed Feedbck ω * r( err) Fuzzy T e Controller S Te τ - + S b Fuzzy Torque Error Voltge Vecr Selection φ Tble - + λ Flux Error Predictive Clcultion θ Secr Selection S c Voltge Clcultion Short- b Circuit b Prevention c c V b λ q V c V λ d AC220V Inverter Vd I c I Ib bc-dq Trnformtion Vq Hll Senor ADC Id Flux Cl. Iq Induction Mor P b P Fuzzy PDTC ASIC Torque Cl.. Block digrm modified PDTC ASIC for three-phe IM control ytem.. Block digrm modified PDTC ASIC for three-phe IM control ytem. 2.. Voltge Clcultion 2.. Voltge Clcultion To clculte voltge, n bc dq trnformtion w performed not only implify To clculte voltge, n bc dq trnformtion w performed not only implify clcultion proce, but lo ccelerte trnformtion. In generl, mor voltge were clcultion proce, but lo ccelerte trnformtion. In generl, mor voltge were determined uing three-phe witching tte S, S b, S c DC voltge V dc inverter. determined uing three-phe witching tte S, Sb, Sc DC voltge Vdc inverter. clculted three-phe output voltge, repect centrl point, V n, V bn, V cn, cn be clculted three-phe output voltge, repect centrl point, Vn, Vbn, Vcn, cn be expreed follow: expreed follow: V n = V dc V3 (2S S b S c ), () dc Vn = ( 2S Sb Sc ), () V bn = V 3dc 3 ( S + 2S b S c ), (2) Vdc Vbn = ( S + 2Sb Sc ), (2) V cn = V 3dc 3 ( S S b + 2S c ) (3) For mor tr, clculted V n, V bn, V cn cn be expreed three-phe tr voltge V, V b, V c which cn be V trnformed in two-phe tr voltge, V dc Vcn = ( S Sb + 2Sc ) d V (3) q, by uing following eqution: 3 For mor tr, clculted Vn, Vbn, Vcn cn be expreed three-phe tr V voltge V, V b, V d c which cn = be V = V dc trnformed 3 (2S S b S c ), (4) in two-phe tr voltge, V d V q, by uing following eqution: Vq Vdc Vd = = V = ( dc (S 2S b S c ) (5) 3 b S c ), (4)

4 4 6 Tble relted voltge prmeter repect vriou witching tte. In ddition, Hll enor w ued detect three-phe tr i, i b, i c mor drive, e were trnformed in two-phe tr, i d i q, follow: [ i d (t) i q(t) ] = [ 0 / 3 2/ 3 ][ i (t) i b (t) ] (6) Tble. Relted voltge prmeter repect vriou witching tte. Vecr Voltge S S b S c V n V bn V cn V d V q V V 0 0 2V dc /3 V dc /3 V dc /3 2V dc /3 0 V 2 0 V dc /3 V dc /3 2V dc /3 V dc /3 V dc / 3 V V dc /3 2V dc /3 V dc /3 V dc /3 V dc / 3 V 4 0 2V dc /3 V dc /3 V dc /3 2V dc /3 0 V V dc /3 V dc /3 2V dc /3 V dc /3 V dc / 3 V 6 0 V dc /3 2V dc /3 V dc /3 V dc /3 V dc / 3 V If two tr, i i b, re, third prmeter i c cn be clculted on bi following eqution: i + i b + i c = 0 (7) 2.2. Flux Torque Clcultion After two-phe tr tr voltge re obtined, two-phe mgnetic fluxe φ d φ q cn be clculted uing winding reitnce R, which i direct- reitnce in ingle-phe winding tr. In or word, mgnetic fluxe in d q xi cn be expreed follow [6]: [ V d V q ] = R [ i d i q ] + p [ φ d φ q ], p = d dt (8) If R i mll, Eqution (8) cn be implified uing mpling time T follow [7]: [ φ d φ q ] z [ φ d φ q ] + T [ V d V q ] (9) mgnetic T e in d q xi cn n be expreed follow [8]: T e = 3 2 p ( ) φ 2 d i d φ qiq, (0) where p i pole number mor. Note tht digitl multiplier i implemented Booth multipliction lgorithm [9], compoite mgnetic flux i completed qure root opertion, which i implemented in hdow tree lgorithm [20] Angle Selection ngle cn be elected uing clculted two-phe tr fluxe by determining flux φ dq. In generl, voltge pce vecr cn be divided in ix ecr, ech ecr including n ngle 60. To implify nlyi, firt qudrnt coordinte plne i depicted in 2. Both φ d φ q re poitive in thi qudrnt. In ddition, 2 two ecr, S S 2.

5 2.3. Angle Selection ngle cn be elected uing clculted two-phe tr fluxe by determining flux φ dq. In generl, voltge pce vecr cn be divided in ix ecr, ech ecr including n ngle 60. To implify nlyi, firt qudrnt coordinte plne i depicted J. Low Power in Electron. Appl. 2. Both 207, φ7, d 5 φ q re poitive in thi qudrnt. In ddition, 2 5two 6 ecr, S S2. ngle firt ecr, S, extend 0 30, where tht econd ecr, S2, extend In trigonometry, ngle firt ecr, S, extend 0 reltionl 30 eqution i expreed follow:, where tht econd ecr, S 2, extend In trigonometry, reltionl eqution i expreed follow: φd = φdq co30 φd () φdq φq = φdq co60 co 30 φq = co 60 () Dividing φ q(t) by φ d(t) give following: φ dq Dividing φ q(t) by φ d(t) give 3 φ following: φ = 0 (2) q When two fluxe φ d(t) φ q(t) φ 3 re poitive q φ d = 0 3 φq φ i negtive, we elect d (2) firt ecr S, where output i econd ecr S2 becue When two fluxe φ d(t) φ q(t) re poitive two 3 φq fluxe φ φd d(t) φ q(t) re poitive 3 φ i negtive, we elect q φ i poitive. output i if vlue φ d(t), φ q(t), or d 3 φ q φ i d poitive firt ecr S, where output i econd ecr S 2 becue two fluxe φ d(t) φ q(t) re poitive i 0 orwie. 3 φq φd Tble 2 i ecr election tble for i poitive. output i if vlue φ d(t), φ q(t), or 3 φq φd output ecr cn be eily elected uing thi tble. i poitive i 0 orwie. Tble 2 i ecr election tble for output ecr cn be eily Tble elected 2. Secr uing election thi tble. 3 φ d φq Tble 2. Secr election φ tble φ Output Secr d 3 Œ d 0 Œ q Œ Œ d S = q Output [0 0 ] Secr 0 0 S = [ 0 ] 0 S = [0 0 ] S4 = [0 S = ] [ 0 ] S4 = [ S4 = ] [0 ] S2 = [0 S4 0 = 0] [ ] 0 S6 = [ S2 0 = 0] [0 0 0] 0 S6 = [ 0 0] 0 0 S3 = [0 S3 = 0] [0 0] S5 = [ S5 = 0] [ 0] q d φ dq φ q φ d 2. Firt qudrnt coordinte tr fluxe, φ d φ q. 2. Firt qudrnt coordinte tr fluxe, φ d φ q Modified Predictive Clcultion 2.4. Modified Predictive Clcultion 3 modified compention circuit preent mgnetic flux tr, φ [k], 3 modified compention mor, T e [k]. circuit A hown inpreent mgnetic 3, dely flux (z ) block tr, i φ[k], completed uing preent n edge-triggered Dmor, flipflop Te[k]. (DFF) A circuit, hown in ubtrction 3, block dely (denoted (z ) block by i ymbol in figure) i ued obtin devition between preent flux φ [k] previou flux φ [k ], bolute vlue block (Ab.) provide mgnitude devition, multiplexer determine output k + k φ [k] ccording control ignl Cφ [k]. 3b me function, but preent T e [k] previou Te[k ]. Unlike conventionl DTC, predictive compention circuit ued in tudy cn reduce ripple

6 completed uing n edge-triggered D flipflop (DFF) circuit, ubtrction block (denoted by ymbol in figure) i ued obtin devition between preent flux φ[k] previou flux φ[k ], bolute vlue block (Ab.) provide mgnitude devition, J. Low multiplexer Power Electron. determine Appl. 207, 7, 5 output k k + φ[k] ccording control ignl Cφ[k]. 6 3b 6 me function, but preent Te[k] previou Te[k ]. Unlike conventionl DTC, predictive compention circuit ued in tudy cn reduce ripple in flux in flux. Moreover,. Moreover, PDTC notpdtc only h not only dvntge h dvntge conventionl conventionl DTC, but lo DTC, horten but lo horten dely time dely thu time exhibit thu high exhibit performnce. high performnce. C ] φ [k [k] φ [k -] φ k Δ + k φ [ k] () T [ k ] e T[ k -] e C e [ k] T k Δ + k T [ k] e (b) 3. Modified predictive compention circuit () Mgnetic flux tr 3. Modified predictive compention circuit () Mgnetic flux tr φ. φ (b) Torque mor Te.. (b) Torque mor T e Fuzzy Controller 2.5. Fuzzy Controller 4 memberhip function two input vrible n output vrible. 4 memberhip function two input vrible n output vrible. According nlyi tep in DTC ytem, three field vrible cn According nlyi tep in DTC ytem, three field vrible cn be defined follow. field mor peed feedbck e i [ 00, 00], tht peed be defined follow. field mor peed feedbck e i [ 00, 00], tht peed vrition e i [ 0, 0], tht vlue u i [ 2, 2]. ubet re {NB, NS, vrition e i [ 0, 0], tht vlue u i [ 2, 2]. ubet re {NB, ZE, PS, PB} [3]. bbrevition NB, NS, ZE, PS, PB repreent negtive big, negtive NS, ZE, PS, PB} [3]. bbrevition NB, NS, ZE, PS, PB repreent negtive big, negtive mll, zero, poitive mll, poitive big, repectively [6]. mll, zero, poitive mll, poitive big, repectively [6]. Ech rule controller cn be decribed uing e, e, u. A hown in Tble 3, if e = Ech rule controller cn be decribed uing e, e, u. A hown in Tble 3, if e = NB e = NB, n u = PB. A tl 25 rule re preented for two input vrible. NB e = NB, n u = PB. A tl 25 rule re preented for two input vrible. control rule re preented in Tble 3. control rule re preented in Tble Fuzzy FuzzyVoltge VoltgeVecr VecrSelecr To Toenhnce enhnce performnce performnce DTC DTCytem, typicl typiclvoltge voltgevecr vecrelection electiontble tblew w modified. modified. In In modified modified tble, tble, input input vrible vrible were were in in tr tr flux, flux, in in,, tr tr ngle, ngle, output output vrible vrible w w witching witching tte elecr. tte elecr. 5 5 memberhip memberhip function function flux flux three ubet three {N, Z, P}. ubet letter {N, N, Z, P}. Z, P letter repreent N, Z, negtive P repreent flux, negtive zero flux flux,, zero poitive flux, flux, poitive repectively. flux, repectively. 6 memberhip 6 function T five ubet {NL, NS, ZE, PS, PL}. bbrevition NL, NS, ZE, PS, PL repreent negtive lrge, negtive mll, zero, poitive mll, poitive lrge, repectively. u t i memberhip function e t i.

7 memberhip function T five ubet {NL, NS, ZE, PS, PL}. 7 6 bbrevition memberhip NL, NS, function ZE, PS, PL repreent T negtive five lrge, ubet negtive {NL, mll NS, ZE,, PS, zero PL}., poitive bbrevition mll, NL, NS, ZE, poitive PS, lrge PL repreent, repectively. negtive lrge ut i, negtive memberhip mll function, zero, et i poitive 7mll., memberhip 7 poitive lrge function memberhip, repectively. tr function ngle ut i ix tr ngulr memberhip ngle intervl, function ix {θngulr, θ 2, θet 3, intervl, i θ 4, θ 5, θ 6 {θ, }.. θ2, ngulr θ3, θ4, θ5, intervl 7 θ6}. θngulr, θ 2, θmemberhip 3, intervl θ 4, θ 5, θ, function θθ2, 6 extend θ3, θ4, θ5, tr 29 θ6 extend ngle 30, 3 29 ix 90 ngulr, 9 30, 3 intervl, 50, 90, 5 9 {θ, 20 θ2, 50, θ3,, 2 θ4, 5 θ5, 270 θ6}. 20,, 2 ngulr , 330 intervl, repectively 27 θ, θ2, 330, θ3, [2]. θ4, repectively θ5, Tble 4θ6 i[2]. extend Tble 4 voltge i 29 vecr 30, voltge 3 election 90, vecr tble 9 election for 50, 5 tble for 20, PDTC 2 270, PDTC 27 controller. 330, repectively controller. [2]. Tble 4 i voltge vecr election tble for PDTC controller. NB NB NS ZE PS NS ZE PS PB PB e Δe e Δe u u Memberhip function two twoinput vrible n n output. 4. Memberhip function two input vrible n output. Tble3. 3. Fuzzy control rule. Tble 3. Fuzzy control rule. e e e e PB PS ZE e NS NB e PB PS ZE NS NB PB NB PB NB PS NS ZE NS NS ZE NB PB NB NB NS NS ZE PS PB NS NB NS NB NS ZE NS ZE PS NS NS NS ZE ZE ZE ZE PS NS NS NS NSZE PS ZE PS PS ZE PS NS NS ZE ZE ZE NS ZE NS PS ZE PS PS PS PS PS PS PS NB NB NS ZE ZE ZE PS PS PS PB PS PB PB PS PB NB ZE ZE PS PB PB u t un t Z P N Z P e t e t 5. Memberhip function flux three ubet {N, Z, P}. 5. Memberhip function flux three ubet {N, Z, P}.

8 8 6 J. J. Low Power Electron. Appl. 207, 7, 7, u tt NL NL NS NS ZE ZE PS PS PL PL e tt Memberhip function five ubet {NL, NS, ZE, PS, PS, PL}. 6. Memberhip function five ubet {NL, NS, ZE, PS, PL}. 7. Memberhip function tr ngle ix ngulr intervl {θ, θ2, θ3, θ4, θ5, θ6} Memberhip function tr ngle ix ngulr intervl {θ,, θ2, θθ2, 2, θ3, θθ3, 3, θ4, 4 θ5,, θ5, θ 5, θ6}. θ Short-Circuit Prevention 2.7. Short-Circuit Prevention To To prevent hort circuit in inverter, ded time i ued protect inverter burning To prevent hort circuit in in inverter, ded time i i ued protect inverter burning mor control ytem. hort-circuit prevention cheme, which mor control ytem. 88 hort-circuit prevention cheme, which comprie two tte, 0 0, in in control ignl. Firt, Up ignl i i low (0) (0) high comprie two tte, 0 0, in control ignl. Firt, Up ignl i low (0) high () () when control ignl turn f f ( 0); Down ignl i i high () () low (0) (0) when () when control ignl turn f ( 0); Down ignl i high () low (0) when ded time ( T) i i up. Second, Down ignl i i low (0) (0) high () () when control ignl turn ded time ( T) i up. Second, Down ignl i low (0) high () when control ignl turn on on (0 ); Up ignl i i high () () low (0) (0) when ded time ( T) i i up. dvntge on (0 ); Up ignl i high () low (0) when ded time ( T) i up. dvntge hort-circuit prevention method i i tht it it help eily djut ded-time intervl hort-circuit prevention method i tht it help eily djut ded-time intervl ( T) ccording pecifiction mor control ytem. ( T) ccording pecifiction mor control ytem. 8. Propoed hort-circuit prevention cheme Propoed hort-circuit prevention cheme Simultion Simultion Meurement Meurement Reult Reult PDTC PDTC w w implemented implemented uing uing Verilog Verilog HDL, HDL, ModelSim ModelSim twre twre w w ued ued imulte imulte verify verify opertion opertion deigned deigned hrdwre hrdwre circuit. circuit. 99

9 9 6 Tble 4. Fuzzy voltge vecr election tble. Ψ T θ θ 2 θ 3 θ 4 θ 5 θ 6 PL V 2 V 3 V 4 V 5 V 6 V 9 6 PS V 2 V 3 V 4 V 5 V 6 V imultion reult for Pix rm ZE feeding V V 2 inverter. V 3 VIn 4 thi Vfigure, 5 V 6 P Pb re feedbck ignl peed encoder; NS output V 6 ignl V U_out, V 2 Ub_out, V 3 V 4 Uc_out V 5 re output wveform upper rm for U-, V-, NL VW 6 phe, V repectively; V 2 V 3 V 4 output V 5 ignl D_out, Db_out, Dc_out repreent output PL wveform V 3 V 4 V 5 lower V 6 rm V for V 2 U-, V-, W phe, repectively. In or word, three PS complementry V 2 V 3 Vwitche, 4 V 5 U_out V 6 V D_out, Ub_out Db_out, Z ZE V 6 V V 2 V 3 V 4 V Uc_out Dc_out, were imulted verify tht output wveform 5 both upper NS V 6 V V 2 V 3 V 4 V lower rm worked intended. 0 compoite mgnetic 5 flux NL V 5 V 6 V V 2 V 3 V 4 PDTC, PL V 3 V compoite 4 V mgnetic 5 V 6 V flux V conventionl DTC. A 2 comprion between 0 PS V clerly 3 V revel 4 V tht 5 V 6 V V rchitecture operted 2 mller ripple. performnce N ZE V 4 V 5 PDTC V 6 w V uperior V 2 Vtht 3 conventionl DTC [22]. 2 locu NS V 5 tr V 6 flux in V V 2 V 3 V 4 PDTC, which w uperior tht in [23]. 3 NL imulted V 5 V 6 electromgnetic V V 2 V 3 V 4 PDTC repect chnge peed r/min in, which operted mll ripple, 3. Simultion hown in Meurement 4. In comprion Reult [24], PDTC performed moothly by reducing ripple generted in indirect mtrix converter. ripple controller occurred irrepective PDTC mpling w implemented frequency, uing where Verilog thoe HDL, hyterei ModelSim controller twre were w ueddependent imulte on mpling verify frequency. opertion Furrmore, deigned hrdwre voltge vecr circuit. election tble 9(Tble 4) imultion w ued reult not foronly ix rpidly rmdetermine feeding inverter. ix output Inwveform, thi figure, but P lo Pb re protect feedbck inverter ignl peed burning encoder; mor output control ignl ytem U_out, ded Ub_out, time. Uc_out re output wveform upper rm for U-, V-, W phe, repectively; output ignl D_out, Db_out, Tble 4. Fuzzy voltge vecr election tble. Dc_out repreent output wveform lower rm for U-, V-, W phe, repectively. In or word, three complementryψ witche, T θ θ2 θ3 θ4 θ5 θ6 U_out D_out, Ub_out Db_out, Uc_out Dc_out, were imulted verify tht PL V2 V3 V4 V5 V6 V output wveform both upper lower rm worked PS V2 V3 V4 V5 V6 V intended. 0 compoite mgnetic flux PDTC, P ZE V V2 V3 V4 V5 V6 compoite mgnetic flux conventionl DTC. A comprion between 0 NS V6 V V2 V3 V4 V5 clerly revel tht rchitecture NL operted mller ripple. performnce V6 V V2 V3 V4 V5 PDTC w uperior tht PL V3 conventionl V4 V5 V6 DTC V [22]. V2 2 locu tr flux in PDTC, PS which V2 V3 w V4 uperior V5 V6 V tht in [23]. 3 imulted electromgnetic Z ZE V6 V V2 V3 PDTC V4 V5 repect chnge peed r/min in, which operted NS V6 V mll V2 ripple, V3 V4 V5 hown in 4. In comprion [24], PDTC performed NL V5 V6 V V2 V3 V4 moothly by reducing ripple generted in indirect mtrix converter. ripple PL V3 V4 V5 V6 V V2 controller occurred irrepective mpling frequency, PS V3 V4 V5 V6 V V2 where thoe hyterei controller were dependent on mpling frequency. Furrmore, N ZE V4 V5 V6 V V2 V3 voltge vecr election tble (Tble 4) w ued not only rpidly determine ix output NS V5 V6 V V2 V3 V4 wveform, but lo protect inverter burning mor control ytem ded time. NL V5 V6 V V2 V3 V4 9. Simultion ix rm through ModelSim twre. 9. Simultion ix rm through ModelSim twre.

10 0 6 J. J. J. Low Low Power Power Electron. Electron. Appl. Appl. 207, 207, 7, 7, 7, Compoite mgnetic flux.. Compoite Compoite mgnetic mgnetic flux flux conventionl conventionl DTC. DTC. 2. Locu tr flux in in

11 J. J. Low Low Power Power Electron. Electron. Appl. Appl. 207, 207, 7, 7, Simulted electromgnetic repect chnge peed r/min 3. Simulted electromgnetic repect chnge peed r/min 3. Simulted chnge chnge peed peed 000 r/min in for electromgnetic 3. Simulted electromgnetic repect repect r/min in for in infor for PDTC. 4. Simulted ripple repect chnge peed r/min in 4. Simulted ripple repect chnge peed r/min in. 4. Simulted ripple repect chnge peed r/min in 4. Simulted ripple repect chnge peed r/min in... An FPGA development bord (Alter DE2-70) w ued verify output wveform ix AnAn FPGA development bord DE2-70) w ued verify verify output outputwveform wveform FPGA development bord(alter (Alter DE2-70) w ued rm.an 5development pltform, which included n FPGA crd, wveform witchingbord, FPGA bord (Alter DE2-70) w ued verify output ixix rm. 5 pltform, which included n FPGA crd, witching rm. 5 witching bord pltform, included n FPGA crd, ignl witching n inverter, n AC mor. wwhich ued for ening feedbck for ixbord, rm. 5 pltform, which included n FPGA crd, witching bord, nn inverter, n AC mor. witching bord w ued for ening feedbck ignl inverter, n AC mor. witching bord w ued for ening feedbck ignl ccelerting FPGA crd inverter. 6ening feedbck wveform bord, inverter, nbetween AC mor. witching bord w ued for ignl forn ccelerting between crd inverter. for ccelerting between FPGA FPGA crd inverter. 66 ix uing logicbetween nlyzer. In FPGA crd 6, three complementry witche, U_out forrm ccelerting inverter. 6 wveform In 6, threecomplementry complementry wveform ixixrm rm uing uing logic logic nlyzer. nlyzer. In 6, three D_out, Ub_out Db_out, Uc_out Dc_out, work ded time 3 µ prevent wveform ix rm uing logic nlyzer. In 6, three complementry witche, U_out D_out, Ub_out Db_out, Uc_out Dc_out, work ded time witche, U_out D_out, Ub_out Db_out, Uc_out Dc_out, work ded time hort circuit between upper lower rm. 7 ded time witche, U_out D_out, Ub_out Db_out, lower Uc_out Dc_out, work ded time 3 μ prevent hort circuit between upper rm. 7 3μ prevent hort circuit between upper lower rm. 7 complementry witche. 3ded μtime prevent complementry hort circuit between upper lower rm. 7 time witche. ded complementry witche. ded time complementry witche. 5. Meured pltform, which include n FPGA crd, witching bord, n inverter, n 5. Meured pltform, which include n FPGA crd, witching bord, n inverter, n 5. Meured pltform, which include n FPGA crd, witching bord, n inverter, n AC mor. AC mor. 5. Meured pltform, which include n FPGA crd, witching bord, n inverter, n AC mor. AC mor.

12 Wveform ix ix rm rm logic nlyzer Wveform uing uing logic nlyzer. 6. Wveform ix rm uing logic nlyzer. 6. Wveform ix rm uing logic nlyzer. 7. Meured ded time complementry witche prevent hort circuit between 7. Meured ded time complementry witche prevent hort circuit between upper lower rm. 7. Meured ded time complementry witche prevent hort circuit between upper lower rm. upper lower rm. 8 Meured, i b, generted inverter 7. ded time feedbck complementry witche iprevent hortuing circuit between (ee 8 feedbck, i i b, generted uing inverter (ee ). Notbly, econd output inverter i b w delyed by 20 firt upper lower rm. ). Notbly, econd output inverter i b w delyed by 20 firt output inverter i. 9 experimentl reult 8 feedbck, i ib, generted uing inverter (ee output inverter i experimentl reult feedbck, ifor ib,w generted uing (ee 8 lod output rpm mor peed ). Notbly, econd in inverter ib delyed by 20inverter firt ripple ). lod 000 rpm mor peed in 2verge for i Notbly, econd output inverter b w delyed by firt vried i bout out output inverter i. 9 experimentl reult ripple vried verge i bout 0.2 out output inverter i. 9vried experimentl lod, while ripple.8reult verge Ni mpproximtely lod 000 rpm mor peed in 2 in for lod, vried mor verge while lod t rpm mor peed 2 for ripple lod 000 rpm peed. ripple vried 0.2 mperform 0.35 m 0.35 verge bout 0.2 N m 0.2 out lod, i pproximtely.0n t N lod 000 irpm mor peed. ripple vried 0.2 verge i out electromgnetic mll ripple. 20bout while ripple vried 0.90 N m.8 N m verge i pproximtely electromgnetic perform mll ripple. 20 lod, while ripple vried verge out lod how t rpm 2 t PDTC.0 Nlod mpproximtely t Nin m2 lod mor peed. electromgnetic i.0 t lod 000 lod 000 rpm mor peed. out for Inhow comprion [24], lod in 2 for In comprion [24], PDTC electromgnetic perform mll ripple. 20 perform mll ripple ripple. 22 perform mll ripple. 20mll out perform mll mll 22 out lod 2 how tin PDTC 2 microphogrph ASIC. Tble 5ripple ytem pecifiction lod 2 how t ripple. N m lod for microphogrph ASIC. Tble 5 ytem pecifiction PDTC lod 2 forin In comprion [24], ASIC. in comprion [24], PDTC perform mll ASIC. perform mll ripple mll ripple. 22 ripple mll ripple. 22 microphogrph ASIC. Tble 5 microphogrph ASIC. Tble 5 ytem pecifiction PDTC ytem pecifiction PDTC ASIC. ASIC. 8. Meured feedbck, i ib, inverter. 8. Meured feedbck, i ib, inverter. 8. Meured feedbck, i ib, inverter. 8. Meured feedbck, i ib, inverter.

13 m lod Experimentl reult t N rpm rpm mor mor peed in 2 for peed in 2 for 20. Meured out out lod lod in in 22..

14 Meured t lod in 2 for 2. Meured t lod in 2 for 2. Meured t lod in 2 for 22. Microphogrph PDTC ASIC. 22. Microphogrph PDTC ASIC. 22. Microphogrph PDTC ASIC. Tble 5. Sytem pecifiction ASIC. Tble 5. Sytem pecifiction ASIC. Tble 5.Item Sytem pecifiction Specifiction ASIC. Item Specifiction Technology 0.8 μm P6M CMOS Technology 0.8 μm P6M Supplied Voltge.8 VCMOS Item Specifiction Supplied Voltge.8 V Tet Coverge 96.03% Technology 0.8 µm P6M CMOS Tet Coverge 96.03% Fult Coverge 95.06% Supplied Voltge.8 V Fult Coverge 95.06% Operting Frequency 50 MHz Tet Coverge 96.03% Operting Frequency MHz Power Conumption mw Fult Coverge 95.06% 2 Power Conumption 296 mw Chip Size.8.8 Operting Frequency 50 MHzmm 2 ChipPin Size mm 60 Power Conumption mw Pin Chip Size mm2 Pin 60

15 Concluion Thi tudy n ASIC for PDTC, which involve conventionl DTC, modified predictive clcultion, control. All functionl block were deigned uing Verilog HDL were verified uing n FPGA bord. PDTC reduce ripple in flux hyterei controller by reducing verge witching time, controller help chieve high operting peed high tbility mor control mll dely time. PDTC ASIC help not only clculte tr mgnetic flux by detecting three-phe, three-phe voltge, ror peed, but lo eliminte ripple in flux hyterei controller by uing controller predictive cheme. According imultion reult, PDTC chieved tet coverge 96.03%, fult coverge 95.06%, power conumption 296 mw t n operting frequency 50 MHz upply voltge.8 V. chip re ASIC i.8 mm.8 mm, chip contin pd. Acknowledgment: uthor thnk Ntionl Science Council Republic Chin, Tiwn, for finncilly upporting thi reerch under Contrct No. MOST E We re lo grteful Chip Implementtion Center, Tiwn, for fbricting tet chip. We cknowledge Wllce Acdemic Editing for editing thi mnucript. Author Contribution: Thi tudy w completed by four uthor. G.S. deigned PDTC, completed oreticl nlyi, wrote pper; W.W. conceived deigned experiment; W.L. nlyzed dt urveyed reference; C.Y. completed IC lyout imultion. Conflict Interet: uthor declre no conflict interet. Reference. Li, Y.S.; Chen, J.H. A new pproch direct control induction mor drive for contnt inverter witching frequency ripple reduction. IEEE Trn. Energy Conver. 200, 6, Li, Y.; Ang, K.H.; Chong, G.C.Y. PID control ytem nlyi deign. IEEE Control Syt. Mg. 2006, 26, Wei, W. Deign flux-wekening control ytem PMSM bed on elf-tuning PID controller. In Proceeding Interntionl Conference on Conumer Electronic, Communiction Network (CECNet), XinNing, Chin, 6 8 April 20; pp Geyer, T.; Ppfotiou, G.; Morri, M. Model predictive direct control Prt I: Concept, lgorithm nlyi. IEEE Trn. Ind. Electron. 2009, 56, [CroRef] 5. Ppfotiou, G.; Kley, J.; Ppdopoulo, K.G.; Bohren, P.; Morri, M. Model predictive direct control Prt II: Implementtion experimentl evlution. IEEE Trn. Ind. Electron. 2009, 56, [CroRef] 6. Tkhhi, I.; Noguchi, T. A new quick- high-efficiency control trtegy n induction mor. IEEE Trn. Ind. Appl. 986, IA 22, [CroRef] 7. Prkh, N.S.; Rmch, R. Contnt witching frequency DTC for induction mor fed two level voltge ource inverter. In Proceeding IEEE Interntionl Conference on Power Electronic, Drive Energy Sytem (PEDES), Mumbi, Indi, 6 9 December 204; pp Borhn, H.A.; Vhidi, A. Model predictive control power-plit hybrid electric vehicle combined bttery ultrcpcir energy rge. In Proceeding Americn Control Conference, Bltimore, MD, USA, 30 June 2 July 200; pp Suzuki, K.; Shen, T.; Kko, J.; Yohid, S. Individul A/F etimtion control fuel-g rtio for multicylinder IC engine. IEEE Trn. Veh. Technol. 2009, 58, [CroRef] 0. Bgehwr, V.L.; Jenneret, W.L.; Rjmni, R. Model predictive control trnitionl mneuver for dptive cruie control vehicle. IEEE Trn. Veh. Technol. 2004, 53, [CroRef]. Seren, B.; Diehl, M.; Swever, J. Model predictive control umotive powertrin Firt experimentl reult. In Proceeding 47th IEEE Conference on Deciion Control, Cncun, Mexico, 9 December 2008; pp He, L.; Shen, T.; Yu, L.; Feng, N.; Song, J. A model-predictive-control-bed dem control pproch for prllel hybrid powertrin. IEEE Trn. Veh. Technol. 203, 62, [CroRef]

16 Okumu, H.I. A new controller for direct controlled induction mchine drive. In Proceeding 2th Interntionl Middle-Et Power Sytem Conference, Awn, Egypt, 2 5 My 2008; pp Siv Reddy, Y.V.; Vijy Kumr, M.; Brhmn Reddy, T.; Amrnth, J. Direct control induction mor bed on tte feedbck vrible tructure controller. In Proceeding IEEE Power Indi Conference, New Delhi, Indi, 0 2 April 2006; pp Venktrmn Nik, N.; Singh, S.P. Improved dynmic performnce type-2 bed DTC induction mor uing SVPWM. In Proceeding IEEE Interntionl Conference on Power Electronic, Drive Energy Sytem (PEDES), Bengluru, Krntk, Indi, 6 9 December 202; pp Mei, B.; Liu, H.; Zhng, J. Study control in direct control ytem. In Proceeding Interntionl Conference on Artificil Intelligence Computtionl Intelligence, Shnghi, Chin, 7 8 November 2009; pp Whb, H.F.A.; Snui, H. Simulink model direct control induction mchine. Am. J. Appl. Sci. 2008, 5, Krim, S.; Gdim, S.; Mtib, A.; Mimouni, M.F. Fuzzy peed controller for n induction mor ocited direct control: Implementtion on FPGA. In Proceeding 4th Interntionl Conference on Sytem Control (ICSC), Soue, Tunii, April 205; pp Suriy, T.S.U.; Rni, A.A. Low power nlyi MAC uing modified booth lgorithm. In Proceeding 4th Interntionl Conference on Computing, Communiction Networking Technologie (ICCCNT), Tiruchengode, Indi, 4 6 July 203; pp Wong, K.W.; Tng, W.W. An efficient hdow lgorithm for re light ource uing BSP tree. In Proceeding 6th Pcific Conference on Computer Grphic Appliction, Singpore, Ocber 998; pp Benich, S.; Zidni, F.; Sid, R.N.; Sid, M.S.N. A novel direct control SVM-inverter-fed induction mor drive. In Proceeding 4th Interntionl Conference on Power Engineering, Energy Electricl Drive (POWERENG), Itnbul, Turkey, 3 7 My 203; pp Sutikno, T.; Idri, N.R.N.; Jidin, A.; Cirte, M.N. An improved FPGA implementtion direct control for induction mchine. IEEE Trn. Ind. Inf. 203, 9, [CroRef] 23. Rmmy, S.; Venktrmni, B.; Jgdeewr, S. FPGA implementtion direct control induction mor. In Proceeding Interntionl Conference on Signl Imge Proceing (ICSIP), Chenni, Indi, 5 7 December 200; pp Singh, A.K.; Reddy, C.U.; Prbhkr, K.K.; Kumr, P. FPGA implementtion direct control induction mor reduced ripple in flux. In Proceeding IEEE Interntionl Trnporttion Electrifiction Conference (ITEC), Chenni, Indi, Augut 205; pp by uthor. Licenee MDPI, Bel, Switzerl. Thi rticle i n open cce rticle ditributed under term condition Cretive Common Attribution (CC BY) licene (